diff --git a/.github/scripts/coverage_obligations.py b/.github/scripts/coverage_obligations.py index 7096edd..58bf6cb 100644 --- a/.github/scripts/coverage_obligations.py +++ b/.github/scripts/coverage_obligations.py @@ -1,5 +1,5 @@ #!/usr/bin/env python3 -"""Check the 20 declared behavioral obligations (test/coverage-obligations.json) +"""Check the declared behavioral obligations (test/coverage-obligations.json) have passing evidence in collection and the signed receipt. This is an obligation-presence check, not line or semantic coverage.""" diff --git a/.gitignore b/.gitignore index f2b206b..fa38605 100644 --- a/.gitignore +++ b/.gitignore @@ -18,6 +18,7 @@ docs/HANDOFF.md # Raw per-GPU sweep dumps (regenerate via bench/run_*sweep.sh; distilled results are the tracked *.md) bench/mega_sweep_*.txt +bench/nvt_valid_*.txt bench/warp_block_sweep_*.txt bench/paper_*.txt diff --git a/CHANGELOG.md b/CHANGELOG.md index 63bf618..5945416 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,8 +6,28 @@ All notable changes to GLASS will be documented here. The format follows ## [Unreleased] +### Added + +- `glass::nvidia::thread::` provides one-problem-per-thread cuSOLVERDx + implementations for the supported LAPACK subset. The measured sm_120 and + sm_87 ladders select it only where it clears the native implementation by + the tuning margin. + ### Changed +- **Breaking:** NVIDIA operations now require an explicit execution scope + (`glass::nvidia::block::op`, `glass::nvidia::warp::op`, or + `glass::nvidia::thread::op`); the ambiguous bare `glass::nvidia::op` + re-export is removed. +- **Breaking:** the flat `backend` and `suggested_*` advisor family is replaced + by `glass::recommend()`, which returns one `execution_plan` + containing implementation family, execution scope, and launch packing. + Measured architectures carry paired MathDx and native-only tables. +- **Breaking:** advisor operation names use `op::potrf` and + `op::ldlt_solve`, and rectangular GEMM shape arguments use conventional + `(M,N,K)` order. +- `GLASS_TARGET_SM` is the single architecture selector for native dispatch, + execution plans, and MathDx descriptors; legacy `SMS` remains an input alias. - `glass::block::riccati_gain` reuses the symmetric `P·B` intermediate (`BᵀPA = (PB)ᵀA`), shrinking its shared-scratch requirement from `NU²+NX²` to `NU²+NX·NU` scalars and speeding up the fused gain solve. @@ -18,9 +38,9 @@ All notable changes to GLASS will be documented here. The format follows (numerically identical, fewer barriers per iteration). - Compile-time `ger` uses a flat one-thread-per-output work mapping (bit-identical results by construction). -- Documented-overload coverage is measured per overload contract — 662 +- Documented-overload coverage is measured per overload contract — 665 contracts extracted from Doxygen XML with call-shape evidence - (`test/api-contracts.json`) — instead of per public name, plus 19 declared + (`test/api-contracts.json`) — instead of per public name, plus 21 declared behavioral correctness obligations checked against the signed receipt. - The signed GPU receipt is split into eight dependency-scoped shards with lazy test-binary compilation; development reruns only affected shards, and diff --git a/CLAUDE.md b/CLAUDE.md index 69314ad..d52f1ec 100644 --- a/CLAUDE.md +++ b/CLAUDE.md @@ -21,9 +21,10 @@ documentation, start with `README.md`. block, warp-0, or thread-0 body for measured compile-time cells. - `glass::warp::` owns one problem per full 32-lane warp. - `glass::thread::` owns one problem per thread. It is compile-time-only, - branch-free, and intended for register-resident sizes up to `N <= 7`. -- `glass::nvidia::block::` and `glass::nvidia::warp::` expose vendor-backed - implementations. MathDx is optional; CUB ships with CUDA. + branch-free, and is usually strongest while its operands remain register-resident. +- `glass::nvidia::block::`, `glass::nvidia::warp::`, and + `glass::nvidia::thread::` expose vendor-backed implementations. The thread + surface requires cuSOLVERDx 0.4+; MathDx is optional and CUB ships with CUDA. - `glass::cgrps::` is a cooperative-groups spelling of the block algorithm, not an independently tuned backend. @@ -173,7 +174,7 @@ cd docs && PATH="$(cd .. && pwd)/.venv/bin:$PATH" make all SPHINXOPTS="-W --keep `release.sh` requires a clean `main`, a changelog entry, a complete public-overload manifest (every documented overload compile-covered — an -overload metric, not line coverage), all 20 declared behavioral obligations +overload metric, not line coverage), all 21 declared behavioral obligations passing, a fresh full GPU receipt, and local receipt verification before it tags and pushes. diff --git a/README.md b/README.md index 4f66d9a..b9d025d 100644 --- a/README.md +++ b/README.md @@ -38,19 +38,22 @@ surface inventory. ### Interfaces -GLASS exposes four primary interfaces. Pick one based on how many independent -problems should share a block and whether optional vendor dependencies are -acceptable: +GLASS separates two choices: **execution scope** (thread, warp, or block) and +**implementation family** (dependency-free GLASS code or optional NVIDIA +libraries). Pick a scope based on how many independent problems share a block, +then a family based on availability and measurement: | Interface | Scope | What it is / when to choose it | Header | |-----------|-------|--------------------------------|--------| | `glass::block::` (**Block**) | block | Explicit hand-rolled SIMT implementation; no dependencies and never re-dispatched | `glass.cuh` | | `glass::warp::` (**Warp**) | **warp** | Single-warp SIMT via `__shfl_*_sync` (*selected* L1/L2/L3 ops, no `__syncthreads`). Pack many small independent problems into one block | inline in the base headers (via `glass.cuh`) | -| `glass::thread::` (**Thread**) | **thread** | Sequential branch-free subset, one compile-time problem per thread; intended for register-resident sizes up to `N≤7` | inline in the base headers (via `glass.cuh`) | -| `glass::nvidia::block::` (**Nvidia**) | block | CUB + cuBLASDx + cuSOLVERDx, auto-dispatched against SIMT by size **at compile time** (compile-time sizes). When a vendor tensor-core kernel wins at your size. Plus `glass::nvidia::warp::` — CUB `WarpReduce` L1 reductions, one full 32-lane warp per problem | `glass-nvidia.cuh` | +| `glass::thread::` (**Thread**) | **thread** | Sequential branch-free subset, one compile-time problem per thread; usually register-resident around `N≤7`, but correct and measured beyond that point | inline in the base headers (via `glass.cuh`) | +| `glass::nvidia::block::` (**Nvidia block**) | block | CUB + cuBLASDx + cuSOLVERDx; compile-time-size block implementations and queries | `glass-nvidia.cuh` | +| `glass::nvidia::warp::` (**Nvidia warp**) | warp | CUB `WarpReduce` L1 reductions, one full 32-lane warp per problem | `glass-nvidia.cuh` | +| `glass::nvidia::thread::` (**Nvidia thread**) | thread | cuSOLVERDx 0.4+ LAPACK, one packed problem per CUDA thread; no shared scratch or block barrier | `glass-nvidia.cuh` | -**Bare `glass::op`** (and bare `glass::nvidia::op`) is the **measured-default face**: the -same block-scope calling contract, with the implementation body chosen per (op, size, +**Bare `glass::op`** is the **measured-default face**: the same block-scope +calling contract, with the implementation body chosen per (op, size, dtype) by `glass::dispatch_body()` (`glass-dispatch.cuh`, regenerated by `bench/tune.py --legs body`). This selection is a **`constexpr` decision inside the device function itself** — the compiler resolves each call site to a block, warp-0, or @@ -62,8 +65,28 @@ compile unchanged). Pin `glass::block::` explicitly wherever determinism is load-bearing: **explicit namespace = contract tier, bare namespace = performance tier**. -> **Note:** `glass::cgrps::` (header `glass-cgrps.cuh`) is a convenience cooperative-groups -> *alias* of the Block interface — the same SIMT loop indexed via a +NVIDIA calls always name their scope: `glass::nvidia::block::op`, +`glass::nvidia::warp::op`, or `glass::nvidia::thread::op`. There is no bare +`glass::nvidia::op` alias because those scopes require different launches. + +When a launcher or code generator wants the measured placement, include +`glass-defaults.cuh` and make one query: + +```cpp +constexpr auto plan = glass::recommend( + glass::dependency_set::mathdx); +// plan.implementation, plan.execution_scope, plan.block_threads, +// plan.problems_per_block, plan.shared_bytes +``` + +`recommend()` is host/code-generation metadata, not an implicit dispatcher: +the caller still launches and calls the explicit namespace selected by the +plan. `native_only` is the default dependency set; measured architectures ship +a paired native-only table from the same capture. Family and scope are measured; +the packing fields are ready-to-use legal defaults that callers may retune. + +> **Note:** `glass::cgrps::` (header `glass-cgrps.cuh`) is a cooperative-groups +> *adapter* for the Block interface — the same SIMT loop indexed via a > `cooperative_groups::thread_group`, numerically identical and **not** a separately-tuned > backend. @@ -123,7 +146,9 @@ need NVIDIA MathDx (cuBLASDx / cuSOLVERDx) and extra flags: | `glass-nvidia.cuh` (L2/L3 GEMM/GEMV/batched) | C++17 + `--expt-relaxed-constexpr` + cuBLASDx | | `glass-nvidia.cuh` (LAPACK) | C++17 + `--expt-relaxed-constexpr` + `-rdc=true -dlto -lcusolverdx -lcublas -lcusolver -lcudart` + cuSOLVERDx | -The nvidia wrappers auto-detect availability (`GLASS_HAVE_CUBLASDX` / `GLASS_HAVE_CUSOLVERDX`). +The NVIDIA wrappers auto-detect availability (`GLASS_HAVE_CUBLASDX`, +`GLASS_HAVE_CUSOLVERDX`, and `GLASS_HAVE_CUSOLVERDX_THREAD`; the last requires +cuSOLVERDx 0.4+). Full setup, linking, and the MathDx download are in [`bench/INSTALL.md`](bench/INSTALL.md) and the [installation guide](docs/source/user_guide/getting_started/installation.rst). @@ -164,10 +189,10 @@ The README is a landing page; the deep reference lives in the | Topic | Page | |-------|------| -| API reference (L1 / L2 / L3 / nvidia / warp / banded) | [`api_reference/`](docs/source/api_reference/) | +| API reference (L1 / L2 / L3 / NVIDIA / thread / warp / execution plans / banded) | [`api_reference/`](docs/source/api_reference/) | | Namespaces, naming rules, and the two-axis taxonomy | [`concepts/namespaces.rst`](docs/source/user_guide/concepts/namespaces.rst) | | Choosing a backend + tuning for your hardware | [`concepts/tuning.rst`](docs/source/user_guide/concepts/tuning.rst) | -| `glass::nvidia::gemm` cuBLASDx-vs-SIMT dispatch | [`concepts/backend_dispatch.rst`](docs/source/user_guide/concepts/backend_dispatch.rst) | +| `glass::nvidia::block::gemm` cuBLASDx-vs-SIMT dispatch | [`concepts/backend_dispatch.rst`](docs/source/user_guide/concepts/backend_dispatch.rst) | | `TRAILING_SYNC` and barrier conventions | [`concepts/trailing_sync.rst`](docs/source/user_guide/concepts/trailing_sync.rst) | | Contraction-parallel (`*_reduced`) family | [`concepts/contraction_parallel.rst`](docs/source/user_guide/concepts/contraction_parallel.rst) | | Block-tridiagonal layout (`bdmv` / `pcg`) | [`concepts/block_tridiagonal.rst`](docs/source/user_guide/concepts/block_tridiagonal.rst) | @@ -176,21 +201,23 @@ The README is a landing page; the deep reference lives in the ## Notes / gotchas -- **One block per problem.** Every function runs inside a single block; launch `<<>>`. - Exception: `glass::thread::` is one problem per THREAD (`<<>>`) — for low-DOF - packing (N≲7, compile-time size only). See CLAUDE.md for its constraints. +- **Scope determines placement.** Block forms use one block per problem; warp + forms pack one problem per full warp. `glass::thread::` and + `glass::nvidia::thread::` use one problem per CUDA thread + (`<<>>`). - **Column-major by default** (Fortran order, matching cuBLAS). GEMM uses `TRANSPOSE_A` / `TRANSPOSE_B` + `ROW_MAJOR_C` (a row-major operand is just a transpose); GEMV keeps a - per-matrix `ROW_MAJOR` flag (its transpose changes the math op); `glass::nvidia::` uses the + per-matrix `ROW_MAJOR` flag (its transpose changes the math op); `glass::nvidia::block::` uses the `layout` enum per matrix (`LA`/`LB`/`LC`). - **Reductions are destructive.** `dot` / `nrm2` / reduction variants write the result to `x[0]` and may consume the input as scratch; `nrm2` squares elements before reducing. The `glass::warp::` and `glass::thread::` forms return the value instead; the `glass::nvidia::warp::` (CUB) forms take an explicit per-warp scratch pointer. - `potrf` fills only the **lower triangle**; the upper retains input values. -- `glass::nvidia::*` (default form) requires exactly `gemm_threads()` threads; use the +- `glass::nvidia::block::*` (default form) requires exactly `gemm_threads()` threads; use the `BLOCK_THREADS` template parameter (with `DEFINE_NVIDIA__BLOCKDIM`) to launch any count `≥ gemm_min_block_threads()`. Compile without `-DNDEBUG` for a clean assertion instead of a silent deadlock if the launch is too small. -- `glass::nvidia::trsm` has no native non-1.0 `alpha` (cuSOLVERDx limitation); the wrapper - pre-scales `B` in shared memory before `execute`. +- cuSOLVERDx TRSM has no native non-1.0 `alpha`; both NVIDIA wrappers pre-scale + `B` before `execute` (in shared memory at block scope, in the owning thread at + thread scope). diff --git a/bench/INSTALL.md b/bench/INSTALL.md index 3b2c303..ca071d8 100644 --- a/bench/INSTALL.md +++ b/bench/INSTALL.md @@ -11,7 +11,7 @@ benches. All three are auto-detected by `bench/run_bench.py`. | Library | Required for | Header-only? | |---------|-------------|--------------| -| CUB | `bench_reduce` (CUB baseline + `glass::nvidia::reduce` variant) | Yes (bundled with CUDA) | +| CUB | `bench_reduce` (CUB baseline + `glass::nvidia::block::reduce`) | Yes (bundled with CUDA) | | cuBLASDx | `bench_gemv`, `bench_gemm`, `bench_blockdim`, `bench_gemm_batched`, `bench_lapack` | Yes | | cuSOLVERDx | `bench_lapack` (Cholesky / TRSM / posv / etc.) | **No** — links a precompiled device fatbin | @@ -41,8 +41,9 @@ portal. (Free NVIDIA Developer account required.) 2. Choose: **MathDx for CUDA 12, Linux x86_64** (`.tar.gz` format). - Version 25.12.x or later is recommended (this is the version the GLASS - wrappers are tested against). + Version 25.12.x or later supports the block wrappers. Use **26.03 or later** + for `glass::nvidia::thread::` (cuSOLVERDx 0.4+); the thread correctness suite + is validated against 26.03. ### Install @@ -54,7 +55,7 @@ tar -xzf MathDx_*.tar.gz -C /opt ls /opt/nvidia/mathdx/ # Set the environment variable (add to ~/.bashrc to persist) -export MATHDX_ROOT=/opt/nvidia/mathdx/25.12 # adjust version as needed +export MATHDX_ROOT=/opt/nvidia/mathdx/26.03 # adjust version as needed ``` ### Verify diff --git a/bench/JETSON.md b/bench/JETSON.md index 78ff95c..04413bd 100644 --- a/bench/JETSON.md +++ b/bench/JETSON.md @@ -4,7 +4,8 @@ One capture per box (Orin AGX / Orin NX / Orin Nano — all `sm_87`). Each run produces a single `bench/jetson__.tar.gz` containing the timings plus a full device/JetPack provenance bundle; send those back for ingestion (figure columns + the `ideal_sm87` ladder table, spliced off-box via -`tune.py --from-ladder --sm 870`). +`tune.py --from-ladder --from-nvt-valid --sm 870` when MathDx is available; +native-only captures need no confirmation companion). ## 0. Pre-flight: get on the latest JetPack the box supports @@ -124,7 +125,8 @@ methodology). The script: | Capture | Feeds | |---|---| -| `mega_sweep_*.txt` | `ideal_sm87` ladder table (spliced on the desktop via `python bench/tune.py --from-ladder --sm 870 --allow-no-mathdx`), paper §portability "which crossovers moved" | +| `mega_sweep_*.txt` | `ideal_sm87` ladder table. Full MathDx replay: `python bench/tune.py --sm 870 --legs ladder --from-ladder --from-nvt-valid `; a native-only capture needs only `--from-ladder --allow-no-mathdx`. | +| `nvt_valid_*.txt` | Required valid-input veto companion when the ladder selects NVIDIA thread; pass it with `--from-nvt-valid` during off-box regeneration. | | `paper_hostblas_*.txt` | Jetson columns for the hostblas + latency figures | | `paper_fusion_*.txt` | Jetson fusion curves | | `robotics_sweep_*.txt` | Jetson robotics tier panels | diff --git a/bench/RESULTS.md b/bench/RESULTS.md index e7369f7..99dd42e 100644 --- a/bench/RESULTS.md +++ b/bench/RESULTS.md @@ -18,19 +18,28 @@ labor (2026-08-11 consolidation): is current only when its source digest, environment, timing date, and proximate signed correctness receipt are recorded together. -## ladder (mega sweep — thread/warp/block/nvidia) - -The shipped `ideal_sm120` table was re-gated 2026-08-15 from the pinned quiet -capture `mega_sweep_20260815_205919.txt` (archived externally), taken with the -drift-fixed v2 harness (untimed per-trial input reset in `timing_common.cuh`); -it is the cleanest capture recorded (40/396 rows jitter-flagged, each verified -cell-by-cell at re-gate). Earlier captures (3-way 2026-06-23, 4-way thread -tier 2026-07-19) are superseded for table generation. sm_87 (Jetson Orin, -three power modes, byte-identical tables) landed 2026-08-03. Ladder analysis, -thread-tier verdict tables, and figures live on the docs site; the -winner-per-(op,N) table renders from `docs/source/_static/sweep_winners.txt`. - -## blas2 (warp vs block for syrk/syr2k/ldlt/ldltsv/inv/trmv/ger) +## ladder (mega sweep — native thread/warp/block plus NVIDIA block/thread) + +The shipped tables were regenerated 2026-08-30 after adding cuSOLVERDx's +thread-per-problem LAPACK interface as a fifth contender. The sm_120 table uses +the independent 500-repetition throughput capture +`mega_sweep_20260830_042156.txt`; the three-regime figures use +`mega_sweep_20260830_025517.txt`. Their raw ladder policy winners agree in +131/132 cells and in all 17 pre-veto NVIDIA-thread cells. The shipped sm_120 +table then applies `nvt_valid_20260830_160047.txt`, retaining 14 of those +cells after every timed launch receives an independent valid system. The +sm_87 table uses the pinned-50-W Tegra +profile capture `mega_sweep_orin_tegra_20260830_035819.txt`; a separate +oversampled low-batch capture supplies its NPROB=64 characterization, and +`nvt_valid_sm87_20260830_160506.txt` retains 15 of 19 NVIDIA-thread ladder +winners. Raw +captures and SHA-256 pins are archived with the paper materials. Earlier +three- and four-way captures remain historical evidence but are superseded for +ladder table generation. Current analysis and figures live on the docs site; +the winner-per-(op,N) table renders from +`docs/source/_static/sweep_winners.txt`. + +## blas2 (warp vs block for syrk/syr2k/ldlt/ldlt_solve/inv/trmv/ger) Ops the ladder misses. No nvidia counterparts (2-way); inv/trmv/ger are block-only (reported, never picked). The 2-impl ops regenerate the shipped @@ -41,7 +50,7 @@ per-arch `blas2_sm*` table in glass-defaults.cuh (since 2026-08-06). _Source: `blas2_sweep_20260814_011659.txt` · NPROB=8192 ns/problem · margin ±5% (warp/block are both dependency-free; pick = cheapest, note flags sub-margin gaps) · warp picked in 30 of 154 cells._ -inv/trmv/ger are BLOCK-ONLY (no `glass::warp::` variant, so nothing competes — reported, never picked); none of these ops has a `glass::nvidia::` counterpart. The 2-impl ops (syrk/syr2k/ldlt/ldltsv) regenerate the shipped per-arch `blas2_sm*` table in glass-defaults.cuh (since 2026-08-06). +inv/trmv/ger are BLOCK-ONLY (no `glass::warp::` variant, so nothing competes — reported, never picked); none of these ops has an NVIDIA counterpart. The 2-impl ops (syrk/syr2k/ldlt/ldlt_solve) regenerate the shipped per-arch `blas2_sm*` table in glass-defaults.cuh (since 2026-08-06). | op | shape | dtype | block ns | warp ns | pick | note | |----|-------|-------|----------|---------|------|------| @@ -111,28 +120,28 @@ inv/trmv/ger are BLOCK-ONLY (no `glass::warp::` variant, so nothing competes — | ldlt | N=96 | f64 | 1022.24 | 1075.16 | **block** | block wins (1022.240 vs warp 1075.160, 5.2%) | | ldlt | N=128 | f32 | 665.47 | 807.69 | **block** | block wins (665.470 vs warp 807.690, 21.4%) | | ldlt | N=128 | f64 | 2038.77 | 2462.17 | **block** | block wins (2038.770 vs warp 2462.170, 20.8%) | -| ldltsv | N=4 | f32 | 0.73 | 0.58 | **warp** | warp wins (0.580 vs block 0.730, 25.9%) | -| ldltsv | N=4 | f64 | 2.98 | 4.39 | **block** | block wins (2.980 vs warp 4.390, 47.3%) | -| ldltsv | N=6 | f32 | 1.43 | 1.02 | **warp** | warp wins (1.020 vs block 1.430, 40.2%) | -| ldltsv | N=6 | f64 | 5.76 | 7.61 | **block** | block wins (5.760 vs warp 7.610, 32.1%) | -| ldltsv | N=8 | f32 | 2.13 | 1.54 | **warp** | warp wins (1.540 vs block 2.130, 38.3%) | -| ldltsv | N=8 | f64 | 8.56 | 11.34 | **block** | block wins (8.560 vs warp 11.340, 32.5%) | -| ldltsv | N=12 | f32 | 3.92 | 2.83 | **warp** | warp wins (2.830 vs block 3.920, 38.5%) | -| ldltsv | N=12 | f64 | 16.02 | 20.66 | **block** | block wins (16.020 vs warp 20.660, 29.0%) | -| ldltsv | N=16 | f32 | 5.81 | 4.43 | **warp** | warp wins (4.430 vs block 5.810, 31.2%) | -| ldltsv | N=16 | f64 | 26.48 | 32.44 | **block** | block wins (26.480 vs warp 32.440, 22.5%) | -| ldltsv | N=24 | f32 | 10.87 | 8.82 | **warp** | warp wins (8.820 vs block 10.870, 23.2%) | -| ldltsv | N=24 | f64 | 54.94 | 63.42 | **block** | block wins (54.940 vs warp 63.420, 15.4%) | -| ldltsv | N=32 | f32 | 19.77 | 15.91 | **warp** | warp wins (15.910 vs block 19.770, 24.3%) | -| ldltsv | N=32 | f64 | 94.23 | 104.42 | **block** | block wins (94.230 vs warp 104.420, 10.8%) | -| ldltsv | N=48 | f32 | 52.09 | 48.92 | **warp** | warp wins (48.920 vs block 52.090, 6.5%) | -| ldltsv | N=48 | f64 | 223.69 | 243.07 | **block** | block wins (223.690 vs warp 243.070, 8.7%) | -| ldltsv | N=64 | f32 | 105.38 | 103.67 | **warp** | warp wins (103.670 vs block 105.380, 1.6%) | -| ldltsv | N=64 | f64 | 416.28 | 444.67 | **block** | block wins (416.280 vs warp 444.670, 6.8%) | -| ldltsv | N=96 | f32 | 300.68 | 321.69 | **block** | block wins (300.680 vs warp 321.690, 7.0%) | -| ldltsv | N=96 | f64 | 1047.14 | 1097.29 | **block** | block wins (1047.140 vs warp 1097.290, 4.8%) | -| ldltsv | N=128 | f32 | 734.13 | 863.41 | **block** | block wins (734.130 vs warp 863.410, 17.6%) | -| ldltsv | N=128 | f64 | 2050.26 | 2534.78 | **block** | block wins (2050.260 vs warp 2534.780, 23.6%) | +| ldlt_solve | N=4 | f32 | 0.73 | 0.58 | **warp** | warp wins (0.580 vs block 0.730, 25.9%) | +| ldlt_solve | N=4 | f64 | 2.98 | 4.39 | **block** | block wins (2.980 vs warp 4.390, 47.3%) | +| ldlt_solve | N=6 | f32 | 1.43 | 1.02 | **warp** | warp wins (1.020 vs block 1.430, 40.2%) | +| ldlt_solve | N=6 | f64 | 5.76 | 7.61 | **block** | block wins (5.760 vs warp 7.610, 32.1%) | +| ldlt_solve | N=8 | f32 | 2.13 | 1.54 | **warp** | warp wins (1.540 vs block 2.130, 38.3%) | +| ldlt_solve | N=8 | f64 | 8.56 | 11.34 | **block** | block wins (8.560 vs warp 11.340, 32.5%) | +| ldlt_solve | N=12 | f32 | 3.92 | 2.83 | **warp** | warp wins (2.830 vs block 3.920, 38.5%) | +| ldlt_solve | N=12 | f64 | 16.02 | 20.66 | **block** | block wins (16.020 vs warp 20.660, 29.0%) | +| ldlt_solve | N=16 | f32 | 5.81 | 4.43 | **warp** | warp wins (4.430 vs block 5.810, 31.2%) | +| ldlt_solve | N=16 | f64 | 26.48 | 32.44 | **block** | block wins (26.480 vs warp 32.440, 22.5%) | +| ldlt_solve | N=24 | f32 | 10.87 | 8.82 | **warp** | warp wins (8.820 vs block 10.870, 23.2%) | +| ldlt_solve | N=24 | f64 | 54.94 | 63.42 | **block** | block wins (54.940 vs warp 63.420, 15.4%) | +| ldlt_solve | N=32 | f32 | 19.77 | 15.91 | **warp** | warp wins (15.910 vs block 19.770, 24.3%) | +| ldlt_solve | N=32 | f64 | 94.23 | 104.42 | **block** | block wins (94.230 vs warp 104.420, 10.8%) | +| ldlt_solve | N=48 | f32 | 52.09 | 48.92 | **warp** | warp wins (48.920 vs block 52.090, 6.5%) | +| ldlt_solve | N=48 | f64 | 223.69 | 243.07 | **block** | block wins (223.690 vs warp 243.070, 8.7%) | +| ldlt_solve | N=64 | f32 | 105.38 | 103.67 | **warp** | warp wins (103.670 vs block 105.380, 1.6%) | +| ldlt_solve | N=64 | f64 | 416.28 | 444.67 | **block** | block wins (416.280 vs warp 444.670, 6.8%) | +| ldlt_solve | N=96 | f32 | 300.68 | 321.69 | **block** | block wins (300.680 vs warp 321.690, 7.0%) | +| ldlt_solve | N=96 | f64 | 1047.14 | 1097.29 | **block** | block wins (1047.140 vs warp 1097.290, 4.8%) | +| ldlt_solve | N=128 | f32 | 734.13 | 863.41 | **block** | block wins (734.130 vs warp 863.410, 17.6%) | +| ldlt_solve | N=128 | f64 | 2050.26 | 2534.78 | **block** | block wins (2050.260 vs warp 2534.780, 23.6%) | | inv | N=4 | f32 | 0.71 | — | **block** | block only impl measured (0.710) | | inv | N=4 | f64 | 1.44 | — | **block** | block only impl measured (1.440) | | inv | N=6 | f32 | 1.12 | — | **block** | block only impl measured (1.120) | @@ -207,7 +216,8 @@ inv/trmv/ger are BLOCK-ONLY (no `glass::warp::` variant, so nothing competes — Tall/wide gemv + rectangular gemm shapes (consumers' Jacobians are rectangular; the ladder is square-only). nvidia leg skipped — per-shape cuBLASDx decisions live in the `shapes` leg. Measured shapes regenerate the -shipped exact-shape `rect_*_sm*` pickers (`suggested_backend_rect_gemv/gemm<>`). +shipped exact-shape `rect_*_sm*` pickers (publicly queried through +`recommend`). > ⚠ **2026-08-11 audit:** the 2026-07-18 capture below predates > `bench_rect`'s launch-FAIL guard; its five `warp 0.04 ns` gemm cells @@ -221,7 +231,7 @@ shipped exact-shape `rect_*_sm*` pickers (`suggested_backend_rect_gemv/gemm<>`). _Source: `rect_sweep_20260814_031430.txt` · NPROB=8192 ns/problem · margin ±5% (warp/block are both dependency-free; pick = cheapest, note flags sub-margin gaps) · warp picked in 16 of 24 cells._ -nvidia leg skipped for rectangular shapes (needs new per-shape DEFINE_NVIDIA_* machinery; cuBLASDx-vs-SIMT per (M,N,K) lives in the `shapes` leg). Measured shapes regenerate the shipped exact-shape `rect_*_sm*` pickers in glass-defaults.cuh (`suggested_backend_rect_gemv/gemm<>`, since 2026-08-06); unmeasured shapes stay block. +nvidia leg skipped for rectangular shapes (needs new per-shape DEFINE_NVIDIA_* machinery; cuBLASDx-vs-SIMT per (M,N,K) lives in the `shapes` leg). Measured shapes regenerate the shipped exact-shape `rect_*_sm*` pickers in glass-defaults.cuh (`recommend`, since 2026-08-06); unmeasured shapes stay block. | op | shape | dtype | block ns | warp ns | pick | note | |----|-------|-------|----------|---------|------|------| @@ -290,7 +300,7 @@ bdsv is faster in 1 of 12 cells **on this well-conditioned test system at PCG's posv (Cholesky) is the intended SPD path; gesv prices the pivoted-LU robustness fallback, inv+gemv the invert-then-multiply anti-pattern. -The `thr-posv` column is the **thread-tier** `glass::thread::posv` (one problem per thread, 32 packed per warp) — measured only below the N<=7 register-residency ceiling. Where `thr/posv` < 1 the thread tier beats the block Cholesky solve on that low-DOF shape. +The `thr-posv` column is the **thread-tier** `glass::thread::posv` (one problem per thread, 32 packed per warp) — measured here only in the register-resident low-DOF band. Where `thr/posv` < 1 the thread tier beats the block Cholesky solve on that shape. | N | dtype | gesv ns | posv ns | inv+gemv ns | thr-posv ns | gesv/posv | inv/posv | thr/posv | |---|-------|---------|---------|-------------|-------------|-----------|----------|----------| @@ -339,12 +349,12 @@ _Source: `reduced_sweep_20260814_011659.txt` · tie margin ±5% (reduced must cl | f64 | 4 | 4 | 64 | 256 | 128 | 1.9115 | 1.3604 | **1.41** | | f64 | 4 | 4 | 64 | 256 | 256 | 1.9163 | 0.9705 | **1.97** | -Predicate `suggested_use_reduced()` = `false` on every cell (K_contract is the N column here). +The public advisor stays two-axis; reduced GEMM remains an explicit opt-in. -⚠️ **2 config(s) disagree** with the predicate — review before trusting the formula on this GPU: +⚠️ **2 config(s) favor the explicit reduced variant while the conservative plan stays standard:** -- f64 4×4×64 bd=128 (n_out=256): measured **reduced**, predicate **serial** -- f64 4×4×64 bd=256 (n_out=256): measured **reduced**, predicate **serial** +- f64 4×4×64 bd=128 (n_out=256): measured **reduced**, plan **serial** +- f64 4×4×64 bd=256 (n_out=256): measured **reduced**, plan **serial** diff --git a/bench/TUNING.md b/bench/TUNING.md index 9153172..bb7bc20 100644 --- a/bench/TUNING.md +++ b/bench/TUNING.md @@ -2,14 +2,15 @@ ## One command — `bench/tune.py` -GLASS ships three measured defaults tables: the thread/warp/block/nvidia **backend -ladder** (`glass-defaults.cuh`, consumed by `glass::suggested_backend<>`; the +GLASS ships measured execution plans and implementation tables. The native and NVIDIA +thread/warp/block **backend ladder** (`glass-defaults.cuh`, consumed by +`glass::recommend<>`; the tables are **per-arch** — the ladder leg replaces the marker block + dispatch case for the arch it measured, so a first-time GPU like a Jetson Orin gains an `ideal_sm87` alongside the shipped `ideal_sm120` instead of overwriting it), the per-(M,N,K) **cuBLASDx-vs-SIMT table** (`src/nvidia/tuning_table.cuh`, this -document's main subject), and the serial-vs-reduced **`suggested_use_reduced<>`** -predicate. `bench/tune.py` remeasures all of them on your GPU and regenerates +document's main subject), plus serial-vs-reduced characterization. +`bench/tune.py` remeasures all of them on your GPU and regenerates them under **one shared noise margin**, so nothing bakes sub-noise jitter: ```bash @@ -59,23 +60,23 @@ needed), prebuild-cached like the others, and route every verdict through the same `tune_pick` margin rule: - **`blas2`** (`bench/bench_blas2.cu`) — warp-vs-block for `syrk`, `syr2k`, - `ldlt`, `ldltsv` (factor+solve), `inv` (augmented `[A|I]` Gauss-Jordan), + `ldlt`, `ldlt_solve` (factor+solve), `inv` (augmented `[A|I]` Gauss-Jordan), `trmv`, `ger` over the ladder's square-N set, f32+f64. `inv`/`trmv`/`ger` are block-only (no `warp::` variant); none of these ops has a `glass::nvidia::` counterpart, so there is no vendor column. - **`rect`** (`bench/bench_rect.cu`) — warp-vs-block for rectangular `gemv` (tall 64×8/128×16/256×32, wide 8×64/16×128/32×256) and `gemm` - ((M,K,N) ∈ {(32,8,32),(8,32,8),(64,16,16),(16,64,16),(6,6,64),(64,6,6)}). + ((M,N,K) ∈ {(32,32,8),(8,8,32),(64,16,16),(16,16,64),(6,64,6),(64,6,6)}). The nvidia leg is skipped (rectangular cuBLASDx forcing would need new `DEFINE_NVIDIA_*` instantiation machinery; per-shape vendor decisions belong to the `shapes` leg). Since 2026-08-06 both legs regenerate shipped header tables alongside their md reports: `blas2` splices a per-arch `blas2_sm*` block into -`glass-defaults.cuh` for the 2-impl ops (syrk/syr2k/ldlt/ldltsv — reachable -through the ordinary `suggested_backend<>`; inv/trmv/ger are single-impl and +`glass-defaults.cuh` for the 2-impl ops (syrk/syr2k/ldlt/ldlt_solve — reachable +through the ordinary `recommend<>`; inv/trmv/ger are single-impl and stay report-only), and `rect` splices exact-shape `rect_gemv_sm*` / -`rect_gemm_sm*` pickers (public face `suggested_backend_rect_gemv/gemm<>`; +`rect_gemm_sm*` pickers (public face `recommend`; unmeasured shapes and arches fall to block). Offline hooks `--from-blas2 ` / `--from-rect ` regenerate from an existing sweep capture without touching the GPU (pass `--sm` to name the capture's arch): @@ -103,7 +104,8 @@ The direct-vs-PCG table is an approximate-solve comparison at PCG's configured Prebuild-cached like the other legs; offline hook `--from-solvers `. The shared rule (`bench/tune_pick.py::pick`): a dependency-carrying impl -(`nvidia`/`cublasdx`/`reduced`) wins **only if it beats the simplest impl by more +(`nvidia`/`nvidia_thread`/`cublasdx`/`reduced`) wins **only if it beats the +best dependency-free impl by more than the margin** — otherwise the no-dependency path (always launchable, no MathDx) stays. Between the SIMT tiers themselves, any tier within the **±2% SIMT tie band** of the fastest takes the cell if it is simpler (thread ≻ warp @@ -121,7 +123,7 @@ the documented workaround for a CUDA 12.9 ptxas failure on cuBLASDx/cuSOLVERDx TUs (it also damps dead-store elimination of benchmark outputs). The ladder-family harnesses (`ladder`, `blas2`, `rect`, `solvers`) keep those same flags even in SIMT-only builds, so every contender feeding -the `suggested_backend<>` tables is measured under ONE flag set regardless +the `recommend<>` tables is measured under ONE flag set regardless of whether the nvidia tier is present. The `body` and `reduced` legs and the characterization drivers (`perf_sweeps.py`, `paper_sweeps.py`, and `run_bench.py`'s non-MathDx builds) compile at plain `-O3`, matching @@ -166,11 +168,20 @@ The ladder-grammar harnesses share one measurement core busy GPU and invalidates a leg if a foreign compute PID appears after start. Correctness stays a separate gate; a timing capture does not promote peer agreement into a numerical oracle. -- **Mutation invariant**: reps run with no restore in the timed region, so +- **Mutation invariant**: the main ladder's reps run with no restore in the timed region, so in-place ops re-factor their own output from rep 2 on. This is - timing-benign only for branch-free, data-independent ops (everything - currently laddered; GPU NaN/denormal arithmetic is full-speed). Never time - a `CHECK`-gated or pivoted op through this loop. + suitable for branch-free steady-throughput characterization, but it is not + sufficient evidence for a solver default. Every main-ladder + `nvidia_thread` winner is therefore remeasured by `bench_nvt_valid.cu` + against native thread/warp/block using a bounded ring of independent valid + systems (one per timed launch; initialization untimed). It must clear the + same 5% margin or `tune.py` vetoes it to the valid-input native winner. + Missing confirmation fails regeneration, and the confirmation leg never + promotes a vendor path. The capture records each contender's three-trial + spread; if the observed min-to-max intervals overlap the 5% decision + boundary, regeneration fails closed instead of treating the nominal minima + as a verdict. Never use the main loop alone for a `CHECK`-gated, + pivoted, or other data-dependent op. - **Decisions absorb residual noise**: the 5% dependency margin, the ±2% SIMT tie band, and the `noise_floor` override (sub-granularity cells refuse to resolve a margin) all live in `tune_pick.py` — measured 4× on Jetson Orin @@ -196,7 +207,7 @@ python bench/perf_sweeps.py --arch sm_120 --profile overnight # release confirm ## The cuBLASDx-vs-SIMT table -GLASS's `glass::nvidia::*` wrappers — `gemm`, `gemv`, `row_strided_*`, +GLASS's `glass::nvidia::block::*` wrappers — `gemm`, `gemv`, `row_strided_*`, `gemm_batched_1d` — auto-dispatch between a pure-SIMT path and cuBLASDx at compile time. The decision lives in `src/nvidia/query_simt.cuh::should_use_cublasdx*<>()` and consults, in order: @@ -213,7 +224,7 @@ specialized independently for a given (shape, SM). ## Why bother? -A representative measurement (RTX 3080, sm_120): +A representative measurement (RTX 5090, sm_120): | Shape | Heuristic says | Measured winner | Speedup | |----------------|----------------|-----------------|---------| @@ -301,10 +312,10 @@ Use the per-API `print_dispatch_*` host helpers from `query_simt.cuh`: #include "glass-nvidia.cuh" int main() { - glass::nvidia::print_dispatch(); - // → "glass::nvidia::gemm: SIMT fallback" - glass::nvidia::print_dispatch_gemv(); - // → "glass::nvidia::gemv: cuBLASDx (needs DEFINE_NVIDIA_GEMV*)" + glass::nvidia::block::print_dispatch(); + // → "glass::nvidia::block::gemm: SIMT fallback" + glass::nvidia::block::print_dispatch_gemv(); + // → "glass::nvidia::block::gemv: cuBLASDx" } ``` diff --git a/bench/autotune.py b/bench/autotune.py index f0c12cd..1ca46ec 100755 --- a/bench/autotune.py +++ b/bench/autotune.py @@ -150,7 +150,7 @@ def _cublasdx_wins(simt, cdx, margin): __global__ void k_cublasdx(float* A, float* B, float* C, volatile float* sink, int iters) {{ extern __shared__ __align__(16) char smem[]; for (int rep = 0; rep < iters; rep++) {{ - glass::nvidia::gemm(1.f, A, B, 0.f, C, smem); + glass::nvidia::block::gemm(1.f, A, B, 0.f, C, smem); __syncthreads(); if (threadIdx.x == 0) sink[rep & 0xFF] = C[0]; __syncthreads(); @@ -164,7 +164,7 @@ def _cublasdx_wins(simt, cdx, margin): cudaMalloc(&dB, N*K * sizeof(float)); cudaMalloc(&dC, M*K * sizeof(float)); cudaMalloc(&dSink, 256 * sizeof(float)); - constexpr size_t smem = glass::nvidia::gemm_scratch_bytes(); + constexpr size_t smem = glass::nvidia::block::gemm_scratch_bytes(); k_simt<<<1, TC>>>(dA, dB, dC, dSink, 100); bool simt_ok = !leg_failed("simt"); @@ -207,7 +207,7 @@ def _cublasdx_wins(simt, cdx, margin): __global__ void k_cublasdx(float* A, float* x, float* y, volatile float* sink, int iters) {{ extern __shared__ __align__(16) char smem[]; for (int rep = 0; rep < iters; rep++) {{ - glass::nvidia::gemv(1.f, A, x, 0.f, y, smem); + glass::nvidia::block::gemv(1.f, A, x, 0.f, y, smem); __syncthreads(); if (threadIdx.x == 0) sink[rep & 0xFF] = y[0]; __syncthreads(); @@ -221,7 +221,7 @@ def _cublasdx_wins(simt, cdx, margin): cudaMalloc(&dx, N * sizeof(float)); cudaMalloc(&dy, M * sizeof(float)); cudaMalloc(&dSink, 256 * sizeof(float)); - constexpr size_t smem = glass::nvidia::gemv_scratch_bytes(); + constexpr size_t smem = glass::nvidia::block::gemv_scratch_bytes(); k_simt<<<1, TC>>>(dA, dx, dy, dSink, 100); bool simt_ok = !leg_failed("simt"); @@ -266,7 +266,7 @@ def _cublasdx_wins(simt, cdx, margin): __global__ void k_cublasdx(float* A, float* x, float* y, volatile float* sink, int iters) {{ extern __shared__ __align__(16) char smem[]; for (int rep = 0; rep < iters; rep++) {{ - glass::nvidia::gemv_strided(1.f, A, x, 0.f, y, smem); + glass::nvidia::block::gemv_strided(1.f, A, x, 0.f, y, smem); __syncthreads(); if (threadIdx.x == 0) sink[rep & 0xFF] = y[0]; __syncthreads(); @@ -281,7 +281,7 @@ def _cublasdx_wins(simt, cdx, margin): cudaMalloc(&dy, M * sizeof(float)); cudaMalloc(&dSink, 256 * sizeof(float)); constexpr size_t smem = - glass::nvidia::gemv_strided_scratch_bytes(); + glass::nvidia::block::gemv_strided_scratch_bytes(); k_simt<<<1, TC>>>(dA, dx, dy, dSink, 100); bool simt_ok = !leg_failed("simt"); @@ -328,7 +328,7 @@ def _cublasdx_wins(simt, cdx, margin): __global__ void k_cublasdx(float* A, float* B, float* C, volatile float* sink, int iters) {{ extern __shared__ __align__(16) char smem[]; for (int rep = 0; rep < iters; rep++) {{ - glass::nvidia::gemm_strided(1.f, A, B, 0.f, C, smem); + glass::nvidia::block::gemm_strided(1.f, A, B, 0.f, C, smem); __syncthreads(); if (threadIdx.x == 0) sink[rep & 0xFF] = C[0]; __syncthreads(); @@ -343,7 +343,7 @@ def _cublasdx_wins(simt, cdx, margin): cudaMalloc(&dC, M * K * sizeof(float)); cudaMalloc(&dSink, 256 * sizeof(float)); constexpr size_t smem = - glass::nvidia::gemm_strided_scratch_bytes(); + glass::nvidia::block::gemm_strided_scratch_bytes(); k_simt<<<1, TC>>>(dA, dB, dC, dSink, 100); bool simt_ok = !leg_failed("simt"); @@ -366,8 +366,8 @@ def _cublasdx_wins(simt, cdx, margin): # ───── gemm_batched_1d ────────────────────────────────────────────────────── -# Compares the 1D SIMT batched (glass::nvidia::gemm_batched_1d) against the -# 2D cuBLASDx batched (glass::nvidia::gemm_batched). The launches differ +# Compares the 1D SIMT batched (glass::nvidia::block::gemm_batched_1d) against +# the 2D cuBLASDx batched (glass::nvidia::block::gemm_batched). The launches differ # (1D = TC*BATCH threads; 2D = dim3(TC, BATCH)). The autotune still picks the # faster wall-time per op — that's what cublasdx_wins_batched<> answers. _GEMM_BATCHED_MICROBENCH = _BENCH_PREAMBLE + textwrap.dedent(""" @@ -387,7 +387,7 @@ def _cublasdx_wins(simt, cdx, margin): __global__ void k_simt(float** As, float** Bs, float** Cs, volatile float* sink, int iters) {{ for (int rep = 0; rep < iters; rep++) {{ - glass::nvidia::gemm_batched_1d( + glass::nvidia::block::gemm_batched_1d( 1.f, As, Bs, 0.f, Cs); __syncthreads(); if (threadIdx.x == 0) sink[rep & 0xFF] = Cs[0][0]; @@ -399,7 +399,7 @@ def _cublasdx_wins(simt, cdx, margin): volatile float* sink, int iters) {{ extern __shared__ __align__(16) char smem[]; for (int rep = 0; rep < iters; rep++) {{ - glass::nvidia::gemm_batched( + glass::nvidia::block::gemm_batched( 1.f, As, Bs, 0.f, Cs, smem); __syncthreads(); if (threadIdx.x == 0 && threadIdx.y == 0) sink[rep & 0xFF] = Cs[0][0]; @@ -432,7 +432,7 @@ def _cublasdx_wins(simt, cdx, margin): cudaMemcpy(dBs, hBs, BATCH * sizeof(float*), cudaMemcpyHostToDevice); cudaMemcpy(dCs, hCs, BATCH * sizeof(float*), cudaMemcpyHostToDevice); constexpr size_t smem = - glass::nvidia::gemm_batched_scratch_bytes(); + glass::nvidia::block::gemm_batched_scratch_bytes(); // SIMT batched_1d launches 1D with BTC*BATCH threads, ptr-array args. k_simt<<<1, BTC * BATCH>>>(dAs, dBs, dCs, dSink, 100); @@ -613,7 +613,7 @@ def build_shape(api, shape, sms, mathdx_root, build_dir): f"-I{GLASS_DIR}", f"-I{GLASS_DIR / 'src'}", f"-I{mathdx_root / 'include'}", f"-I{mathdx_root / 'external' / 'cutlass' / 'include'}", - "-DGLASS_BENCH_CUBLASDX", f"-DSMS={sms}", + "-DGLASS_BENCH_CUBLASDX", f"-DGLASS_TARGET_SM={sms}", "--expt-relaxed-constexpr", "-Xptxas", "-O1", "-o", str(bin_path), str(src_path), ] @@ -814,34 +814,26 @@ def emit_results_md(md_path: pathlib.Path, # ─── main ─────────────────────────────────────────────────────────────────── -def emit_defaults_table(sweep_path, out_path, sms): +def emit_defaults_table(sweep_path, out_path, sms, margin=0.05): """Parse a bench_mega_sweep run (mega_sweep_*.txt) and emit a per-host override - header for glass-defaults.cuh (the warp/block/nvidia ladder). Uses the NPROB=8192 + header for glass-defaults.cuh (native plus NVIDIA block/thread ladder). Uses the NPROB=8192 throughput regime for f32 + f64.""" - import re text = pathlib.Path(sweep_path).read_text() - bemap = {"BLOCK": "block", "WARP": "warp", "NVIDIA": "nvidia"} - line_re = re.compile(r"^(dot|gemv|gemm|chol|trsv|posv)\s+N=(\d+)\b.*->\s+(BLOCK|WARP|NVIDIA)\b") - hdr_re = re.compile(r"NPROB=(\d+).*dtype=(f32|f64)") - winners = {} # (dtype, op) -> {N: backend} - dtype, nprob = None, None - for line in text.splitlines(): - if line.startswith("####"): - m = hdr_re.search(line) - if m: - nprob, dtype = int(m.group(1)), m.group(2) - continue - if nprob != 8192: - continue - lm = line_re.match(line.strip()) - if lm: - op, N, be = lm.group(1), int(lm.group(2)), bemap[lm.group(3)] - winners.setdefault((dtype, op), {})[N] = be + cells = tp.parse_mega_sweep(text, nprob=8192) + winners = {} # (native_only, dtype, op) -> {N: backend} + for (dtype, op, N), measured in cells.items(): + for native_only in (False, True): + timings = {name: value for name, value in measured.items() + if not native_only or name not in {"nvidia", "nvidia_thread"}} + winner = tp.pick(timings, margin, {"nvidia", "nvidia_thread"}) + if winner: + be = "nvidia_block" if winner == "nvidia" else winner + winners.setdefault((native_only, dtype, op), {})[N] = be if not winners: sys.exit(f"No NPROB=8192 verdicts parsed from {sweep_path}") - def emit_op(op, dtype): - picks = winners.get((dtype, op)) + def emit_op(op, dtype, native_only): + picks = winners.get((native_only, dtype, op)) if not picks: return None ns = sorted(picks) @@ -862,14 +854,20 @@ def emit_op(op, dtype): f"// (sm {sms}, NPROB=8192 throughput regime). Do not edit by hand.", "// Included by glass-defaults.cuh inside namespace glass::defaults — no namespace wrapper.", "#define GLASS_DEFAULTS_HAVE_LOCAL", - "constexpr backend local_ideal(op o, uint32_t N, bool f64, uint32_t /*sm*/) {", + "constexpr backend local_ideal(op o, uint32_t N, bool f64, uint32_t /*sm*/,", + " bool allow_nvidia) {", ] - for dtype, guard in (("f32", "if (!f64) {"), ("f64", "if (f64) {")): - lines.append(f" {guard}") - for op in ("dot", "gemv", "gemm", "chol", "trsv", "posv"): - body = emit_op(op, dtype) - if body: - lines.append(f" if (o == op::{op}) {{ {body} }}") + for native_only, dep_guard in ((False, "if (allow_nvidia) {"), + (True, "if (!allow_nvidia) {")): + lines.append(f" {dep_guard}") + for dtype, type_guard in (("f32", "if (!f64) {"), + ("f64", "if (f64) {")): + lines.append(f" {type_guard}") + for op in tp.LADDER_OPS: + body = emit_op(op, dtype, native_only) + if body: + lines.append(f" if (o == op::{op}) {{ {body} }}") + lines.append(" }") lines.append(" }") lines += [" return backend::block;", "}", ""] out = pathlib.Path(out_path) @@ -929,7 +927,7 @@ def main(): "timed sweep always runs serially for clean measurement.") p.add_argument("--emit-defaults", metavar="SWEEP_TXT", default=None, help="Parse a bench_mega_sweep run (mega_sweep_*.txt) and emit a per-host " - "glass-defaults.cuh override header (warp/block/nvidia ladder), then exit.") + "glass-defaults.cuh override header (native and NVIDIA ladder), then exit.") args = p.parse_args() sms = detect_sm() if args.sm == "AUTO" else int(args.sm) @@ -938,7 +936,7 @@ def main(): if args.emit_defaults: out = args.out or str(TUNING_DIR / f"{hostname}_defaults.cuh") TUNING_DIR.mkdir(parents=True, exist_ok=True) - emit_defaults_table(args.emit_defaults, out, sms) + emit_defaults_table(args.emit_defaults, out, sms, args.margin) return requested_apis = [a.strip() for a in args.apis.split(",") if a.strip()] diff --git a/bench/bench_blas2.cu b/bench/bench_blas2.cu index 68dd3ce..e6220a4 100644 --- a/bench/bench_blas2.cu +++ b/bench/bench_blas2.cu @@ -2,7 +2,7 @@ // syrk C = A·Aᵀ (L3, warp:: variant exists) // syr2k C = A·Bᵀ + B·Aᵀ (L3, warp:: variant exists) // ldlt A = L·D·Lᵀ in place (L3, warp:: variant exists) -// ldltsv ldlt + ldlt_solve (L3 factor+solve, warp:: variant exists) +// ldlt_solve ldlt + solve (L3 factor+solve, warp:: variant exists) // inv Gauss-Jordan on [A|I] (L3, BLOCK-ONLY — no warp:: variant) // trmv y = tril(A)·x (L2, BLOCK-ONLY) // ger A += α·x·yᵀ (L2, BLOCK-ONLY) @@ -10,7 +10,7 @@ // Same methodology + output grammar as bench_mega_sweep.cu (ns/problem = // wall/(reps*NPROB), min of 3 trials; one problem per block / per warp; NPROB // batching) so tune.py's parser conventions carry over. TWO contenders only: -// none of these ops has a glass::nvidia:: counterpart, so there is no vendor leg +// none of these ops has a glass::nvidia::{block,thread} counterpart, so there is no vendor leg // (2-way BLOCK TB∈{32,64,128,256} vs WARP WPB∈{1..32} where warp:: exists). // // Timing-only: inputs are factored/overwritten in place across reps (no per-rep @@ -47,7 +47,7 @@ template __global__ void kb_trmv (T* A, T* x, T* y) { int p=bl template __global__ void kb_ger (T* A, T* x, T* y) { int p=blockIdx.x; glass::block::ger((T)1, x+p*N, y+p*N, A+(size_t)p*N*N); } // ─── WARP model: warp (blockIdx.x*WPB + threadIdx.y) owns its problem ───────── -// Only syrk/syr2k/ldlt/ldltsv have glass::warp:: variants (inv/trmv/ger are block-only). +// Only syrk/syr2k/ldlt/ldlt_solve have warp variants (inv/trmv/ger are block-only). template __global__ void kw_syrk (T* A, T* C, int np) { int p=blockIdx.x*blockDim.y+threadIdx.y; if(p>=np)return; glass::warp::syrk((T)1, A+(size_t)p*N*N, (T)0, C+(size_t)p*N*N); } template __global__ void kw_syr2k(T* A, T* B, T* C, int np) { int p=blockIdx.x*blockDim.y+threadIdx.y; if(p>=np)return; glass::warp::syr2k((T)1, A+(size_t)p*N*N, B+(size_t)p*N*N, (T)0, C+(size_t)p*N*N); } template __global__ void kw_ldlt (T* A, int np) { int p=blockIdx.x*blockDim.y+threadIdx.y; if(p>=np)return; glass::warp::ldlt(A+(size_t)p*N*N); } @@ -55,7 +55,7 @@ template __global__ void kw_ldltsv(T* A, T* x, int np) { int p enum Op { SYRK, SYR2K, LDLT, LDLTSV, INV, TRMV, GER, NOP }; static const char* op_name(Op o) { - const char* n[] = {"syrk","syr2k","ldlt","ldltsv","inv","trmv","ger"}; + const char* n[] = {"syrk","syr2k","ldlt","ldlt_solve","inv","trmv","ger"}; return n[o]; } static bool has_warp(Op o) { return o == SYRK || o == SYR2K || o == LDLT || o == LDLTSV; } @@ -169,7 +169,7 @@ int main(int argc, char** argv) { const char* dt = (argc > 3) ? argv[3] : "f32"; bool f64 = (strcmp(dt, "f64") == 0 || strcmp(dt, "fp64") == 0 || strcmp(dt, "double") == 0); printf("# blas2 sweep | NPROB=%d reps=%d dtype=%s | ns/problem (lower=better)\n", NPROB, reps, f64 ? "f64" : "f32"); - printf("# contenders: BLOCK(SIMT, TB swept) | WARP(WPB swept; syrk/syr2k/ldlt/ldltsv only) — no glass::nvidia:: counterparts for these ops\n"); + printf("# contenders: BLOCK(SIMT, TB swept) | WARP(WPB swept; syrk/syr2k/ldlt/ldlt_solve only) — no NVIDIA counterparts\n"); tc_warm_gpu(); // steady boost clocks before the first timed cell if (f64) run_all(reps); else run_all(reps); diff --git a/bench/bench_blockdim.cu b/bench/bench_blockdim.cu index 2ca09d2..ef63504 100644 --- a/bench/bench_blockdim.cu +++ b/bench/bench_blockdim.cu @@ -3,10 +3,10 @@ // cuBLASDx's natural block_dim choice. // // For each (M, N, K), three measurements: -// default — glass::nvidia::gemm<...> launched with cuBLASDx's +// default — glass::nvidia::block::gemm<...> launched with cuBLASDx's // natural block_dim -// pinned-128 — glass::nvidia::gemm<...,128>(...) launched <<<1, 128>>> -// pinned-352 — glass::nvidia::gemm<...,352>(...) launched <<<1, 352>>> +// pinned-128 — glass::nvidia::block::gemm<...,128>(...) launched <<<1, 128>>> +// pinned-352 — glass::nvidia::block::gemm<...,352>(...) launched <<<1, 352>>> // (matches GRiD's iiwa14 MAX_PERF_LEVEL_THREADS, the value that // deadlocked before P0-1) // diff --git a/bench/bench_gemm.cu b/bench/bench_gemm.cu index 79958e5..1d8f662 100644 --- a/bench/bench_gemm.cu +++ b/bench/bench_gemm.cu @@ -12,7 +12,7 @@ // nvcc -std=c++17 -arch=sm_XX -O3 // -I.. -I../src // -I$MATHDX_ROOT/include -I$MATHDX_ROOT/external/cutlass/include -// -DGLASS_BENCH_CUBLASDX -DSMS=XX0 +// -DGLASS_BENCH_CUBLASDX -DGLASS_TARGET_SM=XX0 // -Xptxas -O1 // bench_gemm.cu -o bench_gemm // Usage: ./bench_gemm [m [n [k [iters]]]] @@ -174,10 +174,6 @@ DEFINE_THREAD_GEMM_CT(6) // ─── cuBLASDx kernels (compile-time M/N/K) ──────────────────────────────────── #ifdef GLASS_BENCH_CUBLASDX -#ifndef SMS -#define SMS 860 -#endif - #define DEFINE_CUBLASDX_GEMM(M, N, K) \ namespace cublasdx_gemm_##M##x##N##x##K { \ using GEMM = decltype( \ @@ -271,8 +267,8 @@ DEFINE_CUBLASDX_GEMM(4, 4, 64) // ─── glass::nvidia kernels (compile-time M/N/K, alongside raw cuBLASDx) ────── // Two variants per size: -// _nv_default — uses glass::nvidia::gemm(...) (no BlockDim) -// _nv_blockdim — uses glass::nvidia::gemm(...) (BlockDim) +// _nv_default — uses glass::nvidia::block::gemm(...) +// _nv_blockdim — uses glass::nvidia::block::gemm(...) // // Both write to a volatile sink each iteration to defeat dead-store elimination. diff --git a/bench/bench_gemm_batched.cu b/bench/bench_gemm_batched.cu index be3a2d4..e04328f 100644 --- a/bench/bench_gemm_batched.cu +++ b/bench/bench_gemm_batched.cu @@ -1,8 +1,8 @@ -// bench_gemm_batched.cu — batched GEMM: glass::nvidia::gemm_batched vs. naive loop. +// bench_gemm_batched.cu — glass::nvidia::block::gemm_batched vs. naive loop. // // Demonstrates the P2-7 single-block batching speedup. For each (M, N, K, BATCH): -// naive: BATCH × glass::nvidia::gemm<...> in a single block, BlockDim -// batched: one glass::nvidia::gemm_batched<...,BATCH,TC> call, dim3(TC, BATCH) launch +// naive: BATCH × glass::nvidia::block::gemm<...> in one block +// batched: one glass::nvidia::block::gemm_batched<...,BATCH,TC> call // // Anti-optimization: per-iteration sink writes; -Xptxas -O1 (set in run_bench.py); // --expt-relaxed-constexpr. @@ -11,7 +11,7 @@ // nvcc -std=c++17 -arch=sm_XX -O3 --expt-relaxed-constexpr -Xptxas -O1 // -I.. -I../src // -I$MATHDX_ROOT/include -I$MATHDX_ROOT/external/cutlass/include -// -DGLASS_BENCH_CUBLASDX -DSMS=XX0 +// -DGLASS_BENCH_CUBLASDX -DGLASS_TARGET_SM=XX0 // bench_gemm_batched.cu -o bench_gemm_batched #include diff --git a/bench/bench_gemm_batched_1d.cu b/bench/bench_gemm_batched_1d.cu index b54e90a..920b69c 100644 --- a/bench/bench_gemm_batched_1d.cu +++ b/bench/bench_gemm_batched_1d.cu @@ -2,8 +2,8 @@ // // Three kernels per BATCH: // naive_loop_1d: BATCH × glass::gemm in a single 1D block. -// batched_1d: one glass::nvidia::gemm_batched_1d<...> call. -// strided_1d: one glass::nvidia::gemm_strided_batched_1d<...> call +// batched_1d: one glass::nvidia::block::gemm_batched_1d<...> call. +// strided_1d: one glass::nvidia::block::gemm_strided_batched_1d<...> call // (shared A; strided B/C). // // Launch geometry: <<>> (no smem needed). diff --git a/bench/bench_gemv.cu b/bench/bench_gemv.cu index 0664837..c1b326c 100644 --- a/bench/bench_gemv.cu +++ b/bench/bench_gemv.cu @@ -11,7 +11,7 @@ // nvcc -std=c++17 -arch=sm_XX -O3 // -I.. -I../src // -I$MATHDX_ROOT/include -I$MATHDX_ROOT/external/cutlass/include -// -DGLASS_BENCH_CUBLASDX -DSMS=XX0 +// -DGLASS_BENCH_CUBLASDX -DGLASS_TARGET_SM=XX0 // -Xptxas -O1 // bench_gemv.cu -o bench_gemv // Usage: ./bench_gemv [iters] @@ -160,10 +160,6 @@ DEFINE_THREAD_GEMV_CT(6) // ─── cuBLASDx kernels (compile-time M/N) ───────────────────────────────────── #ifdef GLASS_BENCH_CUBLASDX -#ifndef SMS -#define SMS 860 -#endif - #define DEFINE_CUBLASDX_GEMV(M, N) \ namespace cublasdx_gemv_##M##x##N { \ using GEMM = decltype( \ diff --git a/bench/bench_lapack.cu b/bench/bench_lapack.cu index 487d6bb..1ae1308 100644 --- a/bench/bench_lapack.cu +++ b/bench/bench_lapack.cu @@ -1,11 +1,11 @@ -// bench_lapack.cu — LAPACK timings: pure-SIMT glass vs. cuSOLVERDx-backed glass::nvidia. +// bench_lapack.cu — pure-SIMT glass vs. cuSOLVERDx-backed glass::nvidia::block. // // Variants per size N (square SPD problem with NRHS=1): // pure-SIMT potrf — glass::potrf // pure-SIMT chol+trsm — potrf then glass::trsm -// glass::nvidia potrf — cuSOLVERDx potrf via glass::nvidia::potrf -// glass::nvidia chol+trsm — potrf then glass::nvidia::trsm -// glass::nvidia posv — fused factor+solve via glass::nvidia::posv +// NVIDIA block potrf — glass::nvidia::block::potrf +// NVIDIA block potrf+trsm — then glass::nvidia::block::trsm +// NVIDIA block posv — fused glass::nvidia::block::posv // // Anti-optimization safeguards: // - Compile with -Xptxas -O1 (set in run_bench.py) @@ -17,7 +17,7 @@ // nvcc -std=c++17 -arch=sm_XX -O3 --expt-relaxed-constexpr -Xptxas -O1 // -I.. -I../src // -I$MATHDX_ROOT/include -I$MATHDX_ROOT/external/cutlass/include -// -DGLASS_BENCH_CUBLASDX -DGLASS_BENCH_CUSOLVERDX -DSMS=XX0 +// -DGLASS_BENCH_CUBLASDX -DGLASS_BENCH_CUSOLVERDX -DGLASS_TARGET_SM=XX0 // -DCUSOLVERDX_IGNORE_NVBUG_5288270_ASSERT // -lcusolverdx -lcublas -lcusolver // bench_lapack.cu -o bench_lapack @@ -180,7 +180,7 @@ __global__ void k_nv_chol(const float* A_master, float* A, volatile float* sink, uint32_t rank = threadIdx.x + threadIdx.y*blockDim.x + threadIdx.z*blockDim.x*blockDim.y; uint32_t size = blockDim.x * blockDim.y * blockDim.z; for (int rep = 0; rep < iters; rep++) { - // glass::nvidia::potrf works on a global pointer; reload from master. + // NVIDIA block potrf works on a global pointer; reload from master. if (rank < N*N) { for (uint32_t i = rank; i < N*N; i += size) A[i] = A_master[i]; } @@ -290,7 +290,7 @@ static void bench_size_ct(int iters) { k_nv_chol<<<1, THREADS, nv_chol_smem>>>(dA_master, dA, dSink, iters); cudaDeviceSynchronize(); clock_gettime(CLOCK_MONOTONIC, &t1); - printf("glass::nvidia::potrf n=%2d %.3f us/op\n", + printf("glass::nvidia::block::potrf n=%2d %.3f us/op\n", N, elapsed_us(t0, t1) / iters); // glass::nvidia chol+trsm @@ -300,7 +300,7 @@ static void bench_size_ct(int iters) { k_nv_chol_trsm<<<1, THREADS, nv_chol_trsm_smem>>>(dA_master, db_master, dA, db, dSink, iters); cudaDeviceSynchronize(); clock_gettime(CLOCK_MONOTONIC, &t1); - printf("glass::nvidia::chol+trsm n=%2d %.3f us/op\n", + printf("glass::nvidia::block::potrf+trsm n=%2d %.3f us/op\n", N, elapsed_us(t0, t1) / iters); // glass::nvidia posv (fused) @@ -309,7 +309,7 @@ static void bench_size_ct(int iters) { k_nv_posv<<<1, THREADS, nv_posv_smem>>>(dA_master, db_master, dA, db, dSink, iters); cudaDeviceSynchronize(); clock_gettime(CLOCK_MONOTONIC, &t1); - printf("glass::nvidia::posv (fused) n=%2d %.3f us/op\n", + printf("glass::nvidia::block::posv (fused) n=%2d %.3f us/op\n", N, elapsed_us(t0, t1) / iters); cudaFree(dA_master); cudaFree(db_master); diff --git a/bench/bench_mega_sweep.cu b/bench/bench_mega_sweep.cu index 074c38d..f5749e5 100644 --- a/bench/bench_mega_sweep.cu +++ b/bench/bench_mega_sweep.cu @@ -1,9 +1,10 @@ // bench_mega_sweep.cu — ladder scaling sweep: // WARP — one warp per problem, <<>>, WPB ∈ {1..32} // BLOCK — one block per problem, <<>>, TB ∈ {32,64,128,256} (pure-SIMT glass::block::) -// NVIDIA — cuBLASDx/cuSOLVERDx, <<>>, descriptor-fixed (f32 to N128; f64 to N64) +// NVIDIA BLOCK — cuBLASDx/cuSOLVERDx, <<>>, descriptor-fixed +// NVIDIA THREAD — cuSOLVERDx 0.4+, one problem/thread, TPB swept (LAPACK ops) // AUTO — bare glass::op at the BLOCK launch shapes: the shipped measured-default -// face (constexpr device-level body dispatch via -DSMS). AUDIT-ONLY — +// face (constexpr device-level body dispatch via GLASS_TARGET_SM). AUDIT-ONLY — // the AUTO segment/token is ignored by tune.py's table parsers and never // feeds a verdict or a plotted figure line (a line invites misreading vs // the warp/thread launch-packing tiers — 08-16 ruling). It validates that @@ -12,26 +13,28 @@ // identical-code AUTO-vs-BLOCK deltas exposed the 2026-08-15 in-place // input-drift bias that the per-trial reset hook now prevents. // -// Answers "where do the breakevens fall on the warp → SIMT-block → MathDx ladder?" across +// Answers "where do the breakevens fall on the thread → warp → block and +// dependency-backed NVIDIA block/thread ladder?" across // problem size N and batch count NPROB (single-problem latency → GPU-saturating throughput). // -// Ops (each has glass::, glass::warp::, and a glass::nvidia:: form): +// Ops each have native scope forms and, where supported, explicit NVIDIA scope forms: // dot (L1) gemv (L2) gemm (L3) chol (L3) trsv (L3, nvidia=trsm) posv (L3) // -// dtype: f32 (3-way, nvidia to N128) or f64 (3-way, nvidia to N64 — f64 vendor descriptors fit a lower smem cap). +// dtype: f32 or f64. Native thread/warp/block and NVIDIA block are measured +// across their supported domains; NVIDIA thread is instantiated through N=32. // The nvidia leg is FORCED at every N: a DEFINE_NVIDIA_* macro is in scope for each N, so -// glass::nvidia:: resolves to the cuBLASDx/cuSOLVERDx specialization +// glass::nvidia::block:: resolves to a MathDx specialization // unconditionally (bypassing the shipped size-heuristic auto-dispatch) — we want the full // vendor curve so the crossover with block/warp is visible, not just the heuristic's verdict. // -// Metric: ns per problem (wall / (reps*NPROB)), min of 3 trials. Lower = better. Timing-only: -// inputs are factored/overwritten in place across reps (no per-rep reload) — uniform across -// all contenders, so the comparison is apples-to-apples. +// Metric: ns per problem (wall / (reps*NPROB)), min of 3 trials. Lower = better. +// Each trial starts from an untimed pristine-input reset. Inputs may still be +// overwritten across repetitions within that trial, uniformly for every contender. // -// Compile (3-way, needs MathDx — set MATHDX_ROOT): +// Compile (full ladder, needs MathDx — set MATHDX_ROOT): // nvcc -std=c++17 -arch=sm_120 -O3 --expt-relaxed-constexpr -Xptxas -O1 -I.. -I../src // -I$MATHDX_ROOT/include -I$MATHDX_ROOT/external/cutlass/include -// -DGLASS_BENCH_CUBLASDX -DGLASS_BENCH_CUSOLVERDX -DSMS=1200 +// -DGLASS_BENCH_CUBLASDX -DGLASS_BENCH_CUSOLVERDX -DGLASS_TARGET_SM=1200 // -DCUSOLVERDX_IGNORE_NVBUG_5288270_ASSERT -dlto // -lcusolverdx -lcublas -lcusolver -lcudart bench_mega_sweep.cu -o bench_mega_sweep // (omit the MathDx -I / -D / -l flags → compiles 2-way warp/block only, both dtypes.) @@ -59,11 +62,17 @@ #endif #if defined(GLASS_BENCH_CUSOLVERDX) -#define MEGA_NV_LAPACK 1 // chol, trsm, posv (cuSOLVERDx) +#define MEGA_NV_LAPACK 1 // chol, trsm, posv (cuSOLVERDx block/thread) #else #define MEGA_NV_LAPACK 0 #endif +#if defined(GLASS_HAVE_CUSOLVERDX_THREAD) && GLASS_HAVE_CUSOLVERDX_THREAD +#define MEGA_NV_THREAD 1 +#else +#define MEGA_NV_THREAD 0 +#endif + static int NPROB = 8192; @@ -95,7 +104,7 @@ template __global__ void ka_posv(T* A, T* b) { int p=blockIdx. enum Op { DOT, GEMV, GEMM, CHOL, TRSV, POSV, NOP }; static const char* op_name(Op o) { - const char* n[] = {"dot","gemv","gemm","chol","trsv","posv"}; + const char* n[] = {"dot","gemv","gemm","potrf","trsv","posv"}; return n[o]; } @@ -156,13 +165,14 @@ static void launch_warp(Op op, int WPB, T* A, T* B, T* C, T* x, T* y) { // pyroffi IK case (A = JᵀJ built on-chip); no memory traffic to attribute, // so it trivially wins and would be a meaningless table entry. // -// Swept over the FULL size domain so every contender shares the same points and -// the figures show the spill catastrophe explicitly instead of a truncated line -// (a per-thread T[N*N] is local-memory-resident far past the N<=7 register -// ceiling — N=128/f64 is a 128KB-per-thread array; the numbers document how bad, -// they never win). tune_pick's parser still treats the column as optional so -// pre-2026-07 captures (no thread column) keep parsing. -template static constexpr bool thread_ok() { return true; } +// Instantiated through N=64. That includes every measured winning native-thread +// cell on sm_120/sm_87 and one losing boundary point, while avoiding the N=96/128 +// template/local-array explosion in this monolithic TU. If a future capture +// makes N>64 scientifically important, extend with a split executable rather +// than increasing the roughly 12GB peak of this already-heavy build. tune_pick +// treats the column as optional so +// older and deliberately out-of-domain rows remain replay-compatible. +template static constexpr bool thread_ok() { return N <= 64; } template __global__ void kt_dot (T* x, T* y, int np) { int p=blockIdx.x*blockDim.x+threadIdx.x; if(p>=np)return; T r=glass::thread::dot(x+(size_t)p*N, y+(size_t)p*N); y[(size_t)p*N]=r; } template __global__ void kt_gemv(T* A, T* x, T* y, int np) { @@ -222,7 +232,7 @@ static void launch_thread(Op op, int TPB, T* A, T* B, T* C, T* x, T* y) { } // ─── NVIDIA model: cuBLASDx / cuSOLVERDx, one block per problem ────────────── -// DEFINE_NVIDIA_* emit explicit specializations so the glass::nvidia:: call +// DEFINE_NVIDIA_* emit specializations for the glass::nvidia::block:: call // resolves to the vendor path unconditionally (forced, no size-heuristic dispatch). // FLOAT: gemm 16/24/32/64 + gemv 4..64 are already cuBLASDx-specialized by // glass-nvidia.cuh/tuning_table.cuh (those shipped specializations ARE the forced @@ -230,7 +240,7 @@ static void launch_thread(Op op, int TPB, T* A, T* B, T* C, T* x, T* y) { // defined via the *_PREC(..., double) macros. Double caps at N<=64 (smem: a 99KB // opt-in limit fits f64 gemm only to 64, f64 chol/posv to ~96; we define <=64). #if MEGA_NV_BLAS -static const int NV_DOT_TB = 256; // CUB BlockReduce thread count for nvidia::dot +static const int NV_DOT_TB = 256; // CUB BlockReduce thread count for nvidia::block::dot namespace glass { namespace nvidia { namespace block { // float gaps (shipped: gemm 16/24/32/64, gemv 4..64) DEFINE_NVIDIA_GEMM(4, 4, 4) DEFINE_NVIDIA_GEMM(6, 6, 6) @@ -300,12 +310,34 @@ template __global__ void kn_posv(T* A, T* b) { } #endif +// ─── NVIDIA THREAD model: cuSOLVERDx 0.4+, one problem per CUDA thread ────── +// Unlike the native glass::thread contender, cuSOLVERDx accepts the packed +// global-memory operands directly. The same per-problem-contiguous layout and +// all global traffic remain inside the timed region; there is no hidden layout +// transform or shared-memory allocation. +#if MEGA_NV_THREAD +template __global__ void knt_chol(T* A, int np) { + int p=blockIdx.x*blockDim.x+threadIdx.x; if(p>=np)return; + glass::nvidia::thread::potrf(A+(size_t)p*N*N); +} +template __global__ void knt_trsv(T* A, T* x, int np) { + int p=blockIdx.x*blockDim.x+threadIdx.x; if(p>=np)return; + glass::nvidia::thread::trsm((T)1, A+(size_t)p*N*N, x+(size_t)p*N); +} +template __global__ void knt_posv(T* A, T* b, int np) { + int p=blockIdx.x*blockDim.x+threadIdx.x; if(p>=np)return; + glass::nvidia::thread::posv(A+(size_t)p*N*N, b+(size_t)p*N); +} +#endif + // True at compile time iff op@N has a forced nvidia variant defined above. // Double is defined only up to 64 (f64 descriptors/smem cap lower than float). template static constexpr bool nv_blas_ok() { return MEGA_NV_BLAS && (std::is_same_v ? N <= 128 : N <= 64); } template static constexpr bool nv_lapack_ok() { return MEGA_NV_LAPACK && (std::is_same_v ? N <= 128 : N <= 64); } +template static constexpr bool nvt_lapack_ok() +{ return MEGA_NV_THREAD && N <= 32; } // Measurement core lives in timing_common.cuh (min-of-3 + FAIL probe + trial // spread + the mutation invariant). g_row_spread accumulates the worst trial @@ -406,6 +438,28 @@ static double nv_dispatch(Op op, T* A, T* B, T* C, T* x, T* y, int reps) { return nv_op_time(op, A, B, C, x, y, reps); } +// One cuSOLVERDx-thread launch shape. The caller sweeps TPB and retains every +// FAIL explicitly, just like the native THREAD tier. +template +static double nvt_dispatch(Op op, int TPB, T* A, T* x, int reps) { + (void)op; (void)TPB; (void)A; (void)x; (void)reps; +#if MEGA_NV_THREAD + if constexpr (nvt_lapack_ok()) { + dim3 grid((NPROB + TPB - 1) / TPB), blk(TPB); + if (op == CHOL) + return nv_timed(knt_chol, 0, + [&]{ knt_chol<<>>(A, NPROB); }, reps); + if (op == TRSV) + return nv_timed(knt_trsv, 0, + [&]{ knt_trsv<<>>(A, x, NPROB); }, reps); + if (op == POSV) + return nv_timed(knt_posv, 0, + [&]{ knt_posv<<>>(A, x, NPROB); }, reps); + } +#endif + return -1.0; +} + template static void bench_size(Op op, int reps) { T *A, *B, *C, *x, *y; @@ -441,8 +495,9 @@ static void bench_size(Op op, int reps) { // results, so output is byte-identical either way. constexpr int TBS[4] = {32, 64, 128, 256}; constexpr int WPBS[6] = {1, 2, 4, 8, 16, 32}; - double r_block[4], r_warp[6], r_thread[4], r_auto[4], r_nv = -1.0; + double r_block[4], r_warp[6], r_thread[4], r_auto[4], r_nvt[4], r_nv = -1.0; for (double* a : {r_block, r_auto, r_thread}) for (int i=0;i<4;i++) a[i] = 1e30; + for (int i=0;i<4;i++) r_nvt[i] = -1.0; for (int i=0;i<6;i++) r_warp[i] = 1e30; std::vector> items; for (int i=0;i<4;i++) items.push_back([&,i]{ @@ -465,6 +520,12 @@ static void bench_size(Op op, int reps) { for (int i=0;i<4;i++) items.push_back([&,i]{ int TB = TBS[i]; r_auto[i] = time_ns_per_prob([&]{ launch_auto(op, TB, A, B, C, x, y); }, reps); }); + if constexpr (nvt_lapack_ok()) { + if (op == CHOL || op == TRSV || op == POSV) { + for (int i=0;i<4;i++) items.push_back([&,i]{ + r_nvt[i] = nvt_dispatch(op, TBS[i], A, x, reps); }); + } + } items.push_back([&]{ r_nv = nv_dispatch(op, A, B, C, x, y, reps); }); if (g_shuffle_seed) std::shuffle(items.begin(), items.end(), g_shuffle_rng); for (auto& it : items) it(); @@ -501,11 +562,21 @@ static void bench_size(Op op, int reps) { if (ns < best_auto) { best_auto = ns; best_atb = TBS[i]; } } double nv = r_nv; + double best_nvt = 1e30; int best_nvt_tpb = 0; + const bool has_nvt = nvt_lapack_ok() && + (op == CHOL || op == TRSV || op == POSV); + if (has_nvt) { + printf(" | NVIDIA_THREAD"); + for (int i=0;i<4;i++) { + double ns = r_nvt[i]; + if (ns > 0) printf(" nvt%d=%.4f", TBS[i], ns); else printf(" nvt%d=FAIL", TBS[i]); + if (ns > 0 && ns < best_nvt) { best_nvt = ns; best_nvt_tpb = TBS[i]; } + } + } - // 4-way winner. thread/warp/block are all dependency-free pure SIMT, so they - // compete on raw time; only nvidia (MathDx) must clear tune_pick's margin — - // hence `base` is the best of the three SIMT tiers, as before, now including - // thread (full domain). + // thread/warp/block are dependency-free pure SIMT. NVIDIA block and NVIDIA + // thread both carry MathDx and are raw-timed here; tune_pick applies the + // shared dependency margin when generating tables. const bool has_thread = (best_thread < 1e29); double base = best_block; const char* base_winner = "BLOCK"; if (best_warp < base) { base = best_warp; base_winner = "WARP"; } @@ -516,13 +587,18 @@ static void bench_size(Op op, int reps) { if (best_warp > base && best_warp < simt_second) simt_second = best_warp; if (has_thread && best_thread > base && best_thread < simt_second) simt_second = best_thread; - const char* winner; double margin; - if (nv > 0 && nv < base) { winner = "NVIDIA"; margin = base / nv; } - else if (nv > 0) { winner = base_winner; margin = nv / base; } // margin = how much NV trails - else { winner = base_winner; margin = (simt_second < 1e29) ? simt_second / base : 1.0; } + const char* winner = base_winner; double winning_time = base; + if (nv > 0 && nv < winning_time) { winner = "NVIDIA"; winning_time = nv; } + if (best_nvt < winning_time) { winner = "NVIDIA_THREAD"; winning_time = best_nvt; } + double runner_up = 1e30; + for (double v : {base, nv, best_nvt}) + if (v > winning_time && v < runner_up) runner_up = v; + if (runner_up == 1e30) runner_up = simt_second; + double margin = runner_up < 1e29 ? runner_up / winning_time : 1.0; printf(" || block tb%d=%.4f warp w%d=%.4f", best_tb, best_block, best_wpb, best_warp); if (has_thread) printf(" thread t%d=%.4f", best_tpb, best_thread); if (nv > 0) printf(" nv=%.4f", nv); + if (best_nvt < 1e29) printf(" nvt t%d=%.4f", best_nvt_tpb, best_nvt); // auto token LAST among times: _ROW_RE captures block/warp[/thread][/nv] // left-to-right, so a trailing token cannot perturb table regeneration. if (best_auto < 1e29) printf(" auto a%d=%.4f", best_atb, best_auto); @@ -549,8 +625,9 @@ int main(int argc, char** argv) { bool f64 = (strcmp(dt, "f64") == 0 || strcmp(dt, "fp64") == 0 || strcmp(dt, "double") == 0); { int v = 48*1024; cudaDeviceGetAttribute(&v, cudaDevAttrMaxSharedMemoryPerBlockOptin, 0); g_optin_smem = (size_t)v; } printf("# mega sweep | NPROB=%d reps=%d dtype=%s | ns/problem (lower=better) | optin_smem=%zuKB\n", NPROB, reps, f64 ? "f64" : "f32", g_optin_smem/1024); - printf("# contenders: BLOCK(SIMT, TB swept) | WARP(WPB swept) | THREAD(SIMT, TPB swept) | AUTO(bare glass::, shipped dispatch, TB swept; figure-only) | NV(cuBLASDx/cuSOLVERDx, forced; f32<=128, f64<=64)\n"); - printf("# THREAD stages operands global->registers->global in the per-problem-contiguous layout (uncoalesced; the layout tax is IN the timing).\n"); + printf("# contenders: BLOCK(SIMT, TB swept) | WARP(WPB swept) | THREAD(SIMT, TPB swept) | AUTO(bare glass::, shipped dispatch, TB swept; figure-only) | NV_BLOCK(cuBLASDx/cuSOLVERDx, forced; f32<=128, f64<=64) | NV_THREAD(cuSOLVERDx 0.4+, TPB swept; LAPACK N<=32)\n"); + printf("# NV_THREAD N>32 is intentionally not instantiated to avoid further growth in this already memory-heavy monolithic TU; extend with a split executable only if a winner reaches N=32.\n"); + printf("# THREAD stages operands global->registers->global in the per-problem-contiguous layout (uncoalesced; the layout tax is IN the timing; instantiated N<=64).\n"); if (const char* s = getenv("GLASS_SHUFFLE_ORDER"); s && strtoull(s, nullptr, 10) != 0) { g_shuffle_seed = strtoull(s, nullptr, 10); g_shuffle_rng.seed(g_shuffle_seed); diff --git a/bench/bench_nvt_valid.cu b/bench/bench_nvt_valid.cu new file mode 100644 index 0000000..be15ee2 --- /dev/null +++ b/bench/bench_nvt_valid.cu @@ -0,0 +1,248 @@ +// bench_nvt_valid.cu — valid-input confirmation for NVIDIA-thread defaults. +// +// The main ladder intentionally measures many back-to-back launches between +// restores. That is a useful steady-throughput workload, but in-place solvers +// see their own output after the first launch. This companion benchmark gives +// every timed launch a distinct, valid input batch. It is a veto gate only: +// tune.py may retain an NVIDIA-thread ladder winner when it also clears the +// native thread/warp/block winner here, but this leg never promotes a vendor +// backend that did not win the main ladder. +// +// Usage: ./bench_nvt_valid [nprob=8192] [requested_slots=64] [dtype=f32|f64] + +#include +#include +#include +#include +#include +#include + +#include "timing_common.cuh" +#include "../glass-nvidia.cuh" + +#define CUDA_OK(call) do { \ + cudaError_t glass_cuda_error_ = (call); \ + if (glass_cuda_error_ != cudaSuccess) { \ + std::fprintf(stderr, "CUDA error %s at %s:%d\n", \ + cudaGetErrorString(glass_cuda_error_), __FILE__, __LINE__); \ + std::exit(2); \ + } \ +} while (0) + +enum class Op { potrf, trsv, posv }; + +static int g_nprob = 8192; + +template +__global__ void init_valid(T* A, T* b, int problems) { + const size_t matrices = static_cast(problems) * N * N; + for (size_t q = static_cast(blockIdx.x) * blockDim.x + threadIdx.x; + q < matrices; q += static_cast(gridDim.x) * blockDim.x) { + const int e = static_cast(q % (N * N)); + const int i = e % N, j = e / N; + if (i == j) { + A[q] = static_cast(N + 2); + } else { + const int lo = i < j ? i : j, hi = i < j ? j : i; + A[q] = static_cast(0.02 * (1 + ((3 * lo + 5 * hi) % 7))); + } + } + const size_t vectors = static_cast(problems) * N; + for (size_t q = static_cast(blockIdx.x) * blockDim.x + threadIdx.x; + q < vectors; q += static_cast(gridDim.x) * blockDim.x) { + b[q] = static_cast(1 + (q % N) * 0.03125); + } +} + +template +__global__ void block_kernel(Op op, T* A, T* b) { + const int p = blockIdx.x; + T* Ap = A + static_cast(p) * N * N; + T* bp = b + static_cast(p) * N; + if (op == Op::potrf) glass::block::potrf(Ap); + if (op == Op::trsv) glass::block::trsv(Ap, bp); + if (op == Op::posv) glass::block::posv(Ap, bp); +} + +template +__global__ void warp_kernel(Op op, T* A, T* b, int problems) { + const int p = blockIdx.x * blockDim.y + threadIdx.y; + if (p >= problems) return; + T* Ap = A + static_cast(p) * N * N; + T* bp = b + static_cast(p) * N; + if (op == Op::potrf) glass::warp::potrf(Ap); + if (op == Op::trsv) glass::warp::trsv(Ap, bp); + if (op == Op::posv) glass::warp::posv(Ap, bp); +} + +template +__global__ void thread_kernel(Op op, T* A, T* b, int problems) { + const int p = blockIdx.x * blockDim.x + threadIdx.x; + if (p >= problems) return; + T a[N * N], bv[N]; + T* Ap = A + static_cast(p) * N * N; + T* bp = b + static_cast(p) * N; + for (int i = 0; i < N * N; ++i) a[i] = Ap[i]; + if (op != Op::potrf) + for (int i = 0; i < N; ++i) bv[i] = bp[i]; + if (op == Op::potrf) glass::thread::potrf(a); + if (op == Op::trsv) glass::thread::trsv(a, bv); + if (op == Op::posv) glass::thread::posv(a, bv); + if (op == Op::potrf) + for (int i = 0; i < N * N; ++i) Ap[i] = a[i]; + else + for (int i = 0; i < N; ++i) bp[i] = bv[i]; +} + +template +__global__ void nvt_kernel(Op op, T* A, T* b, int problems) { + const int p = blockIdx.x * blockDim.x + threadIdx.x; + if (p >= problems) return; + T* Ap = A + static_cast(p) * N * N; + T* bp = b + static_cast(p) * N; + if (op == Op::potrf) glass::nvidia::thread::potrf(Ap); + if (op == Op::trsv) glass::nvidia::thread::trsm(T(1), Ap, bp); + if (op == Op::posv) glass::nvidia::thread::posv(Ap, bp); +} + +struct Timing { + double ns = 1e30; + double spread = 0.0; + int shape = 0; +}; + +template +static Timing time_slots(Prepare prepare, LaunchSlot launch, int slots) { + cudaGetLastError(); + prepare(); + launch(0); + if (cudaDeviceSynchronize() != cudaSuccess || + cudaGetLastError() != cudaSuccess) return {}; + + double best = 1e30, worst = 0.0; + for (int trial = 0; trial < 3; ++trial) { + prepare(); + CUDA_OK(cudaDeviceSynchronize()); + timespec t0{}, t1{}; + clock_gettime(CLOCK_MONOTONIC, &t0); + for (int slot = 0; slot < slots; ++slot) launch(slot); + CUDA_OK(cudaDeviceSynchronize()); + clock_gettime(CLOCK_MONOTONIC, &t1); + const double ns = tc_elapsed_ms(t0, t1) * 1e6 / + (static_cast(slots) * g_nprob); + best = std::min(best, ns); + worst = std::max(worst, ns); + } + return {best, (worst / best - 1.0) * 100.0, 0}; +} + +static void retain(Timing& best, Timing candidate, int shape) { + if (candidate.ns < best.ns) { + best = candidate; + best.shape = shape; + } +} + +template +static void run_case(Op op, int requested_slots) { + const size_t bytes_per_slot = static_cast(g_nprob) * + (N * N + N) * sizeof(T); + size_t free_bytes = 0, total_bytes = 0; + CUDA_OK(cudaMemGetInfo(&free_bytes, &total_bytes)); + const size_t budget = std::min(size_t(1) << 30, free_bytes / 3); + const int slots = std::max(1, std::min(requested_slots, + static_cast(budget / bytes_per_slot))); + const size_t problems = static_cast(g_nprob) * slots; + T *A = nullptr, *b = nullptr; + CUDA_OK(cudaMalloc(&A, problems * N * N * sizeof(T))); + CUDA_OK(cudaMalloc(&b, problems * N * sizeof(T))); + + auto prepare = [&] { + const size_t elements = problems * N * N; + const int blocks = std::min(4096, (elements + 255) / 256); + init_valid<<>>(A, b, static_cast(problems)); + }; + auto slot_A = [&](int slot) { + return A + static_cast(slot) * g_nprob * N * N; + }; + auto slot_b = [&](int slot) { + return b + static_cast(slot) * g_nprob * N; + }; + + constexpr int TBS[] = {32, 64, 128, 256}; + constexpr int WPBS[] = {1, 2, 4, 8, 16, 32}; + Timing block, warp, thread, nvt; + for (int tb : TBS) { + retain(block, time_slots(prepare, [&](int s) { + block_kernel<<>>(op, slot_A(s), slot_b(s)); + }, slots), tb); + retain(thread, time_slots(prepare, [&](int s) { + const int grid = (g_nprob + tb - 1) / tb; + thread_kernel<<>>(op, slot_A(s), slot_b(s), g_nprob); + }, slots), tb); + retain(nvt, time_slots(prepare, [&](int s) { + const int grid = (g_nprob + tb - 1) / tb; + nvt_kernel<<>>(op, slot_A(s), slot_b(s), g_nprob); + }, slots), tb); + } + for (int wpb : WPBS) { + retain(warp, time_slots(prepare, [&](int s) { + const int grid = (g_nprob + wpb - 1) / wpb; + warp_kernel<<>>( + op, slot_A(s), slot_b(s), g_nprob); + }, slots), wpb); + } + + const char* opname = op == Op::potrf ? "potrf" : + op == Op::trsv ? "trsv" : "posv"; + std::printf("NVT_VALID op=%s N=%d dtype=%s nprob=%d slots=%d " + "block=%.4f block_shape=%d block_spread=%.2f " + "warp=%.4f warp_shape=%d warp_spread=%.2f " + "thread=%.4f thread_shape=%d thread_spread=%.2f " + "nvidia_thread=%.4f nvt_shape=%d nvt_spread=%.2f\n", + opname, N, std::is_same_v ? "f32" : "f64", + g_nprob, slots, + block.ns, block.shape, block.spread, + warp.ns, warp.shape, warp.spread, + thread.ns, thread.shape, thread.spread, + nvt.ns, nvt.shape, nvt.spread); + CUDA_OK(cudaFree(A)); + CUDA_OK(cudaFree(b)); +} + +template +static void run_size(int requested_slots) { + run_case(Op::potrf, requested_slots); + run_case(Op::trsv, requested_slots); + run_case(Op::posv, requested_slots); +} + +template +static void run_type(int requested_slots) { + run_size(requested_slots); + run_size(requested_slots); + run_size(requested_slots); + run_size(requested_slots); + run_size(requested_slots); + run_size(requested_slots); + run_size(requested_slots); +} + +int main(int argc, char** argv) { + g_nprob = argc > 1 ? std::atoi(argv[1]) : 8192; + const int slots = argc > 2 ? std::atoi(argv[2]) : 64; + const char* dtype = argc > 3 ? argv[3] : "f32"; + if (g_nprob <= 0 || slots <= 0) { + std::fprintf(stderr, "nprob and requested_slots must be positive\n"); + return 2; + } + std::printf("# nvidia-thread valid-input confirmation | NPROB=%d " + "requested_slots=%d dtype=%s | ns/problem, min of 3\n", + g_nprob, slots, dtype); + std::printf("# each timed launch consumes one independent valid batch; " + "initialization is outside the timed region; memory cap=1GiB\n"); + tc_warm_gpu(); + if (std::strcmp(dtype, "f64") == 0) run_type(slots); + else run_type(slots); + return 0; +} diff --git a/bench/bench_reduce.cu b/bench/bench_reduce.cu index 157b0ba..1980995 100644 --- a/bench/bench_reduce.cu +++ b/bench/bench_reduce.cu @@ -8,12 +8,12 @@ #include #include #include "../glass.cuh" -#include "../glass-nvidia.cuh" // pulls in glass::nvidia::reduce/dot/nrm2 (CUB-backed) +#include "../glass-nvidia.cuh" // glass::nvidia::block CUB reductions static const int THREADS = 256; // ─── glass::nvidia kernels (CUB-backed via glass-nvidia.cuh) ───────────────── -// One variant: glass::nvidia::reduce. Writes a per-iter sink +// One variant: glass::nvidia::block::reduce. Writes a per-iter sink // to defeat dead-store elimination. template __global__ void k_nv_reduce(float* x, volatile float* sink, int iters) { @@ -312,19 +312,19 @@ int main(int argc, char** argv) { k_nv_reduce<<<1, THREADS, nv_smem_total>>>(dx, dSink, iters); \ cudaDeviceSynchronize(); \ clock_gettime(CLOCK_MONOTONIC, &t1); \ - printf("glass::nvidia::reduce n=%3d %.3f us/op\n", \ + printf("glass::nvidia::block::reduce n=%3d %.3f us/op\n", \ N, elapsed_us(t0, t1) / iters); \ clock_gettime(CLOCK_MONOTONIC, &t0); \ k_nv_dot<<<1, THREADS, nv_smem>>>(dx, dy, dSink, iters); \ cudaDeviceSynchronize(); \ clock_gettime(CLOCK_MONOTONIC, &t1); \ - printf("glass::nvidia::dot n=%3d %.3f us/op\n", \ + printf("glass::nvidia::block::dot n=%3d %.3f us/op\n", \ N, elapsed_us(t0, t1) / iters); \ clock_gettime(CLOCK_MONOTONIC, &t0); \ k_nv_nrm2<<<1, THREADS, nv_smem>>>(dx, dSink, iters); \ cudaDeviceSynchronize(); \ clock_gettime(CLOCK_MONOTONIC, &t1); \ - printf("glass::nvidia::nrm2 n=%3d %.3f us/op\n", \ + printf("glass::nvidia::block::nrm2 n=%3d %.3f us/op\n", \ N, elapsed_us(t0, t1) / iters); \ } MAYBE_NV_REDUCE_CT(4) diff --git a/bench/bench_reduced.cu b/bench/bench_reduced.cu index 049e454..fa2badd 100644 --- a/bench/bench_reduced.cu +++ b/bench/bench_reduced.cu @@ -8,7 +8,7 @@ // Emits one parseable row per (dtype,M,N,K,blockDim): // REDUCED dtype M N K blockDim n_out serial_us reduced_us ratio spreads // where ratio = serial_us / reduced_us (>1 ⇒ reduced wins). Used to seed -// glass::suggested_use_reduced<>() and the contraction_parallel concepts page. +// the conservative standard policy and the contraction_parallel concepts page. // // Build: nvcc -std=c++17 -arch=sm_XX -O3 -I.. -I../src bench_reduced.cu -o bench_reduced // Usage: ./bench_reduced [iters] [f32|f64|both] diff --git a/bench/explore_sweep.ipynb b/bench/explore_sweep.ipynb index 5363765..deba382 100644 --- a/bench/explore_sweep.ipynb +++ b/bench/explore_sweep.ipynb @@ -10,7 +10,7 @@ "Loads a `bench_mega_sweep` run (`bench/mega_sweep_*.txt`) and visualizes the\n", "**warp vs block(SIMT) vs nvidia(MathDx)** ladder per op, plus the data-driven\n", "backend winner per (op, N). This is the measurement behind `glass-defaults.cuh`'s\n", - "`suggested_backend<>()` — regenerate a per-host table with\n", + "`recommend<>()` — regenerate a per-host execution-plan table with\n", "`python bench/autotune.py --emit-defaults `.\n", "\n", "Run from the `bench/` directory. Needs numpy + matplotlib." @@ -93,7 +93,7 @@ "id": "14b7226b", "metadata": {}, "source": [ - "## Winner per (op, N) — what `suggested_backend` reflects" + "## Winner per (op, N) — what `recommend` reflects" ] }, { diff --git a/bench/export_sweep_figures.py b/bench/export_sweep_figures.py index a98b952..bc05f7c 100644 --- a/bench/export_sweep_figures.py +++ b/bench/export_sweep_figures.py @@ -1,8 +1,8 @@ #!/usr/bin/env python3 -"""Render the thread/warp/block/nvidia sweep ladder into static docs assets. +"""Render the native/NVIDIA execution-scope sweep into static docs assets. Reads a ``bench/mega_sweep_*.txt`` run (the same data behind -``glass-defaults.cuh``'s ``suggested_backend<>()``) and writes, into +``glass-defaults.cuh``'s ``recommend<>()``) and writes, into ``docs/source/_static/``: * ``mega_sweep_ladder_
_n.png`` — one figure per (dtype, NPROB regime) @@ -33,12 +33,15 @@ matplotlib.use("Agg") # headless: no display needed import matplotlib.pyplot as plt -OPS = ["dot", "gemv", "gemm", "chol", "trsv", "posv"] +import tune_pick as tp + +OPS = ["dot", "gemv", "gemm", "potrf", "trsv", "posv"] _HDR = re.compile(r"NPROB=(\d+).*dtype=(f32|f64)") _ROW = re.compile( - r"^(dot|gemv|gemm|chol|trsv|posv)\s+N=(\d+).*\|\|\s*" + r"^(dot|gemv|gemm|chol|potrf|trsv|posv)\s+N=(\d+).*\|\|\s*" r"block\s+tb\d+=([\d.]+)\s+warp\s+w\d+=([\d.]+)" r"(?:\s+thread\s+t\d+=([\d.]+))?(?:\s+nv=([\d.]+))?" + r"(?:\s+nvt\s+t\d+=([\d.]+))?" ) @@ -64,11 +67,14 @@ def parse(text, regimes=REGIMES): m = _ROW.match(line.strip()) if m: op, N = m.group(1), int(m.group(2)) + op = "potrf" if op == "chol" else op d = {"block": float(m.group(3)), "warp": float(m.group(4))} if m.group(5): d["thread"] = float(m.group(5)) if m.group(6): d["nvidia"] = float(m.group(6)) + if m.group(7): + d["nvidia_thread"] = float(m.group(7)) data[(nprob, dt, op, N)] = d return data @@ -92,7 +98,8 @@ def plot_ladder(data, nprob, dt, out_path): drew = False for ax, op in zip(axes, OPS): for key, c in [("warp", "tab:green"), ("block", "tab:blue"), - ("thread", "tab:orange"), ("nvidia", "tab:red")]: + ("thread", "tab:orange"), ("nvidia", "tab:red"), + ("nvidia_thread", "tab:purple")]: xs, ys = _series(data, nprob, dt, op, key) if xs: ax.plot(xs, ys, "o-", color=c, label=key, ms=4) @@ -104,10 +111,10 @@ def plot_ladder(data, nprob, dt, out_path): ax.grid(alpha=0.3) ax.legend(fontsize=8) fig.text(0.5, 0.005, - "thread curves end where the per-thread local-memory footprint makes the launch infeasible " - "(FAIL cells in the capture) — not unmeasured; nvidia f64 caps at N=64 (smem).", + "FAIL cells are explicit launch failures, not omitted measurements; " + "NVIDIA block f64 caps at N=64 (shared-memory limit).", ha="center", fontsize=7, style="italic") - fig.suptitle(f"{dt} thread/warp/block/nvidia ladder — NPROB={nprob} " + fig.suptitle(f"{dt} native/NVIDIA execution-scope ladder — NPROB={nprob} " f"({'throughput' if nprob >= 8192 else 'low-batch' if nprob <= 64 else 'mid-batch'})", fontsize=11) fig.tight_layout() @@ -124,12 +131,13 @@ def winners_text(data): if not Ns: continue lines.append(f"NPROB={nprob} {dt} winner by op x N:") - lines.append("op " + "".join(f"{N:>7}" for N in Ns)) + lines.append("op " + "".join(f"{N:>14}" for N in Ns)) for op in OPS: cells = [] for N in Ns: d = data.get((nprob, dt, op, N)) - cells.append(f"{min(d, key=d.get):>7}" if d else f"{'-':>7}") + winner = tp.pick(d, 0.05, {"nvidia", "nvidia_thread"}) if d else None + cells.append(f"{winner:>14}" if winner else f"{'-':>14}") lines.append(f"{op:6} " + "".join(cells)) lines.append("") return "\n".join(lines).rstrip() + "\n" diff --git a/bench/run_bench.py b/bench/run_bench.py index 8ee1063..bd60baa 100644 --- a/bench/run_bench.py +++ b/bench/run_bench.py @@ -152,7 +152,7 @@ def compile_binary(name: str, arch: str, sms: int, mathdx_root, f"-I{mathdx_root / 'include'}", f"-I{mathdx_root / 'external' / 'cutlass' / 'include'}", "-DGLASS_BENCH_CUBLASDX", - f"-DSMS={sms}", + f"-DGLASS_TARGET_SM={sms}", "--expt-relaxed-constexpr", # silence cuBLASDx constexpr/host/device warnings "-Xptxas", "-O1", # workaround for CUDA 12.9 bug + anti-DSE for benches ] diff --git a/bench/run_jetson.sh b/bench/run_jetson.sh index 4233e5c..fe6cbff 100755 --- a/bench/run_jetson.sh +++ b/bench/run_jetson.sh @@ -124,12 +124,12 @@ python3 tune.py --sm "$SMS" --allow-no-mathdx --legs ladder --prebuild || exit 1 python3 paper_sweeps.py --arch "$ARCH" --build-only || exit 1 ROBOT_BIN="build/bench_robotics_${ARCH}" if [[ ! -x "$ROBOT_BIN" || bench_robotics.cu -nt "$ROBOT_BIN" ]]; then - nvcc -std=c++17 -arch="$ARCH" -O3 -I.. -I../src -DSMS="$SMS" \ + nvcc -std=c++17 -arch="$ARCH" -O3 -I.. -I../src -DGLASS_TARGET_SM="$SMS" \ bench_robotics.cu -o "$ROBOT_BIN" || exit 1 fi BODY_BIN="build/bench_body_dispatch_${ARCH}" if [[ ! -x "$BODY_BIN" || bench_body_dispatch.cu -nt "$BODY_BIN" ]]; then - nvcc -std=c++17 -arch="$ARCH" -O3 -I.. -I../src -DSMS="$SMS" \ + nvcc -std=c++17 -arch="$ARCH" -O3 -I.. -I../src -DGLASS_TARGET_SM="$SMS" \ bench_body_dispatch.cu -o "$BODY_BIN" || exit 1 fi if [[ "$BUILD_ONLY" == 1 ]]; then @@ -198,7 +198,7 @@ run_timed_legs() { # freshest of each into DEST (mv, so the next mode can't pick up stale files; # the sentinel guards against packaging captures committed in the repo). local pat latest - for pat in mega_sweep_ paper_hostblas_ paper_fusion_; do + for pat in mega_sweep_ nvt_valid_ paper_hostblas_ paper_fusion_; do latest=$(ls -t ${pat}*.txt 2>/dev/null | head -1) if [[ -n "$latest" && "$latest" -nt "$DEST/.legs_start" ]]; then mv "$latest" "$DEST/" diff --git a/bench/run_mega_sweep.sh b/bench/run_mega_sweep.sh index a196ad7..c6c62b9 100755 --- a/bench/run_mega_sweep.sh +++ b/bench/run_mega_sweep.sh @@ -1,7 +1,7 @@ #!/usr/bin/env bash -# Full three-contender mega sweep for a quiet GPU: warp vs block(SIMT) vs nvidia(MathDx), -# across NPROB=1 (single-problem latency) → large (throughput), all ops, N up to 128. -# fp32 runs the full 3-way; fp64 runs warp/block only (the nvidia wrappers are float-only). +# Full native/NVIDIA execution-scope sweep for a quiet GPU: thread, warp, +# block(SIMT), NVIDIA block, and NVIDIA thread where supported, across batch +# regimes, both precisions, all ladder ops, N up to 128. # Compiles bench_mega_sweep.cu with cuBLASDx + cuSOLVERDx (needs MATHDX_ROOT). Captures to a # timestamped file. Run on an idle GPU; do NOT run other GPU/heavy-CPU work concurrently. # @@ -15,14 +15,14 @@ OUT="mega_sweep_$(date +%Y%m%d_%H%M).txt" if [ -z "$MATHDX_ROOT" ] || [ ! -f "$MATHDX_ROOT/include/cublasdx.hpp" ]; then echo "ERROR: MATHDX_ROOT not set or cublasdx.hpp missing — the nvidia leg needs MathDx." >&2 - echo " Set MATHDX_ROOT, or run the 2-way warp/block bench by compiling without the -D flags." >&2 + echo " Set MATHDX_ROOT, or compile without the -D flags for the native-only ladder." >&2 exit 1 fi -echo "==> compiling 3-way (cuBLASDx + cuSOLVERDx, sm=$SMS) ..." +echo "==> compiling native + NVIDIA block/thread ladder (sm=$SMS) ..." nvcc -std=c++17 -arch="$ARCH" -O3 --expt-relaxed-constexpr -Xptxas -O1 -I.. -I../src \ -I"$MATHDX_ROOT/include" -I"$MATHDX_ROOT/external/cutlass/include" \ - -DGLASS_BENCH_CUBLASDX -DGLASS_BENCH_CUSOLVERDX -DSMS="$SMS" \ + -DGLASS_BENCH_CUBLASDX -DGLASS_BENCH_CUSOLVERDX -DGLASS_TARGET_SM="$SMS" \ -DCUSOLVERDX_IGNORE_NVBUG_5288270_ASSERT -rdc=true -dlto \ -L"$MATHDX_ROOT/lib" -lcusolverdx -lcublas -lcusolver -lcudart \ bench_mega_sweep.cu -o "$BIN" @@ -34,10 +34,10 @@ nvcc -std=c++17 -arch="$ARCH" -O3 --expt-relaxed-constexpr -Xptxas -O1 -I.. -I.. # (NPROB reps): more reps for small NPROB to amortize launch; fewer for large. for cfg in "1 3000" "64 1500" "1024 700" "8192 500" "32768 200"; do set -- $cfg - echo "################ NPROB=$1 reps=$2 dtype=f32 (3-way) ################" + echo "################ NPROB=$1 reps=$2 dtype=f32 ################" "$BIN" "$1" "$2" f32 echo - echo "################ NPROB=$1 reps=$2 dtype=f64 (warp/block) ################" + echo "################ NPROB=$1 reps=$2 dtype=f64 ################" "$BIN" "$1" "$2" f64 echo done diff --git a/bench/run_quiet_audit.sh b/bench/run_quiet_audit.sh index daf4373..e41c015 100755 --- a/bench/run_quiet_audit.sh +++ b/bench/run_quiet_audit.sh @@ -72,6 +72,7 @@ one_new_capture() { } ladder="$(one_new_capture 'mega_sweep_*.txt')" +nvt_valid="$(one_new_capture 'nvt_valid_*.txt')" body="$(one_new_capture 'body_dispatch_sweep_*.txt')" reduced="$(one_new_capture 'reduced_sweep_*.txt')" blas2="$(one_new_capture 'blas2_sweep_*.txt')" @@ -85,6 +86,7 @@ echo "── offline regeneration from immutable captures ─────── python3 bench/tune.py --sm "$SMS" \ --legs ladder,body,reduced,blas2,rect,solvers,figures \ --from-ladder "$ladder" \ + --from-nvt-valid "$nvt_valid" \ --from-body "$body" \ --from-reduced "$reduced" \ --from-blas2 "$blas2" \ diff --git a/bench/timing_common.cuh b/bench/timing_common.cuh index 672973c..ca8dc6d 100644 --- a/bench/timing_common.cuh +++ b/bench/timing_common.cuh @@ -12,10 +12,12 @@ // margin it is about to resolve; // * MUTATION INVARIANT: reps run with NO restore between them, so in-place // ops (potrf/ldlt/…) re-process their own output from rep 2 on. That is -// timing-benign ONLY for branch-free ops whose control flow is -// data-independent (all currently laddered ops; GPU NaN/denormal -// arithmetic is full-speed). Do NOT time a CHECK-gated or pivoted op -// through this loop — its data-dependent branches would time garbage. +// a steady-throughput characterization ONLY for branch-free ops whose +// control flow is data-independent. It is not sufficient evidence for an +// in-place solver default: NVIDIA-thread ladder winners also pass the +// independent-valid-batch veto in bench_nvt_valid.cu. Do NOT time a +// CHECK-gated or pivoted op through this loop — its data-dependent branches +// would time garbage. #pragma once #include #include diff --git a/bench/tune.py b/bench/tune.py index fedf691..27493ab 100755 --- a/bench/tune.py +++ b/bench/tune.py @@ -4,31 +4,35 @@ python bench/tune.py --sm auto [--margin 0.05] [--quick] [--legs ...] -It drives the three measurement harnesses and routes every verdict through the +It drives the measurement harnesses and routes every verdict through the one shared tie rule in ``bench/tune_pick.py`` (a dependency-carrying impl wins only if it clears the margin; between SIMT tiers, any tier within the ±2% SIMT tie band of the fastest takes the cell if it is simpler — thread ≻ warp ≻ block), so no table bakes sub-noise jitter and a pure-noise re-run reproduces the same tables. The legs: - ladder bench_mega_sweep.cu → thread/warp/block/nvidia ladder in glass-defaults.cuh - (thread — one problem/thread, N<=7 — is a + ladder bench_mega_sweep.cu + bench_nvt_valid.cu + → native/NVIDIA thread/warp/block ladder in glass-defaults.cuh + (native thread — one problem/thread — is a dependency-free contender alongside warp/block: the shared pick takes the cheapest SIMT tier — with ties inside the ±2% SIMT band resolving to the simpler tier — so a fresh sweep emits `backend::thread` wherever the low-DOF packing - actually wins) - (per-arch constexpr ideal_sm* tables + the SM + actually wins; every NVIDIA-thread pick must + also pass the independent-valid-batch veto) + (paired per-arch MathDx/native-only tables + the SM dispatch switch; a first-time arch — e.g. sm_87 on a Jetson Orin — gets a new table + case, other arches' tables are left untouched) + body bench_body_dispatch.cu → compatible thread-0/warp-0/block bodies + behind the fixed block-scope bare interface shapes bench/autotune.py → per-(M,N,K) cuBLASDx-vs-SIMT table in src/nvidia/tuning_table.cuh (needs MATHDX_ROOT) - reduced bench_reduced.cu → validates serial-vs-reduced crossover against - suggested_use_reduced<>; rewrites the reduced section of RESULTS.md + reduced bench_reduced.cu → characterizes serial-vs-reduced crossover and + validates the conservative standard policy; rewrites RESULTS.md blas2 bench_blas2.cu → warp/block sweep of the ops the ladder misses - (syrk/syr2k/ldlt/ldltsv/inv/trmv/ger); reports picks + (syrk/syr2k/ldlt/ldlt_solve/inv/trmv/ger); reports picks into RESULTS.md (blas2 section) + regenerates the per-arch blas2_sm* table (2-impl ops only) rect bench_rect.cu → warp/block sweep of rectangular gemv/gemm shapes; @@ -42,8 +46,9 @@ figures export_sweep_figures → docs _static/*.png ladders + sweep_winners.txt All ops are *measured and recorded*; a dispatch picker is regenerated only for -ops with ≥2 genuinely-competing impls (the 6 ladder ops, the per-shape cuBLASDx -table, and the reduced corner). Single-impl families are reported, not picked. +ops with ≥2 genuinely competing implementations. Reduced GEMM remains an +explicit opt-in because its isolated wins do not justify another public advisor +axis. Single-implementation families are reported, not picked. EXECUTION DISCIPLINE: perf timing must be ISOLATED — run on a quiet GPU with no concurrent CPU/GPU load. Build/iterate the tool offline with the ``--from-*`` @@ -180,7 +185,7 @@ def run_isolated(argv, force=False): def _fatbin_build_mega(sms, mdx): - """4-tier build for hosts where libcusolverdx.a is foreign (the MathDx + """MathDx ladder build for hosts where libcusolverdx.a is foreign (the tarball ships x86-64 objects only — e.g. Jetson/aarch64). cuSOLVERDx also ships an LTO-IR `libcusolverdx.fatbin`, which is host-arch-independent but only legal as a DEVICE-LINK input, so the build is staged: @@ -189,7 +194,8 @@ def _fatbin_build_mega(sms, mdx): common = ["-std=c++17", f"-arch=sm_{sms // 10}", "-O3", "--expt-relaxed-constexpr", "-Xptxas", "-O1", "-I..", "-I../src", f"-I{mdx/'include'}", f"-I{mdx/'external'/'cutlass'/'include'}", - "-DGLASS_BENCH_CUBLASDX", "-DGLASS_BENCH_CUSOLVERDX", f"-DSMS={sms}", + "-DGLASS_BENCH_CUBLASDX", "-DGLASS_BENCH_CUSOLVERDX", + f"-DGLASS_TARGET_SM={sms}", "-DCUSOLVERDX_IGNORE_NVBUG_5288270_ASSERT"] src = (BENCH_DIR / "bench_mega_sweep.cu").read_bytes() key = hashlib.sha256(src + lib_digest().encode() @@ -226,18 +232,19 @@ def build_mega_sweep(sms, mdx, allow_no_mathdx=False): print(" bench_mega_sweep: MathDx absent -> 3-tier (thread/warp/block)") flags = ["nvcc", "-std=c++17", f"-arch=sm_{sms // 10}", "-O3", "--expt-relaxed-constexpr", "-Xptxas", "-O1", "-I..", "-I../src", - f"-DSMS={sms}", "bench_mega_sweep.cu"] + f"-DGLASS_TARGET_SM={sms}", "bench_mega_sweep.cu"] binp, status = cached_build("mega_sweep_simt", "bench_mega_sweep.cu", flags, sms) elif platform.machine() != "x86_64": # The tarball's libcusolverdx.a is x86-64-only; use the fatbin path. - print(" bench_mega_sweep: non-x86 host -> 4-tier via cusolverdx FATBIN") + print(" bench_mega_sweep: non-x86 host -> NVIDIA block/thread via cusolverdx FATBIN") binp, status = _fatbin_build_mega(sms, mdx) else: flags = ["nvcc", "-std=c++17", f"-arch=sm_{sms // 10}", "-O3", "--expt-relaxed-constexpr", "-Xptxas", "-O1", "-I..", "-I../src", f"-I{mdx/'include'}", f"-I{mdx/'external'/'cutlass'/'include'}", - "-DGLASS_BENCH_CUBLASDX", "-DGLASS_BENCH_CUSOLVERDX", f"-DSMS={sms}", + "-DGLASS_BENCH_CUBLASDX", "-DGLASS_BENCH_CUSOLVERDX", + f"-DGLASS_TARGET_SM={sms}", "-DCUSOLVERDX_IGNORE_NVBUG_5288270_ASSERT", "-rdc=true", "-dlto", f"-L{mdx/'lib'}", "-lcusolverdx", "-lcublas", "-lcusolver", "-lcudart", "bench_mega_sweep.cu"] @@ -248,6 +255,72 @@ def build_mega_sweep(sms, mdx, allow_no_mathdx=False): return binp +def _fatbin_build_nvt_valid(sms, mdx): + """Build the small valid-input confirmation harness on non-x86 hosts.""" + common = ["-std=c++17", f"-arch=sm_{sms // 10}", "-O3", + "--expt-relaxed-constexpr", "-Xptxas", "-O1", "-I..", "-I../src", + f"-I{mdx/'include'}", f"-I{mdx/'external'/'cutlass'/'include'}", + "-DGLASS_BENCH_CUSOLVERDX", + f"-DGLASS_TARGET_SM={sms}", + "-DCUSOLVERDX_IGNORE_NVBUG_5288270_ASSERT"] + src = (BENCH_DIR / "bench_nvt_valid.cu").read_bytes() + key = hashlib.sha256(src + lib_digest().encode() + + " ".join(common + ["fatbin"]).encode()).hexdigest()[:12] + binp = cache_dir(sms) / f"nvt_valid_fatbin_{key}" + if binp.exists(): + return binp, "cached" + obj, dlk = str(binp) + ".o", str(binp) + "_dlink.o" + steps = [ + ["nvcc"] + common + ["-rdc=true", "-dlto", "-dc", + "bench_nvt_valid.cu", "-o", obj], + ["nvcc", f"-arch=sm_{sms // 10}", "-dlto", "-dlink", obj, + str(mdx / "lib" / "libcusolverdx.fatbin"), "-o", dlk], + ["nvcc", f"-arch=sm_{sms // 10}", obj, dlk, + "-lcublas", "-lcusolver", "-lcudart", "-o", str(binp)], + ] + for cmd in steps: + if run(cmd, cwd=BENCH_DIR).returncode != 0: + return None, "fail" + return binp, "built" + + +def build_nvt_valid(sms, mdx): + if mdx is None: + sys.exit("ERROR: NVIDIA-thread confirmation needs MATHDX_ROOT.") + if platform.machine() != "x86_64": + binp, status = _fatbin_build_nvt_valid(sms, mdx) + else: + flags = ["nvcc", "-std=c++17", f"-arch=sm_{sms // 10}", "-O3", + "--expt-relaxed-constexpr", "-Xptxas", "-O1", "-I..", "-I../src", + f"-I{mdx/'include'}", f"-I{mdx/'external'/'cutlass'/'include'}", + "-DGLASS_BENCH_CUSOLVERDX", + f"-DGLASS_TARGET_SM={sms}", + "-DCUSOLVERDX_IGNORE_NVBUG_5288270_ASSERT", "-rdc=true", "-dlto", + f"-L{mdx/'lib'}", "-lcusolverdx", "-lcublas", "-lcusolver", "-lcudart", + "bench_nvt_valid.cu"] + binp, status = cached_build("nvt_valid", "bench_nvt_valid.cu", flags, sms) + if status == "fail": + sys.exit("ERROR: bench_nvt_valid compile failed.") + print(f" bench_nvt_valid: {status} ({binp.name})") + return binp + + +def run_nvt_valid(binp, sms, margin, force=False): + """Capture both precisions at the ladder's NPROB=8192 policy point.""" + path = BENCH_DIR / f"nvt_valid_{time.strftime('%Y%m%d_%H%M%S')}.txt" + lines = provenance("nvt_valid", sms, margin) + lines += [f"# nvt_valid {time.strftime('%c')} (bench/tune.py)", ""] + path.write_text("\n".join(lines) + "\n") + for dtype in ("f32", "f64"): + print(f" -> nvt_valid NPROB=8192 requested_slots=64 {dtype}") + stdout = run_isolated([str(binp), "8192", "64", dtype], force) + with open(path, "a") as stream: + stream.write(stdout) + stream.write("\n") + print(f"==> wrote {path.relative_to(GLASS_DIR)}") + return path + + def run_mega_sweep(binp, quick, sms, margin, prefix="mega_sweep", sched=None, force=False): """Run a ladder-style harness (mega/blas2/rect/solvers share the CLI + @@ -305,10 +378,12 @@ def _ladder_expr(winners, dtype, op): runs[-1] = (N, be) else: runs.append((N, be)) + def cpp_backend(name): + return "nvidia_block" if name == "nvidia" else name if len(runs) == 1: - return f"backend::{runs[0][1]}" - parts = [f"N <= {hi}u ? backend::{be}" for hi, be in runs[:-1]] - return " : ".join(parts) + f" : backend::{runs[-1][1]}" + return f"backend::{cpp_backend(runs[0][1])}" + parts = [f"N <= {hi}u ? backend::{cpp_backend(be)}" for hi, be in runs[:-1]] + return " : ".join(parts) + f" : backend::{cpp_backend(runs[-1][1])}" # Ladder-style rows print `spread<=X%` (row-max over cells); the reduced and @@ -336,17 +411,68 @@ def warn_jittery_rows(text, margin, label): return len(jittery) -def winners_from_sweep(text, margin): - """(dtype, op) -> {N: backend} under the shared margin (nvidia is the dep).""" +def winners_from_sweep(text, margin, native_only=False): + """(dtype, op) -> {N: backend} under the shared dependency margin. + + ``native_only`` removes both vendor measurements before applying the same + native SIMT tie rule. This emits an actual measured runner-up table instead + of approximating vendor cells with a size heuristic. + """ cells = tp.parse_mega_sweep(text, nprob=8192) winners = {} for (dt, op, N), times in cells.items(): - win = tp.pick(times, margin, {"nvidia"}) + if native_only: + times = {name: value for name, value in times.items() + if name not in {"nvidia", "nvidia_thread"}} + win = tp.pick(times, margin, {"nvidia", "nvidia_thread"}) if win: winners.setdefault((dt, op), {})[N] = win return winners +def apply_nvt_valid_veto(winners, confirmation_text, margin): + """Veto NVIDIA-thread picks that do not reproduce on independent inputs. + + The confirmation leg is deliberately asymmetric: it may replace a main- + ladder NVIDIA-thread winner with the valid-input native winner, but it does + not promote NVIDIA-thread into any cell. Every selected NVIDIA-thread cell + must have an exact confirmation row; incomplete evidence is a hard error. + Returns ``(updated_winners, veto_count)``. + """ + confirmed = tp.parse_nvt_valid(confirmation_text, nprob=8192) + spreads = tp.parse_nvt_valid_spreads(confirmation_text, nprob=8192) + updated = {key: dict(value) for key, value in winners.items()} + vetoes = 0 + for (dtype, op), cells in updated.items(): + for N, winner in list(cells.items()): + if winner != "nvidia_thread": + continue + key = (dtype, op, N) + if key not in confirmed: + sys.exit("ERROR: NVIDIA-thread ladder winner lacks valid-input " + f"confirmation: {dtype} {op} N={N}.") + times = confirmed[key] + native_names = ("thread", "warp", "block") + raw_native = min(native_names, key=lambda name: times[name]) + native_lo = times[raw_native] + native_hi = native_lo * (1.0 + spreads[key][raw_native] / 100.0) + nvt_lo = times["nvidia_thread"] + nvt_hi = nvt_lo * (1.0 + spreads[key]["nvidia_thread"] / 100.0) + guaranteed_win = nvt_hi < native_lo * (1.0 - margin) + guaranteed_loss = nvt_lo >= native_hi * (1.0 - margin) + if not guaranteed_win and not guaranteed_loss: + sys.exit("ERROR: valid-input confirmation cannot resolve the " + f"±{margin*100:.0f}% margin for {dtype} {op} N={N}: " + f"native {raw_native} interval=[{native_lo:.4f}," + f"{native_hi:.4f}], NVIDIA thread interval=" + f"[{nvt_lo:.4f},{nvt_hi:.4f}].") + if guaranteed_loss: + native_times = {name: times[name] for name in native_names} + cells[N] = tp.pick(native_times, margin) + vetoes += 1 + return updated, vetoes + + def emit_ideal_body(winners, fname, ops=tp.LADDER_OPS): lines = [f"constexpr backend {fname}(op o, uint32_t N, bool f64) {{", " switch (o) {"] @@ -367,23 +493,39 @@ def emit_ideal_body(winners, fname, ops=tp.LADDER_OPS): return "\n".join(lines) -def regen_ladder(sweep_text, margin, src_name, sms): +def regen_ladder(sweep_text, margin, src_name, sms, + nvt_valid_text=None, nvt_valid_name=None): """Regenerate this arch's table block in glass-defaults.cuh (replace if the arch was swept before, insert after the last table block if it's new) and rebuild the SM dispatch case-list from every table block present.""" arch = sms // 10 warn_jittery_rows(sweep_text, margin, "ladder") winners = winners_from_sweep(sweep_text, margin) + native_winners = winners_from_sweep(sweep_text, margin, native_only=True) if not winners: sys.exit("ERROR: no NPROB=8192 verdicts parsed from the sweep.") + has_nvt = any(backend == "nvidia_thread" + for cells in winners.values() for backend in cells.values()) + if has_nvt and nvt_valid_text is None: + sys.exit("ERROR: this ladder selects NVIDIA-thread but no independent-" + "valid-input capture was supplied; pass --from-nvt-valid or " + "run the ladder online.") + vetoes = 0 + if has_nvt: + winners, vetoes = apply_nvt_valid_veto(winners, nvt_valid_text, margin) begin, end = _LAD_BEGIN.format(a=arch), _LAD_END.format(a=arch) region = "\n".join([ begin, f"// Source sweep: {src_name} tie margin: ±{margin*100:.0f}% " - "(nvidia must clear it; SIMT ties ±2% prefer thread>warp>block)", - "// Returns the *ideal* tier assuming nvidia is linked; " - "nv_available() filters after.", + "(NVIDIA block/thread must clear it; SIMT ties ±2% prefer thread>warp>block)", + *([f"// NVIDIA-thread valid-input veto: {nvt_valid_name} " + f"({vetoes} ladder pick{'s' if vetoes != 1 else ''} vetoed)"] + if nvt_valid_name else []), + "// Paired tables preserve the measured native runner-up for callers that", + "// do not opt into MathDx; both use the same capture and SIMT tie rule.", emit_ideal_body(winners, f"ideal_sm{arch}"), + "", + emit_ideal_body(native_winners, f"native_sm{arch}"), end]) text = DEFAULTS.read_text() if begin in text: @@ -401,12 +543,13 @@ def regen_ladder(sweep_text, margin, src_name, sms): arches = sorted(int(a) for a in _LAD_RE.findall(text)) if _DIS_BEGIN not in text or _DIS_END not in text: sys.exit(f"ERROR: dispatch markers missing from {DEFAULTS.name}.") - cases = "".join(f" case {a * 10}u: return ideal_sm{a}(o, N, f64);\n" + cases = "".join(f" case {a * 10}u: return allow_nvidia " + f"? ideal_sm{a}(o, N, f64) : native_sm{a}(o, N, f64);\n" for a in arches) pre, _, rest = text.partition(_DIS_BEGIN) _, _, post = rest.partition(_DIS_END) text = pre + _DIS_BEGIN + "\n" + cases + " " + _DIS_END + post - return text, len(winners) + return text, len(winners), vetoes # ─── blas2 + rect header tables (glass-defaults.cuh; warp-vs-block only) ───── @@ -417,7 +560,7 @@ def regen_ladder(sweep_text, margin, src_name, sms): # 2-impl blas2 ops are tabled — inv/trmv/ger are block-only and stay # report-only by the "single-impl families are reported, not picked" rule. -B2_TABLE_OPS = ("syrk", "syr2k", "ldlt", "ldltsv") +B2_TABLE_OPS = ("syrk", "syr2k", "ldlt", "ldlt_solve") _B2_BEGIN = "// === BEGIN tune.py blas2 sm_{a} ===" _B2_END = "// === END tune.py blas2 sm_{a} ===" @@ -499,8 +642,13 @@ def _emit_rect_fn(cells, op_name, fname, dims_names, margin): continue lines.append(f" if ({'f64' if f64 else '!f64'}) {{") for dims, be in rows: + # The benchmark grammar retains its historical (M,K,N) tuple; + # the public C++ API is uniformly (M,N,K). + if op_name == "gemm": + dims = (dims[0], dims[2], dims[1]) cond = " && ".join(f"{n} == {v}u" for n, v in zip(dims_names, dims)) - lines.append(f" if ({cond}) return backend::{be};") + cpp_backend = "nvidia_block" if be == "nvidia" else be + lines.append(f" if ({cond}) return backend::{cpp_backend};") lines.append(" }") lines += [" return backend::block;", "}"] return "\n".join(lines) @@ -519,14 +667,14 @@ def regen_rect_table(sweep_text, margin, src_name, sms): f"// Source sweep: {src_name} tie margin: ±{margin*100:.0f}% " "(SIMT ties ±2% prefer the simpler tier); exact shapes only", _emit_rect_fn(cells, "gemv", f"rect_gemv_sm{arch}", ("M", "N"), margin), - _emit_rect_fn(cells, "gemm", f"rect_gemm_sm{arch}", ("M", "K", "N"), margin), + _emit_rect_fn(cells, "gemm", f"rect_gemm_sm{arch}", ("M", "N", "K"), margin), end]) text = _splice_arch_block(DEFAULTS.read_text(), begin, end, _RECT_END_RE, region) arches = sorted(int(a) for a in _RECT_RE.findall(text)) for dis_begin, dis_end, fn_prefix in _RECT_DIS: if dis_begin not in text or dis_end not in text: sys.exit(f"ERROR: rect dispatch markers missing from {DEFAULTS.name}.") - argstr = "M, N, f64" if "gemv" in fn_prefix else "M, K, N, f64" + argstr = "M, N, f64" if "gemv" in fn_prefix else "M, N, K, f64" text = _rebuild_dispatch(text, dis_begin, dis_end, arches, fn_prefix, argstr) return text, len(cells) @@ -551,7 +699,7 @@ def regen_rect_table(sweep_text, margin, src_name, sms): _BODY_SM_RE = re.compile(r"// === BEGIN tune\.py body sm_(\d+) ===") _BODY_DIS_BEGIN = "// === BEGIN tune.py body dispatch ===" _BODY_DIS_END = "// === END tune.py body dispatch ===" -BODY_OPS = ("dot", "gemv", "gemm", "chol", "trsv", "posv", "eig3", "softmax") +BODY_OPS = ("dot", "gemv", "gemm", "potrf", "trsv", "posv", "eig3", "softmax") _BODY_HDR_RE = re.compile(r"NPROB=(\d+)\s+reps=\d+\s+dtype=(f32|f64)") _BODY_SEG_RE = re.compile(r"(BLOCKBODY|WARPBODY|THREADBODY)((?:\s+tb\d+=[0-9.]+)+)") _BODY_NAME = {"BLOCKBODY": "block", "WARPBODY": "warp_in_block", @@ -560,7 +708,7 @@ def regen_rect_table(sweep_text, margin, src_name, sms): def build_body(sms): flags = ["nvcc", "-std=c++17", f"-arch=sm_{sms//10}", "-O3", "-I..", "-I../src", - f"-DSMS={sms}", "bench_body_dispatch.cu"] + f"-DGLASS_TARGET_SM={sms}", "bench_body_dispatch.cu"] binp, status = cached_build("body_dispatch", "bench_body_dispatch.cu", flags, sms) if status == "fail": sys.exit("ERROR: bench_body_dispatch compile failed.") @@ -579,9 +727,12 @@ def parse_body_sweep(text): if "||" not in line or nprob is None or "FAIL" in line: continue m = re.match(r"\s*(\w+?)_n(\d+)\s*\|", line) - if not m or m.group(1) not in BODY_OPS: + if not m: + continue + opn = "potrf" if m.group(1) == "chol" else m.group(1) + if opn not in BODY_OPS: continue - key = (dt, m.group(1), int(m.group(2))) + key = (dt, opn, int(m.group(2))) for bname, tbs in _BODY_SEG_RE.findall(line.split("||")[0]): pts = cells.setdefault(key, {}).setdefault(_BODY_NAME[bname], {}) for tb, ns in re.findall(r"tb(\d+)=([0-9.]+)", tbs): @@ -699,7 +850,7 @@ def regen_body(sweep_text, margin, src_name, sms): _BODY_DIS_BEGIN, "// Bodies for the bare block-scope face; unmeasured arches stay block.", "GLASS_DISPATCH_HD constexpr body dispatch_body(op o, uint32_t N, bool f64,", - " uint32_t sm = GLASS_DEFAULTS_SM) {", + " uint32_t sm = GLASS_TARGET_SM) {", " switch (sm) {", cases.rstrip("\n"), " default: break;", @@ -713,7 +864,7 @@ def regen_body(sweep_text, margin, src_name, sms): return text, moved -# ─── reduced leg: bench_reduced → validate suggested_use_reduced<> ──────────── +# ─── reduced leg: bench_reduced → characterize the explicit reduced path ─── def build_reduced(sms): flags = ["nvcc", "-std=c++17", f"-arch=sm_{sms//10}", "-O3", "-I..", "-I../src", @@ -725,13 +876,11 @@ def build_reduced(sms): return binp -def predicate_use_reduced(n_out, K, blockDim): - """Mirror of glass::suggested_use_reduced(). +def plan_uses_reduced(n_out, K, blockDim): + """Conservative policy for the measured standard/reduced leg. - Kept constant False after the 2026-08-14 sm_120 sweep: f32 had 0/48 wins; - f64 had 2/48 at one shape, which this dtype-independent signature cannot - encode safely. A future type-aware predicate may promote a repeatable - region; keep this mirror synchronized with the .cuh predicate.""" + Kept false after the 2026-08-14 sm_120 sweep: f32 had 0/48 wins and f64 + had 2/48 at one shape. A future plan may promote a repeatable region.""" return False @@ -743,8 +892,8 @@ def analyze_reduced(text, margin): margin, {"reduced"}) measured_reduced = (win == "reduced") # bench_reduced computes C(M,K)=A(M,N)·B(N,K): the contracted dim is N - # (n_out = M*K), so the predicate's K_contract is the N column. - predicted = predicate_use_reduced(r["n_out"], r["N"], r["blockDim"]) + # (n_out = M*K); keep these arguments if the plan gains a typed region. + predicted = plan_uses_reduced(r["n_out"], r["N"], r["blockDim"]) r["winner"] = win if measured_reduced: wins.append(r) @@ -776,18 +925,16 @@ def gen_reduced_block(rows, wins, mism, margin, src): f"{r['blockDim']} | {r['serial']:.4f} | {r['reduced']:.4f} | " f"**{r['serial']/r['reduced']:.2f}** |") L.append("") - L.append("Predicate `suggested_use_reduced()` = " - "`false` on every cell (K_contract is the N column here).") + L.append("The public advisor stays two-axis; reduced GEMM remains an explicit opt-in.") if mism: - L += ["", f"⚠️ **{len(mism)} config(s) disagree** with the predicate — " - "review before trusting the formula on this GPU:", ""] + L += ["", f"⚠️ **{len(mism)} config(s) favor the explicit reduced " + "variant while the conservative plan stays standard:**", ""] for r in mism: - pred = "reduced" if predicate_use_reduced(r['n_out'], r['N'], r['blockDim']) else "serial" + pred = "reduced" if plan_uses_reduced(r['n_out'], r['N'], r['blockDim']) else "serial" L.append(f"- {r['dtype']} {r['M']}×{r['N']}×{r['K']} bd={r['blockDim']} " - f"(n_out={r['n_out']}): measured **{r['winner']}**, predicate **{pred}**") + f"(n_out={r['n_out']}): measured **{r['winner']}**, plan **{pred}**") else: - L += ["", "✅ Measurement matches the predicate for every swept config — " - "the formula needs no change."] + L += ["", "✅ Measurement matches the plan for every swept config."] L += ["", _md_end("reduced")] return "\n".join(L) @@ -903,14 +1050,14 @@ def report_pick_leg(name, txt, txt_name, md_path, margin, parse, dry_run, _BLAS2_NOTE = ("inv/trmv/ger are BLOCK-ONLY (no `glass::warp::` variant, so " "nothing competes — reported, never picked); none of these ops " - "has a `glass::nvidia::` counterpart. The 2-impl ops " - "(syrk/syr2k/ldlt/ldltsv) regenerate the shipped per-arch " + "has an NVIDIA counterpart. The 2-impl ops " + "(syrk/syr2k/ldlt/ldlt_solve) regenerate the shipped per-arch " "`blas2_sm*` table in glass-defaults.cuh (since 2026-08-06).") _RECT_NOTE = ("nvidia leg skipped for rectangular shapes (needs new per-shape " "DEFINE_NVIDIA_* machinery; cuBLASDx-vs-SIMT per (M,N,K) lives in " "the `shapes` leg). Measured shapes regenerate the shipped " "exact-shape `rect_*_sm*` pickers in glass-defaults.cuh " - "(`suggested_backend_rect_gemv/gemm<>`, since 2026-08-06); " + "(`recommend`, since 2026-08-06); " "unmeasured shapes stay block.") @@ -1098,8 +1245,8 @@ def main(): p.add_argument("--allow-no-mathdx", action="store_true", help="let the ladder leg run without MATHDX_ROOT as a 3-tier " "(thread/warp/block) SIMT sweep — the regenerated table " - "simply lacks the nvidia contender. Required on Tegra/" - "Jetson, where MathDx does not ship.") + "simply lacks NVIDIA contenders. Use only when MathDx " + "headers/fatbins are unavailable.") p.add_argument("--dry-run", action="store_true", help="regenerate + diff against in-tree tables, write nothing") p.add_argument("--force", action="store_true", @@ -1107,6 +1254,9 @@ def main(): "compute PIDs appearing during a leg still invalidate it") p.add_argument("--from-ladder", metavar="TXT", help="skip ladder build/run; regenerate from this mega_sweep .txt") + p.add_argument("--from-nvt-valid", metavar="TXT", + help="independent-valid-input companion capture required when " + "--from-ladder selects NVIDIA-thread") p.add_argument("--from-body", metavar="TXT", help="skip body build/run; regenerate dispatch_body() from " "this body_dispatch_sweep .txt") @@ -1132,7 +1282,7 @@ def main(): bad = [l for l in legs if l not in ALL_LEGS] if bad: sys.exit(f"unknown leg(s) {bad}; choose from {ALL_LEGS}") - offline = bool(args.from_ladder or args.from_body or args.from_reduced + offline = bool(args.from_ladder or args.from_nvt_valid or args.from_body or args.from_reduced or args.from_blas2 or args.from_rect or args.from_solvers) sms = None if (args.sm == "auto" and offline) else ( detect_sm() if args.sm == "auto" else int(args.sm)) @@ -1153,6 +1303,8 @@ def main(): if "ladder" in legs: print("── prebuild: ladder ──────────────────────────────────────") build_mega_sweep(sms, mdx, args.allow_no_mathdx) + if mdx is not None: + build_nvt_valid(sms, mdx) if "body" in legs: print("── prebuild: body ────────────────────────────────────────") build_body(sms) @@ -1196,14 +1348,26 @@ def main(): "regenerated on the desktop).") sweep_path = pathlib.Path(args.from_ladder) sweep_text = sweep_path.read_text() + nvt_valid_path = (pathlib.Path(args.from_nvt_valid) + if args.from_nvt_valid else None) else: binp = build_mega_sweep(sms, mdx, args.allow_no_mathdx) sweep_path = run_mega_sweep( binp, args.quick, sms, args.margin, sched=user_sched, force=args.force) sweep_text = sweep_path.read_text() - new_defaults, n = regen_ladder(sweep_text, args.margin, sweep_path.name, sms) - print(f" regenerated ideal_sm{sms // 10} from {n} (dtype,op) groups") + nvt_valid_path = None + if mdx is not None: + nvt_bin = build_nvt_valid(sms, mdx) + nvt_valid_path = run_nvt_valid(nvt_bin, sms, args.margin, + force=args.force) + nvt_valid_text = (nvt_valid_path.read_text() + if nvt_valid_path is not None else None) + new_defaults, n, vetoes = regen_ladder( + sweep_text, args.margin, sweep_path.name, sms, nvt_valid_text, + nvt_valid_path.name if nvt_valid_path is not None else None) + print(f" regenerated ideal_sm{sms // 10} from {n} (dtype,op) groups; " + f"valid-input vetoes={vetoes}") if args.dry_run: changed["ladder"] = show_diff(DEFAULTS, new_defaults, "glass-defaults.cuh") else: @@ -1280,9 +1444,9 @@ def main(): warn_jittery_rows(rtxt, args.margin, "reduced") rows, wins, mism = analyze_reduced(rtxt, args.margin) print(f" {len(rows)} configs, reduced wins {len(wins)}, " - f"predicate mismatches {len(mism)}") + f"conservative-plan exceptions {len(mism)}") if mism: - print(" ⚠️ predicate disagrees with measurement — see bench/RESULTS.md") + print(" ⚠️ explicit reduced wins remain outside the conservative plan") block = gen_reduced_block(rows, wins, mism, args.margin, rtxt_path.name) md = splice_results_md(RESULTS_MD.read_text(), block, "reduced") if args.dry_run: @@ -1366,7 +1530,8 @@ def main(): # ── figures ── if "figures" in legs: print("── figures ───────────────────────────────────────────────") - sweep_for_fig = args.from_ladder + sweep_for_fig = (str(pathlib.Path(args.from_ladder).resolve()) + if args.from_ladder else None) if not sweep_for_fig: cands = sorted(glob.glob(str(BENCH_DIR / "mega_sweep_*.txt"))) sweep_for_fig = cands[-1] if cands else None @@ -1377,8 +1542,8 @@ def main(): else: r = run([sys.executable, "export_sweep_figures.py", sweep_for_fig], cwd=BENCH_DIR) if r.returncode != 0: - print(" ⚠️ figures leg failed (needs matplotlib: `pip install matplotlib` " - "into the env running tune.py). Tables above are unaffected.") + print(" ⚠️ figures leg failed; inspect the renderer error above " + "(matplotlib is one possible missing dependency). Tables are unaffected.") if args.dry_run: moved = [k for k, v in changed.items() if v] diff --git a/bench/tune_pick.py b/bench/tune_pick.py index bd83d9b..ea6271a 100755 --- a/bench/tune_pick.py +++ b/bench/tune_pick.py @@ -2,9 +2,10 @@ """Shared tie-margin + sweep parsers for the unified autotuner (bench/tune.py). This is the *one* place the noise margin lives. Every defaults table GLASS ships -— the warp/block/nvidia ladder (``glass-defaults.cuh``), the per-shape +— the native thread/warp/block plus NVIDIA block/thread ladder +(``glass-defaults.cuh``), the per-shape cuBLASDx-vs-SIMT table (``src/nvidia/tuning_table.cuh``), and the -serial-vs-reduced picker (``suggested_use_reduced<>``) — routes its verdict +serial-vs-reduced characterization — routes its verdict through :func:`pick` so none of them bakes sub-noise jitter, and so a pure-noise re-run reproduces the same table. @@ -18,8 +19,9 @@ sm_87 replication pair: gemm f64 N=48 flipped block↔warp on a <1% gap). That single rule subsumes all three legacy decisions: -* ladder: ``dependency={"nvidia"}`` — block/warp (pure SIMT, no MathDx) is the - incumbent; nvidia must clear the margin to be chosen. +* ladder: ``dependency={"nvidia", "nvidia_thread"}`` — native thread/warp/block + are the incumbents; either MathDx implementation must clear the + margin to be chosen. * shapes: ``dependency={"cublasdx"}`` — SIMT is the incumbent (autotune.py's original pairwise ±margin rule, generalized). * reduced: ``dependency={"reduced"}`` — serial ``gemm`` is the incumbent. @@ -118,25 +120,30 @@ def verdict(timings, margin=0.05, dependency=(), noise_floor=0.0, # ─── parsers ──────────────────────────────────────────────────────────────── -LADDER_OPS = ("dot", "gemv", "gemm", "chol", "trsv", "posv") +LADDER_OPS = ("dot", "gemv", "gemm", "potrf", "trsv", "posv") _HDR_RE = re.compile(r"NPROB=(\d+).*dtype=(f32|f64)") # Raw per-backend ns from a mega_sweep row: # " N= | BLOCK ... | WARP ... [| THREAD ...] || block tb= -# warp w= [thread t=] [nv=] -> ..." +# warp w= [thread t=] [nv=] +# [nvt t=] -> ..." # The thread group is OPTIONAL on purpose: it is absent from archived sweep # .txt files (every run before the tier existed — `tune.py --from-ladder` replays # them) and from mid-2026-07 captures where the harness gated the tier to N<=16 # (since lifted to the full domain so all contenders share the same points). # Keep it optional or old sweeps stop parsing and regen silently drops every op. _ROW_RE = re.compile( - r"^(dot|gemv|gemm|chol|trsv|posv)\s+N=(\d+)\b.*\|\|\s*" + r"^(dot|gemv|gemm|chol|potrf|trsv|posv)\s+N=(\d+)\b.*\|\|\s*" r"block\s+tb\d+=([\d.]+)\s+warp\s+w\d+=([\d.]+)" - r"(?:\s+thread\s+t\d+=([\d.]+))?(?:\s+nv=([\d.]+))?") + r"(?:\s+thread\s+t\d+=([\d.]+))?(?:\s+nv=([\d.]+))?" + r"(?:\s+nvt\s+t\d+=([\d.]+))?") def parse_mega_sweep(text, nprob=8192): - """``(dtype, op, N) -> {block, warp[, thread][, nvidia]}`` raw ns/problem at ``nprob``. + """``(dtype, op, N) -> backend times at ``nprob``. + + Optional keys are ``thread``, ``nvidia``, and ``nvidia_thread``; their + absence preserves replay compatibility with every older capture. Reads the raw per-backend numbers (NOT the harness's ``-> WINNER`` verdict, which is a bare argmin with no margin) so :func:`pick` can re-decide the @@ -154,22 +161,71 @@ def parse_mega_sweep(text, nprob=8192): m = _ROW_RE.match(line.strip()) if m: op, N = m.group(1), int(m.group(2)) + op = "potrf" if op == "chol" else op d = {"block": float(m.group(3)), "warp": float(m.group(4))} if m.group(5): d["thread"] = float(m.group(5)) # absent in pre-tier sweeps and at N>16 if m.group(6): d["nvidia"] = float(m.group(6)) + if m.group(7): + d["nvidia_thread"] = float(m.group(7)) data[(dtype, op, N)] = d return data -BLAS2_OPS = ("syrk", "syr2k", "ldlt", "ldltsv", "inv", "trmv", "ger") +_NVT_VALID_RE = re.compile( + r"^NVT_VALID\s+op=(potrf|trsv|posv)\s+N=(\d+)\s+" + r"dtype=(f32|f64)\s+nprob=(\d+)\s+slots=(\d+)\s+" + r"block=([\d.]+)\s+block_shape=(\d+)\s+block_spread=([\d.]+)\s+" + r"warp=([\d.]+)\s+warp_shape=(\d+)\s+warp_spread=([\d.]+)\s+" + r"thread=([\d.]+)\s+thread_shape=(\d+)\s+thread_spread=([\d.]+)\s+" + r"nvidia_thread=([\d.]+)\s+nvt_shape=(\d+)\s+nvt_spread=([\d.]+)$") + + +def parse_nvt_valid(text, nprob=8192): + """Parse the independent-valid-batch NVIDIA-thread confirmation leg. + + Returns ``(dtype, op, N) -> {block, warp, thread, nvidia_thread}``. + Launch-shape and trial-spread metadata remain in the capture for audit; + table generation deliberately consumes only the measured times. + """ + data = {} + for line in text.splitlines(): + m = _NVT_VALID_RE.match(line.strip()) + if not m or int(m.group(4)) != nprob: + continue + data[(m.group(3), m.group(1), int(m.group(2)))] = { + "block": float(m.group(6)), + "warp": float(m.group(9)), + "thread": float(m.group(12)), + "nvidia_thread": float(m.group(15)), + } + return data + + +def parse_nvt_valid_spreads(text, nprob=8192): + """Return per-contender trial spreads for valid-input confirmation rows.""" + data = {} + for line in text.splitlines(): + m = _NVT_VALID_RE.match(line.strip()) + if not m or int(m.group(4)) != nprob: + continue + data[(m.group(3), m.group(1), int(m.group(2)))] = { + "block": float(m.group(8)), + "warp": float(m.group(11)), + "thread": float(m.group(14)), + "nvidia_thread": float(m.group(17)), + } + return data + + +BLAS2_OPS = ("syrk", "syr2k", "ldlt", "ldlt_solve", "inv", "trmv", "ger") # Raw per-backend ns from a bench_blas2 row (same grammar as the mega sweep, but # 2-way: the warp leg is absent for the block-only ops inv/trmv/ger): # " N= | BLOCK ... [| WARP ...] || block tb= [warp w=] -> ..." _B2_ROW_RE = re.compile( - r"^(syr2k|syrk|ldltsv|ldlt|inv|trmv|ger)\s+N=(\d+)\b.*\|\|\s*" + r"^(syr2k|syrk|ldlt_solve|ldltsv|ldlt|inv|trmv|ger)\s+N=(\d+)\b.*\|\|\s*" r"block\s+tb\d+=([\d.]+)(?:\s+warp\s+w\d+=([\d.]+))?") @@ -192,6 +248,7 @@ def parse_blas2(text, nprob=8192): m = _B2_ROW_RE.match(line.strip()) if m: op, N = m.group(1), int(m.group(2)) + op = "ldlt_solve" if op == "ldltsv" else op d = {"block": float(m.group(3))} if m.group(4): d["warp"] = float(m.group(4)) @@ -278,6 +335,12 @@ def parse_reduced(text): "nvidia inside margin of the raw-best SIMT time → thread" assert pick({"block": 100, "warp": 90, "thread": 91, "nvidia": 80}, 0.05, {"nvidia"}) == "nvidia", \ "SIMT tie resolves to thread but nvidia clears the margin over raw-best warp" + assert pick({"block": 100, "warp": 90, "thread": 91, "nvidia": 89, + "nvidia_thread": 80}, 0.05, {"nvidia", "nvidia_thread"}) == "nvidia_thread", \ + "best dependency tier clears the native margin" + assert pick({"block": 100, "warp": 90, "thread": 91, "nvidia": 88, + "nvidia_thread": 87}, 0.05, {"nvidia", "nvidia_thread"}) == "thread", \ + "neither dependency tier clears the native margin" assert pick({"serial": 100, "simt": 101}, 0.05, {"cublasdx"}) == "serial", \ "impls outside SIMT_ORDER keep raw-min behavior" # SIMT tie must be measured against the raw-fastest tier, not pairwise @@ -299,16 +362,20 @@ def parse_reduced(text): _mg = "\n".join([ "################ NPROB=8192 reps=250 dtype=f32 ################", "dot N=4 | BLOCK tb32=1.00 | WARP w1=0.80 | THREAD t256=0.30" - " || block tb32=1.00 warp w1=0.80 thread t256=0.30 nv=2.00 -> THREAD", + " || block tb32=1.00 warp w1=0.80 thread t256=0.30 nv=2.00" + " nvt t64=0.20 -> NVIDIA_THREAD", "posv N=64 | BLOCK tb32=5.00 | WARP w1=6.00" " || block tb32=5.00 warp w1=6.00 nv=3.00 -> NV", ]) _mc = parse_mega_sweep(_mg) - assert _mc[("f32", "dot", 4)] == {"block": 1.0, "warp": 0.8, "thread": 0.3, "nvidia": 2.0}, _mc + assert _mc[("f32", "dot", 4)] == {"block": 1.0, "warp": 0.8, "thread": 0.3, + "nvidia": 2.0, "nvidia_thread": 0.2}, _mc assert _mc[("f32", "posv", 64)] == {"block": 5.0, "warp": 6.0, "nvidia": 3.0}, \ "thread absent at high N parses as block/warp/nvidia only" - assert pick(_mc[("f32", "dot", 4)], 0.05, {"nvidia"}) == "thread", "dot N=4 → thread wins" - # parse_blas2(): 2-way rows, warp leg optional, ldlt/ldltsv disambiguation. + assert pick(_mc[("f32", "dot", 4)], 0.05, + {"nvidia", "nvidia_thread"}) == "nvidia_thread", \ + "new trailing dependency tier parses and clears the margin" + # parse_blas2(): 2-way rows, warp leg optional, old label compatibility. _b2 = "\n".join([ "################ NPROB=8192 reps=250 dtype=f32 ################", "syrk N=8 | BLOCK tb32=1.10 tb64=1.00 | WARP w1=0.80 w2=0.90" @@ -323,7 +390,7 @@ def parse_reduced(text): ]) _c = parse_blas2(_b2) assert _c[("f32", "syrk", 8)] == {"block": 1.00, "warp": 0.80}, _c - assert _c[("f32", "ldltsv", 16)] == {"block": 3.00, "warp": 2.00}, _c + assert _c[("f32", "ldlt_solve", 16)] == {"block": 3.00, "warp": 2.00}, _c assert _c[("f32", "ldlt", 16)] == {"block": 2.50, "warp": 2.40}, _c assert _c[("f32", "inv", 8)] == {"block": 4.00}, "block-only op parses without warp" assert ("f32", "ger", 8) not in _c, "NPROB=64 section must be filtered out" diff --git a/docs/agent_debugging_guide.md b/docs/agent_debugging_guide.md index fd6d107..3eb89bc 100644 --- a/docs/agent_debugging_guide.md +++ b/docs/agent_debugging_guide.md @@ -4,19 +4,21 @@ Hard-won institutional knowledge for working on **GLASS** (*GPU Linear Algebra S Subroutines*) — the comprehensive, header-only, single-block GPU linear-algebra library. The public execution tiers are explicit **Block** `glass::block::`, **Warp** `glass::warp::`, **Thread** `glass::thread::`, and **Nvidia** -`glass::nvidia::block::`/`warp::`; bare `glass::` is the measured-default +`glass::nvidia::{block,warp,thread}::`; bare `glass::` is the measured-default block-scope face, while `glass::cgrps::` is the cooperative-groups twin. Plus the block-tridiagonal `glass::bdmv` / `glass::pcg`. **Read this before you change any -primitive or do a refactor.** Every GLASS function is a `__device__` helper that assumes it -runs inside **one CUDA block**, cooperating across `threadIdx`/`blockDim` (or a cooperative -group). That single-block, multi-thread, shared-data model is the source of essentially every -recurring bug below — they are races, thread-count assumptions, and uninitialized-scratch -reads, not algebra mistakes. Tone of this doc is a runbook: do X, check Y. +primitive or do a refactor.** Every GLASS function is a `__device__` helper, +but its participating scope is part of its namespace contract: block and bare +forms cooperate within one CUDA block, warp forms within one full warp, and +thread forms are independent per caller thread. Most recurring block-path bugs +below are races, thread-count assumptions, and uninitialized-scratch reads, not +algebra mistakes. Tone of this doc is a runbook: do X, check Y. Source map you will reference constantly: - Pure-SIMT surface: `glass.cuh` → `src/base/L1/*.cuh`, `src/base/L2/*.cuh`, `src/base/L3/*.cuh`. - Cooperative-groups surface: `glass-cgrps.cuh`. -- Vendor backends: `glass-nvidia.cuh` → `src/nvidia/{l1,l2,l3,l3_simt,lapack,query_simt,tuning_table,types}.cuh`. +- Vendor backends: `glass-nvidia.cuh` → + `src/nvidia/{l1,l1_warp,l2,l3,l3_simt,lapack,lapack_thread,query,query_simt,tuning_table,types}.cuh`. - Warp-scoped variants: inline in the base L1/L2/L3 headers (`src/base/L1/{reduce,dot,axpy,copy,scal,iamax}.cuh`, `src/base/L2/gemv.cuh`, `src/base/L3/{gemm,potrf,trsv,trsm,posv}.cuh`), under `namespace warp`. - Block-tridiagonal: `glass::bdmv` (`src/base/banded/bdmv.cuh`), `glass::pcg` + `glass::pcg_scratch_bytes` (`src/base/pcg/solve.cuh`). - Host smem helper: `glass_gemm_dispatch_smem` in `glass.cuh`. @@ -196,7 +198,7 @@ Functions that take `extern __shared__` scratch (or an explicit scratch pointer) - **`reduce_fast` / `dot` / `nrm2`:** need `ceil(blockDim/32)*sizeof(T)` bytes of `s_scratch` (one slot per warp). Under-sizing this overflows when `blockDim > 32*available`. - **`glass::nvidia::` (CUB) L1:** scratch is `sizeof(cub::BlockReduce::TempStorage)`; - query it with `glass::nvidia::reduce_smem_size()`. For the cuBLASDx/cuSOLVERDx + query it with `glass::nvidia::block::reduce_smem_size()`. For the cuBLASDx/cuSOLVERDx paths, query with `gemm_smem_size()` / `posv_smem_size<...>()` etc. and pass the EXACT value to the launch — too small = OOB, and (for the default form) a wrong thread count deadlocks. Always query, never hard-code a guessed byte count. @@ -375,7 +377,7 @@ NOT. Rules: literally `#include`s `src/base/L1/*.cuh` etc. *inside* `namespace glass { ... }`, and the other umbrellas do likewise into their namespaces. So editing `src/base/L3/gemm.cuh` changes `glass::gemm` AND `glass::cgrps::gemm` AND the inline `glass::warp::gemm` AND the SIMT fallback - that `glass::nvidia::gemm` auto-dispatches to (and `glass::pcg`, which composes `glass::bdmv` + + that `glass::nvidia::block::gemm` auto-dispatches to (and `glass::pcg`, which composes `glass::bdmv` + the base dot/axpy). After touching a base impl, run the FULL suite (`test_l1` + `test_l2` + `test_l3` + banded/pcg + the nvidia dispatch/trailing-sync tests), not just the namespace you were thinking about. Validate that all the surfaces sharing that base impl still produce identical numbers. @@ -453,12 +455,13 @@ NOT. Rules: - **A `*_reduced` op is a measured LOSS on sm_120 — don't assume parallelizing the contraction helps.** The serial one-thread-per-output loop over shared memory is very hard to beat; the warp-shuffle path is 10–100× slower except in a tiny corner (`n_out <= blockDim/32` AND `K >= 32`). ALWAYS bench before claiming a speedup - (`bench/RESULTS.md`, reduced section); the picker `glass::suggested_use_reduced<>()` recommends serial almost always. -- **Regenerating the dispatch defaults: one tool, one margin.** The three shipped tables — the warp/block/nvidia + (`bench/RESULTS.md`, reduced section); the public advisor stays two-axis and + reduced operations remain explicit opt-ins. +- **Regenerating the dispatch defaults: one tool, one margin.** The shipped tables — the native thread/warp/block plus NVIDIA block/thread ladder (`glass-defaults.cuh`, per-arch `ideal_sm*` tables + SM dispatch — tune.py replaces only the measured arch's marker block), the per-(M,N,K) cuBLASDx-vs-SIMT table (`src/nvidia/tuning_table.cuh`), - and the `suggested_use_reduced<>` predicate — are all regenerated by `bench/tune.py` (legs `ladder`/`shapes`/ + and the serial-vs-reduced characterization — are all driven by `bench/tune.py` (legs `ladder`/`shapes`/ `reduced`/`figures`). Every verdict routes through the single tie rule in `bench/tune_pick.py::pick`: a - dependency impl (nvidia/cublasdx/reduced) wins ONLY if it beats the simplest no-dependency impl by more than the + dependency impl (nvidia/nvidia_thread/cublasdx/reduced) wins ONLY if it beats the simplest no-dependency impl by more than the margin (default 5%), else the launchable-everywhere path stays — this is what stops sub-noise jitter (e.g. a cuBLASDx pick 1% faster than warp) from churning the tables. Don't hand-edit these tables or re-derive the margin per-tool; run `tune.py` on a **quiet GPU** (perf timing must be isolated) and `--dry-run` to diff first. @@ -485,7 +488,7 @@ NOT. Rules: | Two-step `congruence`/`bilinear`/`riccati` differs warp-vs-block by ~1 ULP | Benign FMA-context drift; compare cross-surface with `allclose` (§7) | | `posv(A,b)` suddenly ambiguous after adding a flag | Flagged both posv overloads — flag only multi-RHS (§7) | | `std::size_t` undefined / `glass::std` error in a base header | `std` nested by an in-namespace include — return `uint32_t` (§7) | -| `*_reduced` op far slower than serial | Expected on sm_120 — use `suggested_use_reduced<>()`, prefer serial (§7) | +| `*_reduced` op far slower than serial | Expected on sm_120 — prefer the standard op unless a local sweep supports the explicit reduced form (§7) | ## Bare-face body dispatch (2026-07-30, Phase 2) diff --git a/docs/source/_static/mega_sweep_ladder_f32.png b/docs/source/_static/mega_sweep_ladder_f32.png index 2180011..0638c54 100644 Binary files a/docs/source/_static/mega_sweep_ladder_f32.png and b/docs/source/_static/mega_sweep_ladder_f32.png differ diff --git a/docs/source/_static/mega_sweep_ladder_f32_n1024.png b/docs/source/_static/mega_sweep_ladder_f32_n1024.png index 5acdbdd..e144626 100644 Binary files a/docs/source/_static/mega_sweep_ladder_f32_n1024.png and b/docs/source/_static/mega_sweep_ladder_f32_n1024.png differ diff --git a/docs/source/_static/mega_sweep_ladder_f32_n64.png b/docs/source/_static/mega_sweep_ladder_f32_n64.png index 227a962..4638b88 100644 Binary files a/docs/source/_static/mega_sweep_ladder_f32_n64.png and b/docs/source/_static/mega_sweep_ladder_f32_n64.png differ diff --git a/docs/source/_static/mega_sweep_ladder_f32_n8192.png b/docs/source/_static/mega_sweep_ladder_f32_n8192.png index 2180011..0638c54 100644 Binary files a/docs/source/_static/mega_sweep_ladder_f32_n8192.png and b/docs/source/_static/mega_sweep_ladder_f32_n8192.png differ diff --git a/docs/source/_static/mega_sweep_ladder_f64.png b/docs/source/_static/mega_sweep_ladder_f64.png index 8e4fb3b..2745a3c 100644 Binary files a/docs/source/_static/mega_sweep_ladder_f64.png and b/docs/source/_static/mega_sweep_ladder_f64.png differ diff --git a/docs/source/_static/mega_sweep_ladder_f64_n1024.png b/docs/source/_static/mega_sweep_ladder_f64_n1024.png index 0220cba..da7e77d 100644 Binary files a/docs/source/_static/mega_sweep_ladder_f64_n1024.png and b/docs/source/_static/mega_sweep_ladder_f64_n1024.png differ diff --git a/docs/source/_static/mega_sweep_ladder_f64_n64.png b/docs/source/_static/mega_sweep_ladder_f64_n64.png index 6132f09..6c38c60 100644 Binary files a/docs/source/_static/mega_sweep_ladder_f64_n64.png and b/docs/source/_static/mega_sweep_ladder_f64_n64.png differ diff --git a/docs/source/_static/mega_sweep_ladder_f64_n8192.png b/docs/source/_static/mega_sweep_ladder_f64_n8192.png index 8e4fb3b..2745a3c 100644 Binary files a/docs/source/_static/mega_sweep_ladder_f64_n8192.png and b/docs/source/_static/mega_sweep_ladder_f64_n8192.png differ diff --git a/docs/source/_static/sweep_winners.txt b/docs/source/_static/sweep_winners.txt index a90dd51..fac9236 100644 --- a/docs/source/_static/sweep_winners.txt +++ b/docs/source/_static/sweep_winners.txt @@ -1,53 +1,17 @@ -NPROB=64 f32 winner by op x N: -op 4 6 8 12 16 24 32 48 64 96 128 -dot warp block warp warp thread warp block warp warp warp nvidia -gemv warp block block warp warp nvidia nvidia nvidia nvidia nvidia nvidia -gemm warp block block warp nvidia nvidia nvidia nvidia nvidia block block -chol warp nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia -trsv thread thread nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia -posv thread nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia - -NPROB=64 f64 winner by op x N: -op 4 6 8 12 16 24 32 48 64 96 128 -dot warp warp warp warp warp warp warp warp warp warp block -gemv warp warp warp block block block block block block block block -gemm warp block nvidia nvidia nvidia block block nvidia block block block -chol nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia block block -trsv nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia block block -posv nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia block block - -NPROB=1024 f32 winner by op x N: -op 4 6 8 12 16 24 32 48 64 96 128 -dot warp warp warp warp warp warp warp warp warp warp warp -gemv warp warp warp warp warp warp warp block block block block -gemm warp warp warp block warp nvidia nvidia nvidia nvidia block block -chol thread thread nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia -trsv thread thread thread nvidia nvidia nvidia nvidia nvidia nvidia block block -posv thread thread nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia nvidia - -NPROB=1024 f64 winner by op x N: -op 4 6 8 12 16 24 32 48 64 96 128 -dot thread thread thread warp warp warp warp warp warp warp warp -gemv warp warp warp warp warp warp warp block block block block -gemm warp warp block block block block block block block block block -chol thread thread block block block block nvidia nvidia nvidia block block -trsv thread thread nvidia nvidia nvidia nvidia nvidia nvidia block block block -posv thread thread thread nvidia nvidia nvidia nvidia nvidia nvidia block block - NPROB=8192 f32 winner by op x N: -op 4 6 8 12 16 24 32 48 64 96 128 -dot thread thread thread thread warp warp warp warp warp warp warp -gemv thread thread warp warp warp warp warp block warp warp warp -gemm warp warp warp block warp block nvidia block block block block -chol thread thread warp warp nvidia nvidia nvidia nvidia nvidia nvidia nvidia -trsv thread thread thread thread thread nvidia nvidia warp warp warp warp -posv thread thread thread thread nvidia nvidia nvidia nvidia nvidia nvidia nvidia +op 4 6 8 12 16 24 32 48 64 96 128 +dot thread thread thread thread warp thread warp warp warp warp warp +gemv thread thread warp warp warp warp warp block warp warp warp +gemm warp warp warp warp warp block nvidia block block block block +potrf thread nvidia_thread nvidia_thread warp warp warp nvidia nvidia nvidia nvidia nvidia +trsv thread thread thread thread thread nvidia_thread nvidia warp warp warp warp +posv thread thread nvidia_thread thread nvidia nvidia nvidia nvidia nvidia nvidia nvidia NPROB=8192 f64 winner by op x N: -op 4 6 8 12 16 24 32 48 64 96 128 -dot thread thread thread thread thread thread thread warp warp warp warp -gemv thread thread warp warp warp warp warp warp warp block block -gemm warp warp block block nvidia block block block block block block -chol thread thread thread thread thread thread nvidia nvidia nvidia block block -trsv thread thread thread thread thread nvidia nvidia nvidia block block block -posv thread thread thread thread thread thread nvidia nvidia nvidia block block +op 4 6 8 12 16 24 32 48 64 96 128 +dot thread thread thread thread thread thread thread warp warp warp warp +gemv thread thread warp warp warp warp warp warp warp warp warp +gemm warp warp warp block block block block block block block block +potrf nvidia_thread nvidia_thread nvidia_thread thread thread thread block block block block block +trsv nvidia_thread nvidia_thread nvidia_thread nvidia_thread nvidia_thread nvidia_thread nvidia_thread nvidia warp warp warp +posv nvidia_thread nvidia_thread nvidia_thread thread thread thread nvidia block block block block diff --git a/docs/source/api_reference/defaults.rst b/docs/source/api_reference/defaults.rst index a4f46e0..51c3f26 100644 --- a/docs/source/api_reference/defaults.rst +++ b/docs/source/api_reference/defaults.rst @@ -1,101 +1,99 @@ -Backend Picker (``glass-defaults.cuh``) -======================================= - -Queryable backend-selection defaults — the measured thread / warp / block / nvidia -ladder (``bench/RESULTS.md``) exposed as ``constexpr`` helpers, so callers -and GRiD-style codegen pick a backend + launch config instead of hand-copying a table. - -The pick **cannot** be a device function: the tiers need different -``<<>>`` launches, so the decision happens host-side / at codegen time. See -:doc:`../user_guide/concepts/tuning` for the underlying numbers. - -Distinct from this launch-level advisor, the tiny ``glass-dispatch.cuh`` -header (included by both ``glass.cuh`` and this one; shared ``glass::op`` -enum) carries ``glass::dispatch_body()`` — the measured **in-block body** -table behind the bare ``glass::op`` face, applied automatically by the -wrappers in ``src/base/dispatch.cuh`` under a *fixed* launch. See -:doc:`../user_guide/concepts/namespaces`. +Execution Plans (``glass-defaults.cuh``) +======================================== -.. note:: +``glass::recommend()`` turns the measured implementation ladder into one +``constexpr`` value. It returns: - ``backend::thread`` is **measured and shipped for sm_120** (2026-07-18 quiet-GPU - sweep): the thread tier takes the low-DOF corner of every op except ``gemm`` — - up to 7.5× on ``posv`` f64 at N≤6 (the docs sweep-results page has the - full verdicts). A ``thread`` pick means a thread-per-problem launch: - ``<<>>`` with ``suggested_threads_per_block<>()``. The - ``ideal_generic`` fallback for unswept arches remains warp/block/nvidia-only. +* the measured implementation family and execution scope for this shape; and +* a ready-to-use, legal launch packing. -Include order -------------- +The packing fields are defaults, not a claim that every caller's optimal block +size was measured. Applications may retune them within the explicit operation's +documented launch contract. -Include ``glass-defaults.cuh`` **after** ``glass.cuh``, and after ``glass-nvidia.cuh`` if you -want the ``nvidia`` tier to be eligible (it reads ``GLASS_HAVE_CUBLASDX`` / -``GLASS_HAVE_CUSOLVERDX``). With only ``glass.cuh`` linked, the ``nvidia`` tier collapses to its -warp/block runner-up, so a no-MathDx caller always gets a backend it can launch. +The decision is host-side or code-generation-time. A thread, warp, block, and +NVIDIA block implementation require different CUDA launches; ``recommend()`` +does not dispatch a device call for you. -Helpers -------- +The contract +------------ .. code-block:: cuda - enum class glass::op { dot, gemv, gemm, chol, trsv, posv }; - enum class glass::backend { warp, block, nvidia, thread }; // thread appended: pre-existing ordinals unchanged - - // Which backend for (op, N, T) on this SM? (nvidia only when the vendor lib is linked) - template - constexpr backend glass::suggested_backend(); - - // For the `block` backend: factor/solve want 32; gemm grows with N; dot/gemv 64–128. - template - constexpr uint32_t glass::suggested_block_threads(); - - // For the `warp` backend: dot packs 8; others 2 warps/block. - template - constexpr uint32_t glass::suggested_warps_per_block(); - - // For the `thread` backend: launch <<>>, one problem per thread. - // Seed heuristic (shrinks as N*N registers/thread grow), NOT measured by the ladder leg. - template - constexpr uint32_t glass::suggested_threads_per_block(); - -Example -------- + enum class glass::family { native, nvidia }; + enum class glass::scope { thread, warp, block }; + enum class glass::dependency_set { native_only, mathdx }; + struct glass::execution_plan { + family implementation; + scope execution_scope; + uint32_t block_threads; + uint32_t problems_per_block; + uint32_t shared_bytes; + }; + + template + constexpr glass::execution_plan glass::recommend( + glass::dependency_set dependencies = glass::dependency_set::native_only, + uint32_t sm = GLASS_TARGET_SM); + +Shape arguments follow the operation's mathematical order: + +* Square ladder operations: ``recommend()`` +* Rectangular GEMV: ``recommend()`` +* Rectangular GEMM: ``recommend()`` + +``native_only`` is deliberately the default. Pass ``dependency_set::mathdx`` +to admit measured ``glass::nvidia::block`` and ``glass::nvidia::thread`` +candidates. Each measured architecture carries a paired native-only table from +the same capture, rather than approximating vendor-winning cells with a size +heuristic. The result is independent of header include order. + +Using a plan +------------ .. code-block:: cuda - #include "glass.cuh" - #include "glass-defaults.cuh" // (after glass-nvidia.cuh too, to allow the nvidia tier) - - constexpr auto be = glass::suggested_backend(); - if constexpr (be == glass::backend::nvidia) { /* cuSOLVERDx launch */ } - else if constexpr (be == glass::backend::warp) { /* <<>> */ } - else if constexpr (be == glass::backend::thread) { - constexpr int TPB = glass::suggested_threads_per_block(); - /* <<>> */ - } else /* block */ { - constexpr int TB = glass::suggested_block_threads(); - /* <<>> */ + constexpr auto plan = glass::recommend( + glass::dependency_set::mathdx); + + if constexpr (plan.implementation == glass::family::nvidia && + plan.execution_scope == glass::scope::thread) { + // one problem per thread + // glass::nvidia::thread::potrf(...) + } else if constexpr (plan.implementation == glass::family::nvidia) { + // one problem per block; query the explicit wrapper's exact requirements + // glass::nvidia::block::potrf(...) + } else if constexpr (plan.execution_scope == glass::scope::warp) { + // one problem per warp + // glass::warp::potrf(...) + } else if constexpr (plan.execution_scope == glass::scope::thread) { + // one problem per thread + // glass::thread::potrf(...) + } else { + // one problem per block + // glass::block::potrf(...) } -A runnable version is ``examples/08_backend_picker.cu``. +For native plans, ``block_threads`` and ``problems_per_block`` are complete +launch guidance. NVIDIA block descriptors own shape-specific thread and shared +memory requirements; those fields use +``execution_plan::dynamic_requirement`` when the explicit backend query must be +consulted. -Per-host override ------------------ +``GLASS_TARGET_SM`` +------------------- -The shipped tables are per-arch: each swept SM has its own ``constexpr`` ladder -(``ideal_sm120`` today, measured on an RTX 5090) behind an SM dispatch, and running -``bench/tune.py --sm auto`` on a new GPU (e.g. a Jetson Orin, sm_87) adds that arch's -table + dispatch case in-tree without touching the others; unmeasured SMs fall back to -a coarse heuristic. Alternatively, for a host-local override that leaves the shipped -tables alone, regenerate a table from a sweep run and point -``GLASS_DEFAULTS_TABLE_LOCAL`` at it: +``GLASS_TARGET_SM`` selects the measured architecture table and the MathDx +descriptor architecture from one build setting. It defaults to the shipped +sm_120 seed. Define it explicitly when targeting another GPU, for example +``-DGLASS_TARGET_SM=870``. The historical ``SMS`` macro remains an input alias +for existing build systems. -.. code-block:: bash +The shipped tables currently cover sm_120 and sm_87. Unmeasured architectures +use conservative generic choices until ``bench/tune.py`` adds a measured table. +``examples/08_backend_picker.cu`` is a complete native-only launcher. - cd bench && ./run_mega_sweep.sh sm_XX - python3 autotune.py --emit-defaults mega_sweep_.txt # -> bench/tuning/_defaults.cuh - nvcc ... -DGLASS_DEFAULTS_TABLE_LOCAL='"bench/tuning/_defaults.cuh"' ... - -``bench/explore_sweep.ipynb`` visualizes a sweep (ladder plot + winner table); -:doc:`../user_guide/tutorials/sweep_results` shows the rendered ladder + winner -table the defaults are seeded from. +This launch-level plan is separate from ``glass::dispatch_body()``. The latter +selects a measured thread-0, warp-0, or full-block implementation *inside* the +fixed block-scope contract of bare ``glass::op`` calls. See +:doc:`../user_guide/concepts/namespaces`. diff --git a/docs/source/api_reference/index.rst b/docs/source/api_reference/index.rst index 42e9e2c..921b7ab 100644 --- a/docs/source/api_reference/index.rst +++ b/docs/source/api_reference/index.rst @@ -14,7 +14,8 @@ The reference is organized by BLAS level and by backend: * **NVIDIA backend** — the ``glass::nvidia::block::`` CUB / cuBLASDx / cuSOLVERDx paths and their host-side query/size helpers, plus the ``glass::nvidia::warp::`` CUB ``WarpReduce`` reductions (one full 32-lane - warp per problem). + warp per problem) and ``glass::nvidia::thread::`` cuSOLVERDx 0.4+ LAPACK + wrappers (one packed problem per CUDA thread). * **Warp-scoped** — the ``glass::warp::`` single-warp SIMT variants for warp-per-problem kernels. * **Thread-scoped** — the ``glass::thread::`` sequential variants for @@ -25,9 +26,9 @@ The reference is organized by BLAS level and by backend: * **Robotics operators** — the spatial 6-D, Lie/quaternion, projection/cone, geometry-distance, and sampling-reduction families (all three SIMT tiers; see :doc:`../user_guide/concepts/robotics_conventions`). -* **Backend picker** — ``glass-defaults.cuh`` ``constexpr`` helpers - (``suggested_backend`` / ``suggested_block_threads`` / ``suggested_warps_per_block`` / ``suggested_threads_per_block``) - that pick a backend + launch config from the measured ladder. +* **Execution plans** — ``glass-defaults.cuh`` and its ``constexpr`` + ``glass::recommend()`` query, which returns family, scope, and launch + packing from the measured ladder. .. note:: diff --git a/docs/source/api_reference/nvidia.rst b/docs/source/api_reference/nvidia.rst index 31b9ebc..98c07a5 100644 --- a/docs/source/api_reference/nvidia.rst +++ b/docs/source/api_reference/nvidia.rst @@ -1,16 +1,21 @@ -NVIDIA Backend (``glass::nvidia::``) -==================================== +NVIDIA Backends (``glass::nvidia::*``) +====================================== Vendor-accelerated paths built on CUB (reductions), cuBLASDx (GEMM/GEMV), and -cuSOLVERDx (LAPACK). The block-scope ops live in ``glass::nvidia::block::`` -(the contract tier; bare ``glass::nvidia::`` re-exports them as the -measured-default face). The entry points auto-dispatch **at compile time** +cuSOLVERDx (LAPACK). Block-scope ops live in ``glass::nvidia::block::``. +Those entry points auto-dispatch **at compile time** between a pure-SIMT implementation and the vendor backend based on a size heuristic / tuning table (a ``constexpr`` decision — no runtime branching); see :doc:`../user_guide/concepts/backend_dispatch`. The L2/L3/LAPACK paths require NVIDIA MathDx (``MATHDX_ROOT``) — see :doc:`../user_guide/getting_started/installation`. +cuSOLVERDx 0.4+ also supplies explicit smem-less LAPACK wrappers under +``glass::nvidia::thread::``. Each calling CUDA thread owns one packed problem. +Warp-scope CUB reductions live in ``glass::nvidia::warp::``. There is no bare +operation re-export: the scope is always explicit because it determines launch +geometry. + Each call has a companion **host-side** query helper (``*_scratch_bytes``, ``*_threads``, ``*_block_threads_valid``) used to size the launch. @@ -49,6 +54,12 @@ LAPACK (cuSOLVERDx) .. doxygenfile:: src/nvidia/lapack.cuh :no-link: +LAPACK thread execution (cuSOLVERDx 0.4+) +------------------------------------------ + +.. doxygenfile:: src/nvidia/lapack_thread.cuh + :no-link: + Dispatch & query helpers ------------------------ diff --git a/docs/source/api_reference/thread.rst b/docs/source/api_reference/thread.rst index 36d2162..2e167d0 100644 --- a/docs/source/api_reference/thread.rst +++ b/docs/source/api_reference/thread.rst @@ -6,14 +6,15 @@ a single thread owns the whole operation — **no barriers, no shuffles, no** ``threadIdx`` **read** — so 32 independent problems pack into one warp. They target the *low-DOF corner* (robot DOF ≲ 7) where even a warp per problem leaves most lanes idle: a thread-per-problem launch -(``<<>>``, see ``glass::suggested_threads_per_block<>()``) +(``<<>>``, with packing from ``glass::recommend()``) keeps every lane busy on its own problem. Contract: **compile-time sizes only.** The tier's value is operands that nvcc keeps register-resident, which requires fully-unrolled, compile-time-resolvable -indexing — the measured ceiling is ``N ≤ 7`` (both dtypes; larger ``N`` still -computes correctly but demotes the operands to local memory, forfeiting the -tier's premise). Operands may be thread-local register arrays; nothing is read +indexing. Around ``N ≤ 7`` is a useful register-residency guideline, not an API +or performance ceiling: larger ``N`` still computes correctly, may spill to +local memory, and remains in the tuning ladder while it is feasible. Operands +may be thread-local register arrays; nothing is read from ``threadIdx``, so the functions are launch-shape-agnostic. Every op delegates to the same ``*_impl`` body its block-scoped sibling uses, @@ -46,8 +47,8 @@ tier exists to avoid. ``vec_tensor_vec``, ``congruence_sym`` / ``bilinear`` / ``congruence_accum``, ``riccati_gain``. See :doc:`l3`. -The dispatch ladder (:doc:`defaults`) contends the tier alongside warp / block / -nvidia, and the sm_120 tables ship thread verdicts (2026-07-18 sweep): thread -takes the low-DOF corner of every op except ``gemm`` — up to 7.5× on ``posv`` -f64 at N≤6 (docs sweep-results page + ``bench/RESULTS.md``). Run ``bench/tune.py --sm auto`` -to contend it on your own GPU. +The dispatch ladder (:doc:`defaults`) contends the tier alongside native warp / +block and NVIDIA block / thread implementations. The dated measurements and +generated verdicts are on the :doc:`sweep-results page +<../user_guide/tutorials/sweep_results>` and in ``bench/RESULTS.md``. Run +``bench/tune.py --sm auto`` to contend it on your own GPU. diff --git a/docs/source/index.rst b/docs/source/index.rst index 4c34b6a..0f17008 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -21,8 +21,9 @@ load-bearing layout choices. Interfaces ---------- -GLASS exposes four primary interfaces. Choose by execution scope and dependency -budget. The interfaces intentionally overlap, but do not all expose every +GLASS separates **execution scope** (thread, warp, or block) from +**implementation family** (dependency-free GLASS code or optional NVIDIA +libraries). The spellings intentionally overlap, but do not all expose every operation. .. grid:: 2 @@ -50,20 +51,33 @@ operation. :link-type: doc One problem per **thread**, 32 packed per warp. This is a compile-time, - branch-free subset intended for register-resident sizes up to ``N≤7``. + branch-free subset. It is usually register-resident around ``N≤7``; + larger measured sizes remain correct and can still win despite spills. .. grid-item-card:: Nvidia — ``glass::nvidia::block::`` :link: user_guide/concepts/backend_dispatch :link-type: doc - CUB / cuBLASDx / cuSOLVERDx, auto-dispatched against SIMT by size at - compile time — plus ``glass::nvidia::warp::`` CUB ``WarpReduce`` L1 - reductions (one full 32-lane warp per problem). Choose this when a - vendor **tensor-core** kernel wins at your size (needs NVIDIA MathDx). + CUB / cuBLASDx / cuSOLVERDx at block scope. Choose this when the measured + vendor implementation wins at your size (needs NVIDIA MathDx). + + .. grid-item-card:: Nvidia warp — ``glass::nvidia::warp::`` + :link: api_reference/nvidia + :link-type: doc + + CUB ``WarpReduce`` L1 reductions, one full 32-lane warp per problem and + explicit per-warp scratch. + + .. grid-item-card:: Nvidia thread — ``glass::nvidia::thread::`` + :link: api_reference/nvidia + :link-type: doc + + cuSOLVERDx 0.4+ LAPACK, one independent packed problem per CUDA thread; + no dynamic shared scratch or block-wide synchronization. .. note:: - ``glass::cgrps::`` is a convenience cooperative-groups *alias* of the **Block** + ``glass::cgrps::`` is a cooperative-groups *adapter* for the **Block** interface — identical numerics (the same SIMT loop, indexed via a ``thread_group`` handle), for callers already in a cooperative-groups context or tiling arbitrary sub-block groups. It is **not** a separately-tuned backend. @@ -71,7 +85,7 @@ operation. .. note:: - **Bare** ``glass::op`` (and bare ``glass::nvidia::op``) is the + **Bare** ``glass::op`` is the **measured-default face**: the same block-scope calling contract, with the implementation body chosen per (op, size, dtype) by ``glass::dispatch_body()`` (``glass-dispatch.cuh``, regenerated by the @@ -79,15 +93,17 @@ operation. decision **inside the device function** — resolved per call site at compile time, with no host-side dispatcher and no runtime branch. Cells with a robust measured win route to a warp- or thread-body inside the block; every other name is the - *same entity* as ``glass::block::``, and all pre-restructure spellings - compile unchanged. Determinism-sensitive callers pin ``glass::block::`` + *same entity* as ``glass::block::``. Determinism-sensitive callers pin ``glass::block::`` explicitly; see :doc:`user_guide/concepts/namespaces`. + NVIDIA calls always name ``block``, ``warp``, or ``thread``; there is no + bare ``glass::nvidia::op`` re-export. + Measured defaults ----------------- -``glass::suggested_backend()`` exposes architecture-specific measured -defaults for operations included in the tuning ladder. Measurements are not a +``glass::recommend()`` exposes architecture-specific measured +execution plans for operations included in the tuning ladder. Measurements are not a promise that interfaces have identical coverage or reduction order. See :doc:`user_guide/concepts/tuning` for the selection policy and :doc:`user_guide/tutorials/sweep_results` for dated, configuration-specific @@ -132,9 +148,9 @@ and :doc:`user_guide/tutorials/examples` for a worked program per concept. Measured performance -------------------- -The measured warp / block / nvidia ladder on an RTX 5090 (sm_120) — each op's -fastest interface across problem size, in ns/problem (the data behind -``glass::suggested_backend<>``), shown here in the ``NPROB=8192`` throughput +The measured native and NVIDIA thread / warp / block ladder on an RTX 5090 +(sm_120) — each op's fastest interface across problem size, in ns/problem (the data behind +``glass::recommend<>``), shown here in the ``NPROB=8192`` throughput regime: .. image:: _static/mega_sweep_ladder_f32.png diff --git a/docs/source/user_guide/concepts/backend_dispatch.rst b/docs/source/user_guide/concepts/backend_dispatch.rst index 6e9f30a..52c53c9 100644 --- a/docs/source/user_guide/concepts/backend_dispatch.rst +++ b/docs/source/user_guide/concepts/backend_dispatch.rst @@ -1,14 +1,15 @@ Backend Dispatch ================ -The ``glass::nvidia::gemm`` / ``gemv`` / ``row_strided_*`` / ``gemm_batched_1d`` +The ``glass::nvidia::block::gemm`` / ``gemv`` / ``row_strided_*`` / +``gemm_batched_1d`` primary templates **auto-dispatch** at compile time: for shapes where pure-SIMT wins they fall through to ``::glass::*``; for shapes where the vendor library wins they route to cuBLASDx via the ``DEFINE_NVIDIA_*`` macros. -This means ``glass::nvidia::gemm(...)`` "just works" without any +This means ``glass::nvidia::block::gemm(...)`` "just works" without any DEFINE macro — small shapes route to SIMT automatically. Larger shapes such as -``glass::nvidia::gemm(...)`` still require a +``glass::nvidia::block::gemm(...)`` still require a ``DEFINE_NVIDIA_GEMM(32, 32, 32)`` in scope (placed inside ``namespace glass { namespace nvidia { namespace block {``), but produce a clean compile-time message when it is missing. @@ -16,12 +17,12 @@ clean compile-time message when it is missing. .. note:: This cuBLASDx-vs-SIMT decision is one of **three** distinct dispatch layers. - ``glass::suggested_backend<>`` (:doc:`tuning`) is a *host-side* ladder that - advises **launch-level packing** — which tier (thread / warp / block / - nvidia) to launch, i.e. the shape of ``<<>>``. Newest, and + ``glass::recommend<>`` (:doc:`tuning`) is a *host-side* ladder that + advises **launch-level packing** — which native or NVIDIA thread / warp / + block tier to launch, i.e. the shape of ``<<>>``. Newest, and different from both: ``glass::dispatch_body()`` (``glass-dispatch.cuh``) - picks the **in-block body** behind the bare ``glass::op`` / - ``glass::nvidia::op`` face, under a *fixed* block-scope calling contract — + picks the **in-block body** behind the bare ``glass::op`` face, under a + *fixed* block-scope calling contract — the launch does not change. The measured in-block body sweep (``bench/tune.py --legs body``, Phase 2, 2026-07-30) moved the winning cells to a warp- or thread-body executed inside the block — an attested, @@ -35,7 +36,7 @@ The dispatch flow .. code-block:: text - caller writes: glass::nvidia::gemm(...) + caller writes: glass::nvidia::block::gemm(...) │ ▼ should_use_cublasdx() @@ -95,14 +96,14 @@ drop one into a kernel for runtime diagnostics) report the chosen path: .. code-block:: cpp - glass::nvidia::print_dispatch(); - // → glass::nvidia::gemm: SIMT fallback + glass::nvidia::block::print_dispatch(); + // → glass::nvidia::block::gemm: SIMT fallback - glass::nvidia::print_dispatch(); - // → glass::nvidia::gemm: cuBLASDx (needs DEFINE_NVIDIA_GEMM*) + glass::nvidia::block::print_dispatch(); + // → glass::nvidia::block::gemm: cuBLASDx (needs DEFINE_NVIDIA_GEMM*) - glass::nvidia::print_dispatch_gemv(); - // → glass::nvidia::gemv: cuBLASDx (needs DEFINE_NVIDIA_GEMV*) + glass::nvidia::block::print_dispatch_gemv(); + // → glass::nvidia::block::gemv: cuBLASDx (needs DEFINE_NVIDIA_GEMV*) Overriding the dispatch ----------------------- @@ -116,7 +117,7 @@ Overriding the dispatch * - Force cuBLASDx for a shape the heuristic puts in SIMT - Add ``DEFINE_NVIDIA_GEMM(M,N,K)`` in your ``.cu`` file — the explicit specialization always overrides the primary template. * - Force SIMT for a shape the heuristic puts in cuBLASDx - - Call ``::glass::gemm(...)`` directly (skip the ``nvidia::`` path). + - Call ``::glass::block::gemm(...)`` directly (skip the NVIDIA path). * - Per-host tuning without editing source - Run ``python bench/autotune.py`` to generate ``bench/tuning/.cuh``, then compile with ``-DGLASS_TUNING_TABLE_LOCAL='"bench/tuning/.cuh"'``. * - Different SM in-tree (for a PR) diff --git a/docs/source/user_guide/concepts/batched_1d.rst b/docs/source/user_guide/concepts/batched_1d.rst index bbe5b23..d616269 100644 --- a/docs/source/user_guide/concepts/batched_1d.rst +++ b/docs/source/user_guide/concepts/batched_1d.rst @@ -2,7 +2,7 @@ Batched-1D GEMM APIs ==================== GLASS provides batched GEMM primitives that run **inside a single 1D thread -block**. They exist because the cuBLASDx-backed ``glass::nvidia::gemm_batched`` +block**. They exist because the cuBLASDx-backed ``glass::nvidia::block::gemm_batched`` requires a **2D launch** (``dim3(TC, BATCH)``) — it gives each batch element a ``threadIdx.y`` slot. Kernels that were launched 1D (``dim3(TC*BATCH, 1, 1)``, because every other block-level helper uses ``threadIdx.x``) cannot use it @@ -39,7 +39,7 @@ The two APIs __global__ void k(float* const* A, float* const* B, float* const* C) { // No DEFINE macro needed — fully templated on T. - glass::nvidia::gemm_batched_1d( + glass::nvidia::block::gemm_batched_1d( 1.f, A, B, 0.f, C); } k<<<1, dim3(32 * 8, 1, 1)>>>(dA_ptrs, dB_ptrs, dC_ptrs); // no smem @@ -58,7 +58,7 @@ arrays to set up: __global__ void k_shared(float* A_shared, float* B_base, float* C_base) { // tightly packed: B_STRIDE = N*K, C_STRIDE = M*K (the defaults) - glass::nvidia::gemm_strided_batched_1d( + glass::nvidia::block::gemm_strided_batched_1d( 1.f, A_shared, B_base, 0.f, C_base); } @@ -97,7 +97,7 @@ the ``TRAILING_SYNC`` template parameter (see :doc:`trailing_sync`). .. note:: For **large** batched shapes (M,N,K ≥ 16) where cuBLASDx would win, use the - 2D-launch ``glass::nvidia::gemm_batched<...,BATCH,TC>`` instead and pay the + 2D-launch ``glass::nvidia::block::gemm_batched<...,BATCH,TC>`` instead and pay the ``dim3(TC, BATCH)`` launch geometry. The batched-1D path deliberately does not attempt to wrap cuBLASDx. diff --git a/docs/source/user_guide/concepts/contraction_parallel.rst b/docs/source/user_guide/concepts/contraction_parallel.rst index 322ec01..e046a6a 100644 --- a/docs/source/user_guide/concepts/contraction_parallel.rst +++ b/docs/source/user_guide/concepts/contraction_parallel.rst @@ -27,8 +27,8 @@ All ship in the three SIMT surfaces (``glass::`` block, ``glass::warp::``, quiet RTX 5090 (sm_120) sweep, reduced cleared the ±5% decision margin in 0/48 f32 cells and 2/48 f64 cells. Both f64 wins were the same 4×4×64 shape at 128/256 threads (full table: ``bench/RESULTS.md``). The - dtype-independent ``glass::suggested_use_reduced`` picker therefore - declines it everywhere rather than regressing f32. + measured ``glass::recommend`` plan therefore keeps the standard algorithm + everywhere rather than regressing f32. **Prefer the plain ops** (``gemm`` / ``gemv`` / ``syrk``) for throughput; reach for this family only for the fused forms (``tensor_vec_contract``, ``vec_tensor_vec``, ``congruence_sym``, ``bilinear``) that the serial surface @@ -67,17 +67,15 @@ idle. The two wins are f64 4×4×64 at 128/256 threads (1.41× and 1.97×). That single dtype-specific shape is worth a future targeted sweep, but it does not justify a general or dtype-blind default. -``glass::suggested_use_reduced`` encodes that measurement — it returns -``false`` unconditionally on sm_120. Its ```` -signature has no scalar-type parameter, so it cannot safely encode the observed -f64-only corner: +The public advisor stays focused on implementation family and execution scope; +it does not add a third axis for a path that is never broadly recommended: .. code-block:: cuda - if constexpr (glass::suggested_use_reduced()) - glass::gemm_reduced(1.f, A, B, 0.f, C); - else - glass::gemm(1.f, A, B, 0.f, C); + glass::gemm(1.f, A, B, 0.f, C); + +The explicit ``gemm_reduced`` spelling remains available when a caller has +its own shape-specific evidence. .. note:: diff --git a/docs/source/user_guide/concepts/namespaces.rst b/docs/source/user_guide/concepts/namespaces.rst index 031e5fa..6d55272 100644 --- a/docs/source/user_guide/concepts/namespaces.rst +++ b/docs/source/user_guide/concepts/namespaces.rst @@ -8,24 +8,23 @@ Axis A — scope / backend (the namespace) ---------------------------------------- The namespace says **who cooperates and how**, never *what* the operation is. -There are **four primary interfaces** — Block (``glass::block::``), Warp -(``glass::warp::``), Thread (``glass::thread::``), and Nvidia -(``glass::nvidia::block::`` / ``glass::nvidia::warp::``) — plus -``glass::cgrps::``, a convenience alias of the Block interface, and the -**bare** ``glass::`` face described below. The ladder runs most→least problem -packing: thread (1 problem/thread, 32 per warp) → warp (1/warp) → block -(1/block) → nvidia (1/block, vendor): +There are three execution scopes (block, warp, thread) and two implementation +families (dependency-free GLASS and optional NVIDIA, where supported), plus +``glass::cgrps::``, a cooperative-groups adapter for the Block interface, and the +**bare** ``glass::`` face described below. Scope determines placement; the +family determines the implementation and dependency contract: ================================ ====== ================================================= Namespace Scope What it is ================================ ====== ================================================= ``glass::block::`` block **Block** — explicit hand-rolled pure-SIMT implementation (``threadIdx`` / ``blockDim``). CONTRACT tier: bit-exact, thread-count invariant for deterministic-order ops (the ``_fast`` shuffle reductions and ``pcg`` are oracle-close with documented ``blockDim``-dependent summation order), never re-dispatched. ``glass::warp::`` warp **Warp** — single-warp SIMT (``__shfl_*_sync``), warp-per-problem. (Namespace alias of ``block::warp`` — the warp mirrors live inline in the base headers.) -``glass::thread::`` thread **Thread** — sequential, thread-per-problem, for low-DOF packing (compile-time sizes; register-resident up to ``N≤7``). No barriers, no shuffles, no ``threadIdx`` read. (Alias of ``block::thread``.) +``glass::thread::`` thread **Thread** — sequential, thread-per-problem, for low-DOF packing (compile-time sizes; usually register-resident around ``N≤7``, correct and measured beyond it). No barriers, no shuffles, no ``threadIdx`` read. (Alias of ``block::thread``.) ``glass::nvidia::block::`` block **Nvidia** — CUB / cuBLASDx / cuSOLVERDx, auto-dispatched by size at compile time. ``glass::nvidia::warp::`` warp **Nvidia-warp** — CUB ``WarpReduce`` L1 reductions (``reduce`` / ``dot`` / ``nrm2``), one FULL 32-lane warp per problem; per-warp scratch sized by ``warp_reduce_scratch_bytes()``; ``TRAILING_SYNC`` emits ``__syncwarp()``. -``glass::`` *(bare)* block **Measured default** — block-scope calling contract, body chosen by ``glass::dispatch_body()``; see below. (Likewise bare ``glass::nvidia::``.) -``glass::cgrps::`` block *Convenience alias* of Block via a cooperative-groups handle (same numerics; not a separately-tuned backend). +``glass::nvidia::thread::`` thread **Nvidia-thread** — cuSOLVERDx 0.4+ LAPACK, one packed problem per CUDA thread; smem-less signatures and no block-wide synchronization. +``glass::`` *(bare)* block **Measured default** — block-scope calling contract, body chosen by ``glass::dispatch_body()``; see below. +``glass::cgrps::`` block *Adapter* for callers that already hold a cooperative-groups handle (same numerics; not a separately-tuned backend). ================================ ====== ================================================= ``glass::thread::`` mirrors the branch-free surface only: reduction *strategy* @@ -46,10 +45,11 @@ The bare and explicit spellings make a deliberate implementation choice: - **Explicit namespaces pin an implementation.** ``glass::block::gemm`` (and likewise ``glass::warp::`` / ``glass::thread::`` / ``glass::nvidia::block::`` - / ``glass::nvidia::warp::``) is never re-dispatched. Use these from codegen + / ``glass::nvidia::warp::`` / ``glass::nvidia::thread::``) is never + re-dispatched. Use these from codegen and wherever implementation or reduction order is load-bearing. -- **Bare** ``glass::gemm`` (and bare ``glass::nvidia::gemm``) **is the - measured-default face**: the same block-scope *calling* contract — all block +- **Bare** ``glass::gemm`` **is the measured-default face**: the same + block-scope *calling* contract — all block threads enter, any thread count, the result is valid after return — with the implementation *body* chosen per (op, size, dtype) by ``glass::dispatch_body()`` in ``glass-dispatch.cuh``. @@ -67,6 +67,12 @@ Retuning is therefore a receipt-gated source change; see :doc:`tuning`. Rule of thumb: **explicit namespace = contract tier; bare namespace = performance tier.** +There is intentionally no bare ``glass::nvidia::op`` re-export. NVIDIA calls +must name ``block``, ``warp``, or ``thread`` because that scope changes the +launch contract. This keeps ``glass::nvidia::*`` aligned with the explicit +native interfaces and prevents a block-only alias from looking like an +autotuned counterpart to bare ``glass::*``. + Axis B — reduction strategy (function-name suffixes, vector reductions only) ----------------------------------------------------------------------------- diff --git a/docs/source/user_guide/concepts/testing_oracles.rst b/docs/source/user_guide/concepts/testing_oracles.rst index 62dd841..561bd85 100644 --- a/docs/source/user_guide/concepts/testing_oracles.rst +++ b/docs/source/user_guide/concepts/testing_oracles.rst @@ -3,7 +3,7 @@ Testing, oracles & receipts Every Doxygen-documented public overload is compile-covered by a CUDA test TU (the 100% overload badge — an *overload-manifest* metric, not line or semantic -coverage), while each behavioral family is exercised on a GPU against the 20 +coverage), while each behavioral family is exercised on a GPU against the 21 declared obligations below. Every push to ``main`` that touches library or test sources carries a **signed receipt** (`pytest-gpu-proof `_): a keyholder @@ -22,7 +22,7 @@ public function overload—not a name—matched to a compatible call in from the supported surface, with a reason for every exclusion. Compile-only canary TUs close overload-shape gaps; they do not claim numerical correctness. Numerical correctness, dtype/layout coverage, conditioning, thread-count -invariance, and cross-tier agreement are separate required obligations — 20 +invariance, and cross-tier agreement are separate required obligations — 21 declared in ``test/coverage-obligations.json``, each checked for passing evidence in the signed receipt by ``coverage_obligations.py``. diff --git a/docs/source/user_guide/concepts/trailing_sync.rst b/docs/source/user_guide/concepts/trailing_sync.rst index 66b1cfa..dc5d471 100644 --- a/docs/source/user_guide/concepts/trailing_sync.rst +++ b/docs/source/user_guide/concepts/trailing_sync.rst @@ -16,7 +16,7 @@ Default vs. opt-out // Default — function returns with all threads at a block-wide barrier. // Safe to read the result from any thread in the block immediately after. - glass::nvidia::gemm_strided_batched_1d( + glass::nvidia::block::gemm_strided_batched_1d( 1.f, A, B, 0.f, C); // Opt-out — caller is responsible for syncing before reading any output @@ -24,7 +24,7 @@ Default vs. opt-out // subsequent block-wide work that ALREADY does its own barrier (e.g. a // parallel_loop that begins with __syncthreads()), so two back-to-back // syncs collapse into one. - glass::nvidia::gemm_strided_batched_1d< + glass::nvidia::block::gemm_strided_batched_1d< float, 4, 4, 4, BATCH, TC, /*B_STRIDE=*/N*K, /*C_STRIDE=*/M*K, layout::col_major, layout::col_major, layout::col_major, diff --git a/docs/source/user_guide/concepts/tuning.rst b/docs/source/user_guide/concepts/tuning.rst index 5f88a5b..79a897e 100644 --- a/docs/source/user_guide/concepts/tuning.rst +++ b/docs/source/user_guide/concepts/tuning.rst @@ -4,11 +4,13 @@ Tuning for Your Hardware One command — ``bench/tune.py`` ------------------------------- -GLASS ships three measured defaults tables: the thread/warp/block/nvidia **backend -ladder** (``glass-defaults.cuh``, consumed by ``glass::suggested_backend<>``), +GLASS ships measured native/NVIDIA execution plans, a vendor implementation +table, and explicit-algorithm characterization. The native and NVIDIA +thread/warp/block **backend ladder** (``glass-defaults.cuh``, consumed by +``glass::recommend<>``), the per-(M,N,K) **cuBLASDx-vs-SIMT table** (``src/nvidia/tuning_table.cuh``, the -main subject below), and the serial-vs-reduced **``suggested_use_reduced<>``** -predicate. ``bench/tune.py`` remeasures all of them on your GPU and regenerates +main subject below), and the serial-vs-reduced characterization are all driven +by ``bench/tune.py``. It remeasures them on your GPU and regenerates them under **one shared noise margin**, so nothing bakes sub-noise jitter and a pure-noise re-run reproduces the same tables: @@ -33,7 +35,7 @@ keyed on the rendered source + a digest of the whole header library + the SM, so library edit transparently rebuilds only the affected binaries. The shared rule (``bench/tune_pick.py::pick``): a dependency-carrying impl -(``nvidia`` / ``cublasdx`` / ``reduced``) wins **only if it beats the simplest +(``nvidia`` / ``nvidia_thread`` / ``cublasdx`` / ``reduced``) wins **only if it beats the simplest impl by more than the margin** — otherwise the no-dependency path (always launchable, no MathDx) stays. Every op is measured and recorded; a dispatch picker is regenerated only where ≥2 impls genuinely compete. **Run on a quiet @@ -57,7 +59,7 @@ before continuing. The cuBLASDx-vs-SIMT table -------------------------- -GLASS's ``glass::nvidia::*`` wrappers — ``gemm``, ``gemv``, ``row_strided_*``, +GLASS's ``glass::nvidia::block::*`` wrappers — ``gemm``, ``gemv``, ``row_strided_*``, ``gemm_batched_1d`` — auto-dispatch between a pure-SIMT path and cuBLASDx at compile time (see :doc:`backend_dispatch`). The decision lives in ``src/nvidia/query_simt.cuh::should_use_cublasdx*<>()`` and consults, in order: @@ -75,9 +77,9 @@ independently for a given (shape, SM). Picking a backend: measured defaults ------------------------------------ -Before the nvidia dispatch table (below), the higher-level question is *warp vs -block vs nvidia* for your op and size. The three-contender sweep -(``bench/tune.py --legs ladder`` → ``bench/RESULTS.md``) measures all three on +Before the nvidia dispatch table (below), the higher-level question is *thread +vs warp vs block vs NVIDIA block vs NVIDIA thread* for your op and size. The +five-contender sweep (``bench/tune.py --legs ladder``) measures them on one ns/problem axis. Numbers below are **RTX 5090 / sm_120**; breakevens shift on other GPUs, so re-run the sweep on yours. @@ -103,7 +105,7 @@ GPUs, so re-run the sweep on yours. - **warp** ≤ N≈8, else **block** - scale 64→256 with N - 2–4 - * - ``chol`` / ``trsv`` / ``posv`` + * - ``potrf`` / ``trsv`` / ``posv`` - **warp**; block fallback **TB=32** - 32 - 2–4 @@ -112,27 +114,38 @@ Rule of thumb: **warp-per-problem by default**; ``gemv`` → block past N≈48, block once non-tiny. Factor/solve want block ``TB=32`` — extra threads idle on the serial pivot and TB>32 *hurts*. -**If you link MathDx** (``glass::nvidia::``), the vendor path wins a middle band (f32): -``gemm`` N≈16–64 (block above; cuBLASDx is smem-capped past 64 here), ``chol``/``posv`` -N≥16 through 128 (cuSOLVERDx, 1.5–2.7×), ``trsv`` only N≈16–32 (warp wins above). In -**f64** the band is narrower (≈ N=16–64; the double descriptors hit the ~99 KB opt-in -smem cap at 64). For a *single* large problem (batch≈1), the vendor path wins -factor/solve/gemm from N≈32 (up to ~8×). See ``bench/RESULTS.md`` for the full -per-op × per-precision tables. - -These defaults are also exposed as ``constexpr`` helpers in ``glass-defaults.cuh`` — -``glass::suggested_backend()``, ``suggested_block_threads<>()`` and -``suggested_warps_per_block<>()`` — so callers and codegen can pick a backend + launch -config without hand-copying the table. Include it after ``glass.cuh`` (and after -``glass-nvidia.cuh`` to make the ``nvidia`` tier eligible; otherwise it collapses to the -warp/block runner-up). The pick is host-/codegen-side because the tiers need -different ``<<>>`` launches. (The sm_120 tables include the ``thread`` -tier as of the 2026-07-18 sweep — see the note in -:doc:`../../api_reference/defaults`.) Tables are per-arch (``ideal_sm120`` today) +**If you link MathDx**, both ``glass::nvidia::block`` and +``glass::nvidia::thread`` +interfaces enter the ladder where supported. Which one wins is not monotonic: +the current sm_120 and sm_87 tables select NVIDIA thread for some small +``potrf``/``trsv``/``posv`` cells, NVIDIA block elsewhere, and native tiers in +the remaining bands. See :doc:`../tutorials/sweep_results` and +``bench/RESULTS.md`` for the dated per-op × per-precision results. + +In-place solver timing has one additional gate. The main ladder measures +back-to-back throughput and restores inputs once per trial; after its first +launch, an in-place solver therefore consumes its own output. Whenever that +ladder selects NVIDIA thread, ``bench_nvt_valid.cu`` remeasures native +thread/warp/block and NVIDIA thread with a ring of independent valid systems, +one per timed launch. NVIDIA thread must clear the same 5% margin there or the +table falls back to the valid-input native winner. This companion leg is a +veto only: it cannot promote a vendor path the main ladder did not select, and +missing confirmation evidence makes regeneration fail closed. The gate also +uses each contender's observed three-trial interval: if those intervals cannot +resolve the 5% boundary, regeneration stops for a quieter recapture. + +The ``constexpr`` ``glass::recommend()`` query returns one +``execution_plan`` containing family, scope, and launch packing. +Pass ``dependency_set::mathdx`` explicitly to admit NVIDIA candidates; +``native_only`` is the default. Each measured architecture stores both the +full winner and the measured native-only winner for every cell. The pick is +host-/codegen-side because +the tiers need different ``<<>>`` launches. Tables are per-arch +(``ideal_sm120`` and ``ideal_sm87`` today) behind an SM dispatch; ``bench/tune.py --sm auto`` adds or refreshes your GPU's table (and the tables below) in-tree, leaving other arches' tables untouched. -Note that ``suggested_backend<>`` advises **launch-level** packing — the caller +Note that ``recommend<>`` advises **launch-level** packing — the caller changes the ``<<>>``. Distinct from it, ``glass::dispatch_body()`` (``glass-dispatch.cuh``) picks the **in-block body** behind the bare ``glass::op`` face under a *fixed* block-scope calling contract — the launch @@ -155,18 +168,23 @@ What a retune actually changes (sm_120 vs sm_87) ------------------------------------------------ GLASS ships two measured architectures today: ``sm_120`` (RTX 5090, 170 SMs) -and ``sm_87`` (Jetson AGX Orin, 16 SMs, integrated memory). Comparing them is -the clearest answer to "do I need to retune?". - -**Yes, per architecture.** Of the 396 (op, N, precision, batch) cells measured -on both, **125 (32 %) crown a different tier** — and systematically toward more -problem packing on the smaller part: 34 cells move warp → thread, 27 block → -warp, 17 nvidia → thread. The thread tier's share nearly doubles (64 → 118 -cells). With far fewer SMs to fill, packing more problems per warp beats -spreading one problem across more lanes. No library source differs between the -two machines; a third of the dispatch decisions do. - -**No, per power mode.** The same Orin measured at all three standard +and ``sm_87`` (Jetson AGX Orin, 16 SMs, integrated memory). Comparing the +2026-08-30 five-backend captures is the clearest answer to "do I need to +retune?". + +**Yes, per architecture.** In the raw five-backend ladder, of the 396 +(op, N, precision, batch) cells measured on both, **131 (33 %) crown a +different tier**. The smaller Orin selects native +thread more often (87 vs 66 cells), NVIDIA thread more often (52 vs 29), and +block less often (48 vs 82). After the independent-valid-input veto, the +NPROB=8192 regime that actually generates the tables differs in **39 of 132** +cells. With far fewer SMs to fill, packing more +problems per warp often beats spreading one problem across more lanes, but the +movement is not one-directional. No library source differs between the two +machines; roughly a third of the decisions do. + +**Historically, no material retune was needed per power mode.** Before the +NVIDIA-thread contender was added, the same Orin measured at all three standard ``nvpmodel`` modes slows by a median 1.49× (30 W → 15 W), 1.31× (50 W → 30 W), 1.95× end to end — but the picks barely move: 8 of 396 cells differ between 15 W and 30 W, 11 between 30 W and 50 W, 7 across the full span. @@ -181,11 +199,14 @@ mode is covered. Two practical notes from the Orin bring-up: -* NVIDIA ships no MathDx for Tegra, but the cuSOLVERDx **LTO-IR fatbins are +* NVIDIA ships no native MathDx host package for Tegra, but the cuSOLVERDx + **LTO-IR fatbins are architecture-neutral**: ``tune.py`` detects a non-x86 host and stages a separate-compilation device link against the fatbin, so Jetson runs the full - four-tier ladder. It is worth having — the vendor tier wins 118 of 396 cells - on sm_87 (Cholesky up to 3.7× over the best SIMT tier at small N). + native/NVIDIA ladder. In the current capture, the NVIDIA block and thread + tiers take 87 and 52 of 396 raw ladder cells respectively; the shipped + throughput table retains NVIDIA thread in 15 of 132 cells after its + independent-valid-input veto. * The ``nvpmodel`` labels are ceilings, not draws. Sampling the board rails at 1 Hz with the GPU ≥98.6 % busy, the whole ladder pulls 9.2 W in the 15 W mode, 13.4 W in the 30 W mode and 16.0 W in the 50 W mode. Small @@ -195,7 +216,7 @@ Two practical notes from the Orin bring-up: **Race to idle** — run the highest standard mode your thermals allow and let the board idle between control cycles. -**How reproducible is a retune?** Two independent 50 W captures of the same +**In that four-backend power-mode study, how reproducible was a retune?** Two independent 50 W captures of the same board (different sessions, hours apart) crown the same winner in 391 of 396 cells (98.7 %), and originally generated tables differing in exactly one line: ``gemm`` f64 near N=48, where the block and warp tiers land within 1 % @@ -294,10 +315,10 @@ Debugging dispatch decisions #include "glass-nvidia.cuh" int main() { - glass::nvidia::print_dispatch(); - // → "glass::nvidia::gemm: SIMT fallback" - glass::nvidia::print_dispatch_gemv(); - // → "glass::nvidia::gemv: cuBLASDx (needs DEFINE_NVIDIA_GEMV*)" + glass::nvidia::block::print_dispatch(); + // → "glass::nvidia::block::gemm: SIMT fallback" + glass::nvidia::block::print_dispatch_gemv(); + // → "glass::nvidia::block::gemv: cuBLASDx" } These are ``__host__ __device__`` so you can call them from ``main`` for diff --git a/docs/source/user_guide/getting_started/installation.rst b/docs/source/user_guide/getting_started/installation.rst index f40e056..340799e 100644 --- a/docs/source/user_guide/getting_started/installation.rst +++ b/docs/source/user_guide/getting_started/installation.rst @@ -75,7 +75,7 @@ manual download from the NVIDIA Developer portal. - Used by - Header-only? * - CUB - - ``glass::nvidia::reduce`` / ``dot`` / ``nrm2`` + - ``glass::nvidia::block::reduce`` / ``dot`` / ``nrm2`` - Yes (bundled with CUDA) * - cuBLASDx - ``gemv``, ``gemm``, batched GEMM @@ -90,8 +90,9 @@ Download 1. Go to https://developer.nvidia.com/cublasdx-downloads (a free NVIDIA Developer account is required). 2. Choose **MathDx for CUDA 12, Linux x86_64** (``.tar.gz``). Version 25.12.x - or later is recommended — that is the version the GLASS wrappers are tested - against. + or later supports the block wrappers. Use **MathDx 26.03 or later** for + ``glass::nvidia::thread::`` (cuSOLVERDx 0.4+); 26.03 is the version covered + by the thread-scope correctness suite. Install ~~~~~~~ @@ -105,7 +106,7 @@ Install ls /opt/nvidia/mathdx/ # Set the environment variable (add to ~/.bashrc to persist) - export MATHDX_ROOT=/opt/nvidia/mathdx/25.12 # adjust version as needed + export MATHDX_ROOT=/opt/nvidia/mathdx/26.03 # adjust version as needed Verify ~~~~~~ diff --git a/docs/source/user_guide/getting_started/library_overview.rst b/docs/source/user_guide/getting_started/library_overview.rst index 6647815..d3e662e 100644 --- a/docs/source/user_guide/getting_started/library_overview.rst +++ b/docs/source/user_guide/getting_started/library_overview.rst @@ -37,14 +37,10 @@ problems run in parallel — one per block. Interfaces ---------- -GLASS exposes four primary interfaces. Two are **block-scoped** (one block per -problem) — ``glass::block::`` and the vendor-backed -``glass::nvidia::block::`` -— one is **warp-scoped**, ``glass::warp::`` (one warp per problem), for kernels -that pack many small independent problems into a block, and one is -**thread-scoped**, ``glass::thread::`` (one problem per *thread*, 32 packed per -warp), for the low-DOF corner where even a warp per problem leaves most lanes -idle: +GLASS exposes three execution scopes — block, warp, and thread — in a +dependency-free implementation family and, where NVIDIA provides a suitable +device routine, an optional vendor family. This is a small matrix of explicit +spellings rather than one flat list of interchangeable interfaces: .. list-table:: :header-rows: 1 @@ -64,14 +60,22 @@ idle: - inline in the base L1/L2/L3 headers * - ``glass::thread::`` (Thread) - thread - - Sequential, thread-per-problem — compile-time sizes, register-resident up to ``N≤7``, branch-free ops only + - Sequential, thread-per-problem — compile-time sizes, usually register-resident around ``N≤7`` but correct and measured beyond it; branch-free ops only - inline in the base L1/L2/L3 headers * - ``glass::nvidia::block::`` (Nvidia) - block - CUB (L1) + cuBLASDx (L2/L3, batched) + cuSOLVERDx (LAPACK) — compile-time sizes only; plus ``glass::nvidia::warp::`` CUB ``WarpReduce`` L1 reductions (one full 32-lane warp per problem) - ``glass-nvidia.cuh`` + * - ``glass::nvidia::warp::`` (Nvidia warp) + - warp + - CUB ``WarpReduce`` L1 reductions, one full warp per problem and explicit per-warp scratch + - ``glass-nvidia.cuh`` + * - ``glass::nvidia::thread::`` (Nvidia thread) + - thread + - cuSOLVERDx 0.4+ LAPACK, one packed compile-time problem per CUDA thread; no dynamic shared scratch or block barrier + - ``glass-nvidia.cuh`` -**Bare** ``glass::op`` (and bare ``glass::nvidia::op``) is the +**Bare** ``glass::op`` is the **measured-default face**: the same block-scope calling contract, body chosen per (op, size, dtype) by ``glass::dispatch_body()`` (``glass-dispatch.cuh``). Measured cells may use a warp-0 or thread-0 implementation behind a wrapper; @@ -142,25 +146,25 @@ implementation, three questions narrow the choice: - ``glass::gemm(...)`` - Compiler unrolls inner loops; ~1 µs/op overhead is hard to beat for tiny sizes * - Compile-time sizes, larger matrices, tensor-core hardware - - ``glass::nvidia::gemm(...)`` + - ``glass::nvidia::block::gemm(...)`` - cuBLASDx generates SM-specific tensor-core code * - Compile-time sizes inside a kernel using a different thread count - - ``glass::nvidia::gemm(...)`` with ``DEFINE_NVIDIA_GEMM_BLOCKDIM(M,N,K,TC)`` + - ``glass::nvidia::block::gemm(...)`` with ``DEFINE_NVIDIA_GEMM_BLOCKDIM(M,N,K,TC)`` - Pins cuBLASDx's ``BlockDim``; lets you launch with any thread count ≥ TC * - Need a transposed B / row-major storage in the NVIDIA path - - ``glass::nvidia::gemm<...,LA,LB,LC>`` with ``DEFINE_NVIDIA_GEMM_BLOCKDIM_LAYOUT(...)`` + - ``glass::nvidia::block::gemm<...,LA,LB,LC>`` with ``DEFINE_NVIDIA_GEMM_BLOCKDIM_LAYOUT(...)`` - cuBLASDx Arrangement; no SIMT fallback needed * - Linear solve ``Mx = b`` for SPD ``M`` - - ``glass::nvidia::posv(...)`` + - ``glass::nvidia::block::posv(...)`` - cuSOLVERDx fused factor + solve; faster than chol+trsm at N ≥ 8 * - General linear solve (non-SPD) - - ``glass::nvidia::gesv_no_pivot(...)`` + - ``glass::nvidia::block::gesv_no_pivot(...)`` - cuSOLVERDx LU + solve * - Least-squares / over- or under-determined - - ``glass::nvidia::gels(...)`` + - ``glass::nvidia::block::gels(...)`` - cuSOLVERDx QR (or LQ) + solve * - ``BATCH`` independent GEMMs of the same shape, amortize launch - - ``glass::nvidia::gemm_batched<...,BATCH,TC>`` + - ``glass::nvidia::block::gemm_batched<...,BATCH,TC>`` - Single block, all batches active via ``threadIdx.y`` When **not** to use ``glass::nvidia::``: @@ -172,7 +176,7 @@ When **not** to use ``glass::nvidia::``: * You're on an SM cuBLASDx doesn't tune for — it falls back to a generic config, and the pure-SIMT compile-time path is often competitive there. -The ``glass::nvidia::gemm<>`` / ``gemv<>`` / ``row_strided_*`` / +The ``glass::nvidia::block::gemm<>`` / ``gemv<>`` / ``row_strided_*`` / ``gemm_batched_1d<>`` primary templates **auto-dispatch at compile time**: small shapes route to SIMT automatically without any DEFINE macro (a ``constexpr`` selection — nothing is decided at runtime). See diff --git a/docs/source/user_guide/tutorials/benchmarks.rst b/docs/source/user_guide/tutorials/benchmarks.rst index 4daeb46..7e41bbd 100644 --- a/docs/source/user_guide/tutorials/benchmarks.rst +++ b/docs/source/user_guide/tutorials/benchmarks.rst @@ -16,24 +16,24 @@ What's in ``bench/`` - Comparison * - ``bench_reduce.cu`` - ``glass::*::reduce/dot/nrm2`` (plain, low_memory, high_speed, - compile-time) vs CUB ``BlockReduce`` vs ``glass::nvidia::reduce`` + compile-time) vs CUB ``BlockReduce`` vs ``glass::nvidia::block::reduce`` * - ``bench_gemv.cu`` - ``glass::gemv`` (runtime + compile-time) vs raw cuBLASDx vs - ``glass::nvidia::gemv`` (default + caller-pinned ``BlockDim<256>``) + ``glass::nvidia::block::gemv`` (default + caller-pinned ``BlockDim<256>``) * - ``bench_gemm.cu`` - ``glass::gemm`` (plain, tiled, compile-time) vs raw cuBLASDx vs - ``glass::nvidia::gemm`` (default + caller-pinned) + ``glass::nvidia::block::gemm`` (default + caller-pinned) * - ``bench_blockdim.cu`` - - ``glass::nvidia::gemm`` cuBLASDx-chosen block_dim vs caller-pinned + - ``glass::nvidia::block::gemm`` cuBLASDx-chosen block_dim vs caller-pinned ``BlockDim<128>`` vs ``BlockDim<352>`` * - ``bench_gemm_batched.cu`` - - ``glass::nvidia::gemm_batched<...,BATCH>`` vs a naive ``for(b)`` loop, for + - ``glass::nvidia::block::gemm_batched<...,BATCH>`` vs a naive ``for(b)`` loop, for BATCH ∈ {4, 8, 16, 32} * - ``bench_gemm_batched_1d.cu`` - 1D-launch ``gemm_batched_1d`` (SIMT vs cuBLASDx) — feeds the autotune table * - ``bench_lapack.cu`` *(needs cuSOLVERDx)* - pure-SIMT ``glass::potrf`` / ``trsm`` vs - ``glass::nvidia::potrf`` / ``trsm`` / ``posv`` (fused) + ``glass::nvidia::block::potrf`` / ``trsm`` / ``posv`` (fused) CUB ships with CUDA 11+. cuBLASDx and cuSOLVERDx ship together in NVIDIA MathDx — see :doc:`../getting_started/installation`. diff --git a/docs/source/user_guide/tutorials/examples.rst b/docs/source/user_guide/tutorials/examples.rst index 8467547..7380cbc 100644 --- a/docs/source/user_guide/tutorials/examples.rst +++ b/docs/source/user_guide/tutorials/examples.rst @@ -37,7 +37,7 @@ which requires MathDx. host helper - pure SIMT * - ``05_nvidia_gemm`` - - the cuBLASDx-backed ``glass::nvidia::gemm`` path + - the cuBLASDx-backed ``glass::nvidia::block::gemm`` path - **requires MathDx** * - ``06_warp_ops`` - single-warp ``glass::warp::`` ops (reduce, 4×4 gemm, potrf+trsv), @@ -47,7 +47,7 @@ which requires MathDx. - block-tridiagonal PCG solve ``glass::pcg`` (``[L|D|R]`` strips) - pure SIMT * - ``08_backend_picker`` - - ``suggested_backend<>`` driving a warp/block/thread ``posv`` launch + - ``recommend<>`` driving a warp/block/thread ``posv`` launch - pure SIMT * - ``09_gemm_strided`` - GEMM on sub-blocks with explicit leading dims (``gemm_strided``) diff --git a/docs/source/user_guide/tutorials/quickstart.rst b/docs/source/user_guide/tutorials/quickstart.rst index e54ff7d..6f1cc7c 100644 --- a/docs/source/user_guide/tutorials/quickstart.rst +++ b/docs/source/user_guide/tutorials/quickstart.rst @@ -22,8 +22,10 @@ Launch with one block per data item: my_kernel<<>>(A, B, C, m, n, k); -That's the whole contract: every GLASS function assumes it runs inside **one -CUDA block**, and you launch one block per independent problem. +That's the whole contract for the bare face: every participating thread in one +CUDA block enters the call, and you launch one block per independent problem. +Explicit ``glass::warp::`` and ``glass::thread::`` APIs instead own one problem +per full warp or per CUDA thread; see :doc:`../concepts/namespaces`. Compiling --------- diff --git a/docs/source/user_guide/tutorials/sweep_results.rst b/docs/source/user_guide/tutorials/sweep_results.rst index a88bf3d..9e605ec 100644 --- a/docs/source/user_guide/tutorials/sweep_results.rst +++ b/docs/source/user_guide/tutorials/sweep_results.rst @@ -5,7 +5,7 @@ GLASS ships overlapping thread-, warp-, block-, and vendor-backed execution tiers. For operations present in more than one tier, the fastest choice depends on operation, size, dtype, launch shape, and batch regime. The **mega sweep** (``bench/tune.py``'s ladder leg) compares supported contenders — this is -exactly the measurement behind ``glass-defaults.cuh``'s ``suggested_backend<>()`` +exactly the measurement behind ``glass-defaults.cuh``'s ``recommend<>()`` (see :doc:`../../api_reference/defaults`). .. warning:: @@ -15,13 +15,14 @@ exactly the measurement behind ``glass-defaults.cuh``'s ``suggested_backend<>()` source-digest, and signed-receipt protocol and are marked accordingly. Use the source capture named beside a claim, and rerun on the target machine. -The figures and table below are from an RTX 5090 / sm_120 run, shown across three -batch regimes — **NPROB=64** (low batch, latency-leaning), **NPROB=1024** (mid), -and **NPROB=8192** (the throughput regime that feeds the dispatch tables). The -winner can shift with batch size: at low batch the vendor (``nvidia``) path often -wins the factor/solve ops on launch-amortized latency, while at high batch the -hand-rolled SIMT paths scale back in. They are committed static assets — -regenerate them for your own hardware with:: +The figures and table below come from the 2026-08-30 RTX 5090 / sm_120 +five-backend sweep, shown across three batch regimes — **NPROB=64** (low batch, +latency-leaning), **NPROB=1024** (mid), and **NPROB=8192** (throughput). The +committed dispatch table uses a separate 500-repetition throughput replication; +the figures use the full three-regime capture. The winner can shift with batch +size, so low-batch plots describe that workload rather than overriding the +throughput table. These are committed static assets — regenerate them for your +own hardware with:: python bench/tune.py --sm auto # remeasures + regenerates tables AND figures # or just the figures from an existing sweep .txt: @@ -32,18 +33,22 @@ regenerate them for your own hardware with:: The ladder — ns/problem vs N, per backend ------------------------------------------ -Lower is faster. Each subplot is one op; the curves are ``warp`` (green), -``block`` (blue), ``thread`` (orange, N≤16 — one problem per thread, 32 packed -per warp), and ``nvidia`` / MathDx (red). The crossover points are where -``suggested_backend`` switches tiers — the 2026-07-18 sweep hands thread the -low-DOF corner of every op except ``gemm`` (up to 7.5× on ``posv`` f64 at N≤6; -verdict tables in the thread-tier section below). Where a ``thread`` curve -stops short of N=128 the remaining launches are *infeasible*, not unmeasured — -the per-thread local-memory footprint exceeds the launch limit (those cells are -``FAIL``-marked in the capture); the ``nvidia`` f64 curves cap at N=64 for the -same reason on the shared-memory side. ``suggested_backend<>()`` is keyed on the -**NPROB=8192** throughput regime; the 64/1024 figures show how the crossovers -move at smaller batch. +Lower is faster. Each subplot is one op; the curves are native ``warp`` +(green), ``block`` (blue), and ``thread`` (orange), plus NVIDIA ``block`` +(red) and ``thread`` (purple). Both thread curves pack one problem per CUDA +thread. The native thread implementation is instantiated through ``N=64`` in +this harness; NVIDIA thread LAPACK is instantiated through ``N=32``. A stopped +curve therefore marks an explicit instantiation or resource boundary, not a +claim that larger sizes are unsupported by CUDA or cuSOLVERDx. NVIDIA block +f64 curves may stop at their shared-memory feasibility limit. + +``recommend<>()`` is keyed on the **NPROB=8192** throughput regime. +Its policy first applies a ±2% tie band among dependency-free SIMT contenders, +then requires an NVIDIA contender to clear the best native choice by more than +5%. NVIDIA-thread solver winners must additionally reproduce that margin when +every timed launch consumes an independent valid system. This confirmation is +a veto only; it cannot promote NVIDIA thread into a cell. These rules keep +small, noisy, or mutation-dependent gaps out of the generated table. float32 ~~~~~~~ @@ -57,7 +62,7 @@ float32 :width: 100% .. image:: /_static/mega_sweep_ladder_f32_n8192.png - :alt: f32 ladder, NPROB=8192 (throughput — feeds suggested_backend) + :alt: f32 ladder, NPROB=8192 (throughput — feeds recommend) :width: 100% float64 @@ -72,19 +77,21 @@ float64 :width: 100% .. image:: /_static/mega_sweep_ladder_f64_n8192.png - :alt: f64 ladder, NPROB=8192 (throughput — feeds suggested_backend) + :alt: f64 ladder, NPROB=8192 (throughput — feeds recommend) :width: 100% -Winner per (op, N), per regime ------------------------------- +Raw ladder winner per (op, N), per regime +------------------------------------------ -The backend with the lowest ns/problem at each ``(op, N)``, listed for all three -NPROB regimes — the ``NPROB=8192`` block is what ``suggested_backend<>()`` -encodes. The broad shape at high batch: tiny ``N`` favors ``warp``; mid sizes -favor ``nvidia`` for the factor/solve ops (chol/posv/trsv) once MathDx amortizes; -``gemv`` crosses to ``block`` early; ``dot`` stays ``warp`` throughout. At -``NPROB=64`` the ``nvidia`` band widens (launch latency dominates, so the vendor -kernels win sooner). +The main-ladder policy winner at each ``(op, N)`` is listed for all three +NPROB regimes. The separate valid-input veto affects only final +NVIDIA-thread throughput defaults and is summarized below; it does not rewrite +these raw-capture figures. +The broad high-batch shape is mixed by design: native thread dominates many +small packed problems, native warp/block remain important as work grows, and +the NVIDIA block and thread implementations take measured factor/solve bands. +The ``NPROB=8192`` block shown here is from the full capture; the generated +sm_120 table uses its higher-repetition replication. .. literalinclude:: /_static/sweep_winners.txt :language: text @@ -202,10 +209,52 @@ generalizing, or measure with your actual matrices. Jacobi family. It did not include the parallel fixed-sweep ``eigh`` / ``psd_project`` family, so it cannot support a recommendation between them. -The thread tier — where one-problem-per-thread wins ---------------------------------------------------- +NVIDIA thread LAPACK — measured integration +--------------------------------------------- + +The 2026-08-30 wave added cuSOLVERDx's thread interface as a fifth contender +for ``chol``, ``trsv``, and ``posv``. It is a selective win, not a replacement +for either GLASS's native thread code or cuSOLVERDx's block interface: -The 2026-07-19 full-domain sweep (quiet RTX 5090) added the ``thread`` +.. list-table:: Throughput cells selected by the generated policy + :header-rows: 1 + :widths: 16 14 30 40 + + * - GPU + - cells + - float32 + - float64 + * - RTX 5090 / sm_120 + - 14 / 132 + - ``chol`` N=6,8; ``trsv`` N=24 + - ``chol`` N=4,6,8; ``posv`` N=4,6,8; ``trsv`` N=8–32 + * - Jetson AGX Orin / sm_87 + - 15 / 132 + - ``chol`` N=8,12; ``trsv`` N=16,24,32 + - ``chol`` N=4,6,8; ``trsv`` N=4–32 + +Those ranges enumerate the measured sizes ``4, 6, 8, 12, 16, 24, 32``; they +do not imply testing every intervening integer. Against the fastest native +tier on independent valid inputs, selected NVIDIA-thread cells range from +about 1.09× to 2.34× on the RTX 5090 and 1.08× to 3.53× on Orin. The largest +gains are concentrated in ``trsv``; other operations and sizes still select +another tier. + +The 5090 throughput leg was run twice independently at 250 and 500 +repetitions. The raw ladder policy agreed in 131 of 132 cells, agreed on all +17 pre-veto NVIDIA-thread selections, and disagreed only on ``dot`` f32 N=16 inside the +native-SIMT tie band. Across the NVIDIA-thread measurements, the second/first +median time ratio was 0.999 (10th–90th percentile 0.984–1.026). The Orin +throughput capture used the Tegra profile (50 repetitions, pinned 50 W mode). +The subsequent valid-input captures on both machines had sub-margin spread at +every retained or vetoed NVIDIA-thread decision and reduced the shipped bands +to the 14 and 15 cells above. These checks support the selected bands, not a +portable speedup claim—rerun both ladder components on a new architecture. + +The native thread tier — historical characterization +------------------------------------------------------ + +The 2026-07-19 full-domain sweep (quiet RTX 5090) first added the native ``thread`` contender at every ``(op, N)`` point. Throughput regime (NPROB=8192), thread vs the best other tier (ratio > 1 = thread faster; **bold** cells shipped): diff --git a/docs/source/user_guide/tutorials/using_nvidia_backend.rst b/docs/source/user_guide/tutorials/using_nvidia_backend.rst index 98f3554..eb68d3b 100644 --- a/docs/source/user_guide/tutorials/using_nvidia_backend.rst +++ b/docs/source/user_guide/tutorials/using_nvidia_backend.rst @@ -4,9 +4,7 @@ Using the NVIDIA Backend The ``glass::nvidia::block::`` interface routes to NVIDIA's device-side libraries — CUB (L1), cuBLASDx (L2/L3 GEMM/GEMV/batched), and cuSOLVERDx (LAPACK) — while preserving the same one-block ``__device__`` calling -convention. These wrappers require **compile-time** matrix sizes. (Bare -``glass::nvidia::`` spellings are the measured-default face; its measured -dispatch is described in :doc:`../concepts/namespaces`. There is +convention. These wrappers require **compile-time** matrix sizes. There is also ``glass::nvidia::warp::`` — CUB ``WarpReduce`` ``reduce`` / ``dot`` / ``nrm2``, one FULL 32-lane warp per problem, per-warp scratch via ``warp_reduce_scratch_bytes()``, ``TRAILING_SYNC`` emitting @@ -53,8 +51,10 @@ differ by which level you use. -lcusolverdx -lcublas -lcusolver -lcudart \ my_kernel.cu -o my_kernel -``SMS`` defaults to ``860`` and can be overridden with ``-DSMS=XXX`` so the -dispatch heuristic and cuBLASDx code-gen target your arch. +Define ``GLASS_TARGET_SM`` so the execution-plan table, native body dispatch, +and MathDx descriptors target the same architecture, for example +``-DGLASS_TARGET_SM=860``. It defaults to the shipped sm_120 seed. ``SMS`` is +accepted as a legacy input alias. Calling ``glass::nvidia::block::`` — default form ------------------------------------------------- @@ -181,6 +181,26 @@ Available cuSOLVERDx wrappers: ``potrf``, ``trsm``, ``posv``, ``potrs``, All follow the same ``DEFINE_NVIDIA_`` macro pattern and are **not** pre-instantiated — call the macro per size you need. +Thread-scope LAPACK (cuSOLVERDx 0.4+) +-------------------------------------- + +The same nine operations are available with smem-less signatures under +``glass::nvidia::thread::``. No ``DEFINE_NVIDIA_*`` macro, block-dimension +template argument, scratch query, or barrier is needed: each CUDA thread owns +one packed problem. + +.. code-block:: cpp + + template + __global__ void batched_chol(float* matrices, int count) { + int p = blockIdx.x * blockDim.x + threadIdx.x; + if (p < count) + glass::nvidia::thread::potrf(matrices + p * N * N); + } + +Use the explicit ``block`` or ``thread`` namespace because this choice changes +launch geometry; no bare ``glass::nvidia::potrf`` alias is provided. + See :doc:`../concepts/backend_dispatch` for how the auto-dispatch decides between cuBLASDx and SIMT, and :doc:`../concepts/batched_1d` for the 1D-launch batched GEMM APIs. diff --git a/examples/05_nvidia_gemm.cu b/examples/05_nvidia_gemm.cu index c45b5b3..2a9e5c2 100644 --- a/examples/05_nvidia_gemm.cu +++ b/examples/05_nvidia_gemm.cu @@ -1,4 +1,4 @@ -// 05_nvidia_gemm.cu — cuBLASDx-backed GEMM via glass::nvidia:: (REQUIRES MathDx). +// 05_nvidia_gemm.cu — cuBLASDx GEMM via glass::nvidia::block (REQUIRES MathDx). // // This is the ONLY example that needs NVIDIA MathDx (cuBLASDx). The pure-SIMT // examples 01-05 build with plain nvcc; this one does not. @@ -7,7 +7,7 @@ // install (see ../bench/INSTALL.md): // // nvcc -std=c++17 -arch=sm_86 -I.. \ -// -DGLASS_BENCH_CUBLASDX -DSMS=860 \ +// -DGLASS_BENCH_CUBLASDX -DGLASS_TARGET_SM=860 \ // --expt-relaxed-constexpr -Xptxas -O1 \ // -I$MATHDX_ROOT/include \ // -I$MATHDX_ROOT/external/cutlass/include \ @@ -15,7 +15,7 @@ // // Notes: // * -DGLASS_BENCH_CUBLASDX force-includes from glass-nvidia.cuh. -// * -DSMS=XXX must match your -arch (860 for sm_86, 1200 for sm_120, ...); +// * -DGLASS_TARGET_SM=XXX must match -arch (860 for sm_86, 1200 for sm_120); // it selects the cuBLASDx-tuned config and the pre-instantiated GEMM table. // * 16x16x16 is a pre-instantiated cuBLASDx shape (see glass-nvidia.cuh); the // default form launches with EXACTLY gemm_threads<>() threads and @@ -55,7 +55,7 @@ int main() { cudaDeviceSynchronize(); cudaMemcpy(hC, dC, sizeof(hC), cudaMemcpyDeviceToHost); - printf("glass::nvidia::gemm C = I*B (threads=%u smem=%zu)\n", + printf("glass::nvidia::block::gemm C = I*B (threads=%u smem=%zu)\n", (unsigned)THREADS, (size_t)SMEM); printf("C[0]=%.0f C[17]=%.0f C[255]=%.0f (expect 0 17 255)\n", hC[0], hC[17], hC[255]); diff --git a/examples/08_backend_picker.cu b/examples/08_backend_picker.cu index 9fc0ace..5d8604d 100644 --- a/examples/08_backend_picker.cu +++ b/examples/08_backend_picker.cu @@ -1,13 +1,11 @@ -// 08_backend_picker.cu — choosing a backend + launch config with glass-defaults.cuh. +// 08_backend_picker.cu — choosing an execution plan with glass-defaults.cuh. // // Build (from this examples/ dir, pure SIMT — no MathDx needed): // nvcc -std=c++17 -arch=sm_75 -I.. 08_backend_picker.cu -o picker && ./picker -// (to make the `nvidia` tier eligible, include glass-nvidia.cuh first + link MathDx.) // -// glass-defaults.cuh exposes the measured thread/warp/block/nvidia ladder (bench/RESULTS.md) -// as constexpr helpers. The pick is host-/codegen-side because warp, block, and nvidia need -// DIFFERENT <<>> launches — so you query at compile time and branch the launch. -// With no MathDx linked (as here), the `nvidia` tier collapses to its warp/block runner-up. +// recommend() exposes the measured native/NVIDIA and thread/warp/block ladder +// as one constexpr plan. The choice is host-/codegen-side because scopes need +// different launches. This example requests native-only implementations. #include "glass.cuh" #include "glass-defaults.cuh" @@ -15,12 +13,13 @@ #include using glass::op; -using glass::backend; - -static const char* name(backend b) { - return b == backend::warp ? "warp" - : b == backend::block ? "block" - : b == backend::thread ? "thread" : "nvidia"; +static const char* name(glass::execution_plan p) { + const char* family = p.implementation == glass::family::nvidia ? "nvidia" : "native"; + const char* scope = p.execution_scope == glass::scope::thread ? "thread" + : p.execution_scope == glass::scope::warp ? "warp" : "block"; + static char text[32]; + std::snprintf(text, sizeof(text), "%s/%s", family, scope); + return text; } // ── one SPD solve A x = b, dispatched to the picked backend ────────────────── @@ -41,36 +40,33 @@ template __global__ void k_thread_posv(float* A, float* b) { template static void solve_dispatch(float* dA, float* db) { // Compile-time pick from the measured table (T=float, build's SM). - constexpr backend be = glass::suggested_backend(); - printf(" posv N=%d -> backend=%s", N, name(be)); - if constexpr (be == backend::thread) { - constexpr int TPB = glass::suggested_threads_per_block(); - printf(" (TPB=%d)\n", TPB); + constexpr auto plan = glass::recommend(); + printf(" posv N=%d -> plan=%s", N, name(plan)); + if constexpr (plan.execution_scope == glass::scope::thread) { + printf(" (TPB=%u)\n", plan.block_threads); k_thread_posv<<<1, 1>>>(dA, db); // 1 problem here -> 1 thread - } else if constexpr (be == backend::warp) { - constexpr int WPB = glass::suggested_warps_per_block(); - printf(" (WPB=%d)\n", WPB); + } else if constexpr (plan.execution_scope == glass::scope::warp) { + printf(" (WPB=%u)\n", plan.problems_per_block); k_warp_posv<<<1, dim3(32, 1)>>>(dA, db); // 1 problem here -> 1 warp - } else { // block (or nvidia collapsed to block); a real nvidia tier would launch cuSOLVERDx - constexpr int TB = glass::suggested_block_threads(); - printf(" (TB=%d)\n", TB); - k_block_posv<<<1, TB>>>(dA, db); + } else { + printf(" (TB=%u)\n", plan.block_threads); + k_block_posv<<<1, plan.block_threads>>>(dA, db); } cudaDeviceSynchronize(); } int main() { // 1) Show what the picker chooses across ops/sizes (all compile-time constants). - printf("backend picks (T=float, this build's SM; no MathDx -> nvidia collapses):\n"); - printf(" dot N=8 : %s\n", name(glass::suggested_backend())); - printf(" dot N=64 : %s\n", name(glass::suggested_backend())); - printf(" posv N=8 : %s\n", name(glass::suggested_backend())); - printf(" gemv N=16 : %s\n", name(glass::suggested_backend())); - printf(" gemv N=64 : %s\n", name(glass::suggested_backend())); - printf(" gemm N=8 : %s\n", name(glass::suggested_backend())); - printf(" gemm N=32 : %s\n", name(glass::suggested_backend())); - printf(" chol N=8 : %s\n", name(glass::suggested_backend())); - printf(" chol N=64 : %s\n", name(glass::suggested_backend())); + printf("execution plans (T=float, this build's SM, native-only):\n"); + printf(" dot N=8 : %s\n", name(glass::recommend())); + printf(" dot N=64 : %s\n", name(glass::recommend())); + printf(" posv N=8 : %s\n", name(glass::recommend())); + printf(" gemv N=16 : %s\n", name(glass::recommend())); + printf(" gemv N=64 : %s\n", name(glass::recommend())); + printf(" gemm N=8 : %s\n", name(glass::recommend())); + printf(" gemm N=32 : %s\n", name(glass::recommend())); + printf(" potrf N=8 : %s\n", name(glass::recommend())); + printf(" potrf N=64 : %s\n", name(glass::recommend())); // 2) Use the pick to dispatch a real solve. SPD A = M·Mᵀ + N·I (column-major), N=16. const int N = 16; diff --git a/examples/13_thread_pack.cu b/examples/13_thread_pack.cu index 7e08b43..cf647d8 100644 --- a/examples/13_thread_pack.cu +++ b/examples/13_thread_pack.cu @@ -12,8 +12,7 @@ // // The kernel is the caller's: it stages each problem global -> thread-local // registers, runs the op on its own arrays, and writes back. Launch shape comes -// from glass::suggested_threads_per_block<>() (a seed heuristic, not a measured -// table entry — see glass-defaults.cuh). +// from glass::recommend() (see glass-defaults.cuh). #include "glass.cuh" #include "glass-defaults.cuh" @@ -54,8 +53,10 @@ int main() { cudaMemcpy(dA, hA, sizeof(hA), cudaMemcpyHostToDevice); cudaMemcpy(db, hb, sizeof(hb), cudaMemcpyHostToDevice); - // One problem per thread; TPB from the defaults heuristic (N=6 -> 64). - constexpr uint32_t TPB = glass::suggested_threads_per_block(); + // One problem per thread; the plan carries its packing (N=6 -> 64). + constexpr auto plan = glass::recommend(); + static_assert(plan.execution_scope == glass::scope::thread); + constexpr uint32_t TPB = plan.block_threads; k_thread_posv<<<(P + TPB - 1) / TPB, TPB>>>(dA, db, dx, P); cudaMemcpy(hx, dx, sizeof(hx), cudaMemcpyDeviceToHost); diff --git a/examples/Makefile b/examples/Makefile index 3a4f56d..8c8828b 100644 --- a/examples/Makefile +++ b/examples/Makefile @@ -21,7 +21,7 @@ all: $(BINS) $(NVCC) $(NVCCFLAGS) $< -o $@ 05_nvidia_gemm: 05_nvidia_gemm.cu - $(NVCC) $(NVCCFLAGS) -I$(MATHDX_ROOT)/include -I$(MATHDX_ROOT)/external/cutlass/include -DGLASS_BENCH_CUBLASDX -DSMS=$(SMS) \ + $(NVCC) $(NVCCFLAGS) -I$(MATHDX_ROOT)/include -I$(MATHDX_ROOT)/external/cutlass/include -DGLASS_BENCH_CUBLASDX -DGLASS_TARGET_SM=$(SMS) \ -Xptxas -O1 $< -o $@ run: all diff --git a/examples/README.md b/examples/README.md index fa441ee..4df0cd5 100644 --- a/examples/README.md +++ b/examples/README.md @@ -23,12 +23,12 @@ hardware. | [`05_nvidia_gemm.cu`](05_nvidia_gemm.cu) | the cuBLASDx-backed `glass::nvidia::block::gemm` path | **requires NVIDIA MathDx** | | [`06_warp_ops.cu`](06_warp_ops.cu) | single-warp `glass::warp::` ops (`reduce`, 4×4 `gemm`, SPD `potrf`+`trsm`+`trsm_transpose`), launched `<<<1,32>>>` | pure SIMT | | [`07_pcg_solve.cu`](07_pcg_solve.cu) | block-tridiagonal PCG solve `glass::block::pcg` (`[L\|D\|R]` strips, padded vectors, block-Jacobi preconditioner) | pure SIMT | -| [`08_backend_picker.cu`](08_backend_picker.cu) | choose a backend + launch config with `glass-defaults.cuh` (`suggested_backend` / `suggested_block_threads` / `suggested_warps_per_block`), then dispatch a real SPD solve to the picked launch | pure SIMT | +| [`08_backend_picker.cu`](08_backend_picker.cu) | query one `execution_plan` with `glass::recommend()`, then dispatch a real SPD solve to its scope and launch packing | pure SIMT | | [`09_gemm_strided.cu`](09_gemm_strided.cu) | `gemm_strided` — GEMM on column-major sub-blocks with explicit leading dims | pure SIMT | | [`10_ldlt_solve.cu`](10_ldlt_solve.cu) | symmetric-**indefinite** solve `ldlt` + `ldlt_solve`, plus the `CHECK=true` failure flag + **inertia** reporting (`ldlt_scratch_bytes`) | pure SIMT | | [`11_riccati_gain.cu`](11_riccati_gain.cu) | LQR feedback gain `K = (R + BᵀPB)⁻¹(BᵀPA)` via `riccati_gain`, smem sized by `riccati_scratch_bytes()` | pure SIMT | | [`12_inv.cu`](12_inv.cu) | matrix inversion on the augmented `[A \| I]` layout: `inv` (+ `inv_scratch_bytes`), and the robust `inv_pivoted` recovering a zero leading pivot | pure SIMT | -| [`13_thread_pack.cu`](13_thread_pack.cu) | the `glass::thread::` tier: 4096 N=6 SPD solves, one problem per THREAD (32 packed per warp), launch shape from `suggested_threads_per_block<>` | pure SIMT | +| [`13_thread_pack.cu`](13_thread_pack.cu) | the `glass::thread::` tier: 4096 N=6 SPD solves, one problem per THREAD (32 packed per warp), launch shape from `recommend()` | pure SIMT | | [`14_spatial_dynamics.cu`](14_spatial_dynamics.cu) | Featherstone spatial cross products (the RNEA inner loop): fused `motion_cross_mul`/`force_cross_mul` vs materialize-6×6 + `gemv` | pure SIMT | | [`15_floating_base_retract.cu`](15_floating_base_retract.cu) | batched SE(3) manifold integration at thread scope (`se3_retract`): unit-norm drift-free, one-parameter-subgroup check | pure SIMT | | [`16_mppi_weights.cu`](16_mppi_weights.cu) | the MPPI weight update: `softmax` + `argmin` per controller block, bit-identical across block sizes | pure SIMT | @@ -63,7 +63,7 @@ Install MathDx and set `MATHDX_ROOT` first — see ```bash nvcc -std=c++17 -arch=sm_86 -I.. \ - -DGLASS_BENCH_CUBLASDX -DSMS=860 \ + -DGLASS_BENCH_CUBLASDX -DGLASS_TARGET_SM=860 \ --expt-relaxed-constexpr -Xptxas -O1 \ -I$MATHDX_ROOT/include \ -I$MATHDX_ROOT/external/cutlass/include \ @@ -73,7 +73,7 @@ nvcc -std=c++17 -arch=sm_86 -I.. \ | Flag | Why | |------|-----| | `-DGLASS_BENCH_CUBLASDX` | force-includes `` from `glass-nvidia.cuh` (otherwise gated on include order) | -| `-DSMS=860` | selects the cuBLASDx-tuned config + pre-instantiated GEMM table; **must match `-arch`** (860↔sm_86, 1200↔sm_120, …) | +| `-DGLASS_TARGET_SM=860` | selects native and MathDx tables; **must match `-arch`** (860↔sm_86, 1200↔sm_120, …) | | `--expt-relaxed-constexpr` | required by cuBLASDx's constexpr `__host__`/`__device__` helpers | | `-Xptxas -O1` | works around a cuBLASDx miscompilation on recent CUDA (see `INSTALL.md`) | | `-I$MATHDX_ROOT/include` | cuBLASDx headers | diff --git a/glass-defaults.cuh b/glass-defaults.cuh index 5ec08ae..28ccc64 100644 --- a/glass-defaults.cuh +++ b/glass-defaults.cuh @@ -1,137 +1,181 @@ #pragma once /** * @file glass-defaults.cuh - * @brief Queryable backend-selection defaults — the measured warp/block/nvidia ladder - * (bench/RESULTS.md) exposed as `constexpr` so callers and GRiD-style - * codegen pick a backend + launch config instead of hand-copying a table. + * @brief Queryable execution plans for the measured placement ladder. * * The pick CANNOT be a device function: warp / block / nvidia need different * `<<>>` launches, so the decision happens host-side / at codegen time. - * These helpers answer "given (op, N, T) on this SM, which backend and how many threads?" + * `recommend()` answers "given an operation, shape, scalar, dependency set, + * and target SM, which measured implementation family/scope should the caller + * use, and what legal baseline launch packs it?" It is metadata for a host + * launcher or code generator, not + * a device-function dispatcher. * - * constexpr auto be = glass::suggested_backend(); - * if constexpr (be == glass::backend::nvidia) { ... cuSOLVERDx launch ... } - * else if constexpr (be == glass::backend::warp) { ... <<>> ... } - * else if constexpr (be == glass::backend::thread) { ... <<>> ... } - * else { ... <<>> ... } + * constexpr auto p = glass::recommend( + * glass::dependency_set::mathdx); + * // p.implementation, p.execution_scope, p.block_threads, + * // p.problems_per_block, p.shared_bytes * - * NOTE ON `thread`: measured and shipped for sm_120 (2026-07-18 sweep) — the tier - * takes the low-DOF corner of every op except gemm (up to 7.5x on posv f64 at - * N<=6; see the docs sweep-results page). `ideal_generic` and `without_nvidia` - * still predate the tier (warp/block/nvidia only) — a thread verdict appears on an - * arch once `bench/tune.py --sm auto` sweeps it there. A `backend::thread` pick - * means a thread-per-problem launch: <<>> with - * suggested_threads_per_block<>(). - * - * INCLUDE ORDER: include this AFTER glass.cuh, and after glass-nvidia.cuh if you want the - * `nvidia` tier to be eligible (it reads GLASS_HAVE_CUBLASDX / GLASS_HAVE_CUSOLVERDX, which - * glass-nvidia.cuh defines). With only glass.cuh, the nvidia tier collapses to its warp/block - * runner-up, so a no-MathDx caller always gets a backend it can actually launch. + * A thread recommendation means a thread-per-problem launch: + * `<<>>`. Vendor-backed + * candidates are admitted only when the caller explicitly passes + * `dependency_set::mathdx`. Each measured architecture also ships its measured + * native runner-up table, so either policy is data-backed and neither depends + * on header include order. * * Tables are **per-arch**: every swept SM gets its own constexpr ladder (`ideal_sm120` * today, measured on an RTX 5090), and `bench/tune.py --sm auto` adds or refreshes the * table + dispatch case for whatever GPU it runs on (e.g. `ideal_sm87` on a Jetson Orin) * without touching other arches' tables. Unmeasured SMs fall back to a coarse size - * heuristic (`ideal_generic`). When `nvidia` IS returned, the call still flows through - * `glass::nvidia::`, which refines SIMT-vs-cuBLASDx internally via should_use_cublasdx. + * heuristic (`ideal_generic`). When NVIDIA block is returned, the call flows through + * `glass::nvidia::block::`, whose implementation may refine + * SIMT-vs-cuBLASDx internally via `should_use_cublasdx`. */ #include -#include "glass-dispatch.cuh" // shared `op` enum + GLASS_DEFAULTS_SM + dispatch_body() +#include "glass-dispatch.cuh" // shared `op` enum + GLASS_TARGET_SM + dispatch_body() namespace glass { -// (`op` lives in glass-dispatch.cuh — shared with the bare face's body table.) -// APPEND-ONLY: `thread` is last so the pre-existing warp/block/nvidia ordinals are -// unchanged. Scope ladder (most→least problem packing): thread (1 problem/thread, -// 32 per warp) → warp (1/warp) → block (1/block) → nvidia (1/block, vendor). -enum class backend : int { warp, block, nvidia, thread }; +enum class family : uint8_t { native, nvidia }; +enum class scope : uint8_t { thread, warp, block }; +enum class dependency_set : uint8_t { native_only, mathdx }; -namespace defaults { +/// A measured placement plus a ready-to-use legal launch shape. The packing +/// fields are defaults, not a claim that every caller's best block size was +/// measured. `dynamic_requirement` means that the +/// selected explicit NVIDIA block wrapper's `*_threads()` or +/// `*_scratch_bytes()` query owns the exact value. +struct execution_plan { + static constexpr uint32_t dynamic_requirement = UINT32_MAX; + family implementation; + scope execution_scope; + uint32_t block_threads; + uint32_t problems_per_block; + uint32_t shared_bytes; +}; -// Vendor availability per family (auto-detected from include order; absent => no nvidia tier). -constexpr bool have_nv_blas = -#if defined(GLASS_HAVE_CUBLASDX) && GLASS_HAVE_CUBLASDX - true; -#else - false; -#endif -constexpr bool have_nv_lapack = -#if defined(GLASS_HAVE_CUSOLVERDX) && GLASS_HAVE_CUSOLVERDX - true; -#else - false; -#endif +namespace defaults { -constexpr bool nv_available(op o) { - return (o == op::gemm || o == op::gemv) ? have_nv_blas - : (o == op::chol || o == op::trsv || o == op::posv) ? have_nv_lapack - : false; // dot: nvidia never wins -} +// Generated-table implementation detail. Ordinals stay stable so archived +// captures and local override fragments remain readable across this API cleanup. +enum class backend : int { warp, block, nvidia_block, thread, nvidia_thread }; // ─── measured ladders: one constexpr table per swept arch. bench/tune.py's ladder // leg owns the marker blocks — it replaces the block for the arch it measured (and // inserts a new block + dispatch case for a first-time arch), leaving the rest alone. ─── // === BEGIN tune.py ladder sm_120 === -// Source sweep: mega_sweep_20260815_205919.txt tie margin: ±5% (nvidia must clear it; SIMT ties ±2% prefer thread>warp>block) -// Returns the *ideal* tier assuming nvidia is linked; nv_available() filters after. +// Source sweep: mega_sweep_20260830_042156.txt tie margin: ±5% (NVIDIA block/thread must clear it; SIMT ties ±2% prefer thread>warp>block) +// NVIDIA-thread valid-input veto: nvt_valid_20260830_160047.txt (3 ladder picks vetoed) +// Paired tables preserve the measured native runner-up for callers that +// do not opt into MathDx; both use the same capture and SIMT tie rule. constexpr backend ideal_sm120(op o, uint32_t N, bool f64) { switch (o) { case op::dot: - if (!f64) return N <= 12u ? backend::thread : backend::warp; + if (!f64) return N <= 12u ? backend::thread : N <= 16u ? backend::warp : N <= 24u ? backend::thread : backend::warp; else return N <= 32u ? backend::thread : backend::warp; case op::gemv: if (!f64) return N <= 6u ? backend::thread : N <= 32u ? backend::warp : N <= 48u ? backend::block : backend::warp; - else return N <= 6u ? backend::thread : N <= 64u ? backend::warp : backend::block; + else return N <= 6u ? backend::thread : backend::warp; case op::gemm: - if (!f64) return N <= 8u ? backend::warp : N <= 12u ? backend::block : N <= 16u ? backend::warp : N <= 24u ? backend::block : N <= 32u ? backend::nvidia : backend::block; + if (!f64) return N <= 16u ? backend::warp : N <= 24u ? backend::block : N <= 32u ? backend::nvidia_block : backend::block; else return N <= 8u ? backend::warp : backend::block; - case op::chol: - if (!f64) return N <= 6u ? backend::thread : N <= 24u ? backend::warp : backend::nvidia; + case op::potrf: + if (!f64) return N <= 4u ? backend::thread : N <= 8u ? backend::nvidia_thread : N <= 24u ? backend::warp : backend::nvidia_block; + else return N <= 8u ? backend::nvidia_thread : N <= 24u ? backend::thread : backend::block; + case op::trsv: + if (!f64) return N <= 16u ? backend::thread : N <= 24u ? backend::nvidia_thread : N <= 32u ? backend::nvidia_block : backend::warp; + else return N <= 6u ? backend::thread : N <= 32u ? backend::nvidia_thread : N <= 48u ? backend::nvidia_block : backend::warp; + case op::posv: + if (!f64) return N <= 12u ? backend::thread : backend::nvidia_block; + else return N <= 8u ? backend::nvidia_thread : N <= 24u ? backend::thread : N <= 32u ? backend::nvidia_block : backend::block; + } + return backend::block; +} + +constexpr backend native_sm120(op o, uint32_t N, bool f64) { + switch (o) { + case op::dot: + if (!f64) return N <= 12u ? backend::thread : N <= 16u ? backend::warp : N <= 24u ? backend::thread : backend::warp; + else return N <= 32u ? backend::thread : backend::warp; + case op::gemv: + if (!f64) return N <= 6u ? backend::thread : N <= 32u ? backend::warp : N <= 48u ? backend::block : backend::warp; + else return N <= 6u ? backend::thread : backend::warp; + case op::gemm: + if (!f64) return N <= 16u ? backend::warp : backend::block; + else return N <= 8u ? backend::warp : backend::block; + case op::potrf: + if (!f64) return N <= 6u ? backend::thread : N <= 48u ? backend::warp : backend::block; else return N <= 24u ? backend::thread : backend::block; case op::trsv: - if (!f64) return N <= 16u ? backend::thread : N <= 32u ? backend::nvidia : backend::warp; - else return N <= 16u ? backend::thread : N <= 48u ? backend::nvidia : N <= 64u ? backend::block : backend::warp; + if (!f64) return N <= 16u ? backend::thread : backend::warp; + else return N <= 24u ? backend::thread : N <= 32u ? backend::block : backend::warp; case op::posv: - if (!f64) return N <= 12u ? backend::thread : backend::nvidia; - else return N <= 24u ? backend::thread : N <= 32u ? backend::nvidia : backend::block; + if (!f64) return N <= 12u ? backend::thread : N <= 64u ? backend::warp : backend::block; + else return N <= 24u ? backend::thread : backend::block; } return backend::block; } // === END tune.py ladder sm_120 === // === BEGIN tune.py ladder sm_87 === -// Source sweep: mega_sweep_50W_merged.txt tie margin: ±5% (nvidia must clear it; SIMT ties ±2% prefer thread>warp>block) -// Returns the *ideal* tier assuming nvidia is linked; nv_available() filters after. +// Source sweep: mega_sweep_orin_tegra_20260830_035819.txt tie margin: ±5% (NVIDIA block/thread must clear it; SIMT ties ±2% prefer thread>warp>block) +// NVIDIA-thread valid-input veto: nvt_valid_sm87_20260830_160506.txt (4 ladder picks vetoed) +// Paired tables preserve the measured native runner-up for callers that +// do not opt into MathDx; both use the same capture and SIMT tie rule. constexpr backend ideal_sm87(op o, uint32_t N, bool f64) { switch (o) { case op::dot: if (!f64) return N <= 24u ? backend::thread : backend::warp; else return N <= 64u ? backend::thread : backend::warp; case op::gemv: - if (!f64) return N <= 6u ? backend::thread : N <= 32u ? backend::warp : N <= 48u ? backend::nvidia : backend::warp; + if (!f64) return N <= 6u ? backend::thread : N <= 32u ? backend::warp : N <= 48u ? backend::nvidia_block : backend::warp; else return N <= 12u ? backend::thread : backend::warp; case op::gemm: - if (!f64) return N <= 16u ? backend::warp : N <= 96u ? backend::nvidia : backend::block; + if (!f64) return N <= 16u ? backend::warp : N <= 96u ? backend::nvidia_block : backend::block; else return N <= 96u ? backend::warp : backend::block; - case op::chol: - if (!f64) return N <= 12u ? backend::thread : backend::nvidia; - else return N <= 48u ? backend::thread : N <= 64u ? backend::nvidia : backend::block; + case op::potrf: + if (!f64) return N <= 6u ? backend::thread : N <= 12u ? backend::nvidia_thread : backend::nvidia_block; + else return N <= 8u ? backend::nvidia_thread : N <= 48u ? backend::thread : N <= 64u ? backend::block : N <= 96u ? backend::warp : backend::block; case op::trsv: - if (!f64) return N <= 16u ? backend::thread : N <= 32u ? backend::nvidia : backend::warp; - else return N <= 16u ? backend::thread : N <= 32u ? backend::nvidia : N <= 64u ? backend::thread : N <= 96u ? backend::warp : backend::block; + if (!f64) return N <= 12u ? backend::thread : N <= 32u ? backend::nvidia_thread : backend::warp; + else return N <= 32u ? backend::nvidia_thread : N <= 64u ? backend::thread : N <= 96u ? backend::warp : backend::block; case op::posv: - if (!f64) return N <= 16u ? backend::thread : backend::nvidia; - else return N <= 64u ? backend::thread : backend::block; + if (!f64) return N <= 16u ? backend::thread : backend::nvidia_block; + else return N <= 64u ? backend::thread : N <= 96u ? backend::warp : backend::block; + } + return backend::block; +} + +constexpr backend native_sm87(op o, uint32_t N, bool f64) { + switch (o) { + case op::dot: + if (!f64) return N <= 24u ? backend::thread : backend::warp; + else return N <= 64u ? backend::thread : backend::warp; + case op::gemv: + if (!f64) return N <= 6u ? backend::thread : backend::warp; + else return N <= 12u ? backend::thread : backend::warp; + case op::gemm: + if (!f64) return N <= 32u ? backend::warp : backend::block; + else return N <= 96u ? backend::warp : backend::block; + case op::potrf: + if (!f64) return N <= 8u ? backend::thread : N <= 64u ? backend::warp : backend::block; + else return N <= 48u ? backend::thread : N <= 64u ? backend::block : N <= 96u ? backend::warp : backend::block; + case op::trsv: + if (!f64) return N <= 16u ? backend::thread : backend::warp; + else return N <= 64u ? backend::thread : N <= 96u ? backend::warp : backend::block; + case op::posv: + if (!f64) return N <= 24u ? backend::thread : N <= 96u ? backend::warp : backend::block; + else return N <= 64u ? backend::thread : N <= 96u ? backend::warp : backend::block; } return backend::block; } // === END tune.py ladder sm_87 === -// ─── blas2 family (syrk / syr2k / ldlt / ldltsv): warp-vs-block only — no -// vendor tier exists for these ops (nv_available() is already false for them). +// ─── blas2 family (syrk / syr2k / ldlt / ldlt_solve): warp-vs-block only; +// no vendor tier exists for these ops. // tune.py's blas2 leg owns the marker blocks; unmeasured arches stay block // (the always-correct incumbent). inv/trmv/ger are single-impl (block-only) // and deliberately have no table — measured and reported, never picked. ─── @@ -149,7 +193,7 @@ constexpr backend blas2_sm120(op o, uint32_t N, bool f64) { case op::ldlt: if (!f64) return N <= 64u ? backend::warp : backend::block; else return backend::block; - case op::ldltsv: + case op::ldlt_solve: if (!f64) return N <= 64u ? backend::warp : backend::block; else return backend::block; } @@ -158,7 +202,7 @@ constexpr backend blas2_sm120(op o, uint32_t N, bool f64) { // === END tune.py blas2 sm_120 === constexpr bool is_blas2(op o) { - return o == op::syrk || o == op::syr2k || o == op::ldlt || o == op::ldltsv; + return o == op::syrk || o == op::syr2k || o == op::ldlt || o == op::ldlt_solve; } constexpr backend blas2_ideal(op o, uint32_t N, bool f64, uint32_t sm) { switch (sm) { @@ -194,22 +238,22 @@ constexpr backend rect_gemv_sm120(uint32_t M, uint32_t N, bool f64) { } return backend::block; } -constexpr backend rect_gemm_sm120(uint32_t M, uint32_t K, uint32_t N, bool f64) { +constexpr backend rect_gemm_sm120(uint32_t M, uint32_t N, uint32_t K, bool f64) { if (!f64) { - if (M == 6u && K == 6u && N == 64u) return backend::block; - if (M == 8u && K == 32u && N == 8u) return backend::warp; - if (M == 16u && K == 64u && N == 16u) return backend::block; - if (M == 32u && K == 8u && N == 32u) return backend::warp; - if (M == 64u && K == 6u && N == 6u) return backend::warp; - if (M == 64u && K == 16u && N == 16u) return backend::warp; + if (M == 6u && N == 64u && K == 6u) return backend::block; + if (M == 8u && N == 8u && K == 32u) return backend::warp; + if (M == 16u && N == 16u && K == 64u) return backend::block; + if (M == 32u && N == 32u && K == 8u) return backend::warp; + if (M == 64u && N == 6u && K == 6u) return backend::warp; + if (M == 64u && N == 16u && K == 16u) return backend::warp; } if (f64) { - if (M == 6u && K == 6u && N == 64u) return backend::block; - if (M == 8u && K == 32u && N == 8u) return backend::block; - if (M == 16u && K == 64u && N == 16u) return backend::block; - if (M == 32u && K == 8u && N == 32u) return backend::block; - if (M == 64u && K == 6u && N == 6u) return backend::warp; - if (M == 64u && K == 16u && N == 16u) return backend::block; + if (M == 6u && N == 64u && K == 6u) return backend::block; + if (M == 8u && N == 8u && K == 32u) return backend::block; + if (M == 16u && N == 16u && K == 64u) return backend::block; + if (M == 32u && N == 32u && K == 8u) return backend::block; + if (M == 64u && N == 6u && K == 6u) return backend::warp; + if (M == 64u && N == 16u && K == 16u) return backend::block; } return backend::block; } @@ -223,10 +267,10 @@ constexpr backend rect_gemv_ideal(uint32_t M, uint32_t N, bool f64, uint32_t sm) default: return backend::block; } } -constexpr backend rect_gemm_ideal(uint32_t M, uint32_t K, uint32_t N, bool f64, uint32_t sm) { +constexpr backend rect_gemm_ideal(uint32_t M, uint32_t N, uint32_t K, bool f64, uint32_t sm) { switch (sm) { // === BEGIN tune.py rect gemm dispatch === - case 1200u: return rect_gemm_sm120(M, K, N, f64); + case 1200u: return rect_gemm_sm120(M, N, K, f64); // === END tune.py rect gemm dispatch === default: return backend::block; } @@ -238,21 +282,21 @@ constexpr backend ideal_generic(op o, uint32_t N, bool /*f64*/) { switch (o) { case op::dot: return backend::warp; case op::gemv: return N <= 32 ? backend::warp : backend::block; - case op::gemm: return N <= 8 ? backend::warp : N <= 64 ? backend::nvidia : backend::block; - case op::chol: - case op::posv: return N <= 16 ? backend::warp : backend::nvidia; + case op::gemm: return N <= 8 ? backend::warp : N <= 64 ? backend::nvidia_block : backend::block; + case op::potrf: + case op::posv: return N <= 16 ? backend::warp : backend::nvidia_block; case op::trsv: return N <= 16 ? backend::warp : backend::block; } return backend::block; } -// Runner-up when the ideal pick is nvidia but nvidia isn't linked (warp/block only). -constexpr backend without_nvidia(op o, uint32_t N) { +// Conservative native fallback for an architecture without a measured table. +constexpr backend native_generic(op o, uint32_t N) { switch (o) { case op::dot: return backend::warp; case op::gemv: return N <= 32 ? backend::warp : backend::block; case op::gemm: return N <= 8 ? backend::warp : backend::block; - case op::chol: + case op::potrf: case op::posv: return N <= 32 ? backend::warp : backend::block; // crossover ~48 case op::trsv: return backend::warp; // warp wins w/o nvidia } @@ -260,64 +304,33 @@ constexpr backend without_nvidia(op o, uint32_t N) { } // Per-host override hook: a generated header (bench/autotune.py --emit-defaults) may -// `#define GLASS_DEFAULTS_HAVE_LOCAL` and provide `local_ideal(op,N,f64,sm)`. Point +// `#define GLASS_DEFAULTS_HAVE_LOCAL` and provide +// `local_ideal(op,N,f64,sm,allow_nvidia)`. Point // GLASS_DEFAULTS_TABLE_LOCAL at it to use your GPU's measured table instead of the seed. #ifdef GLASS_DEFAULTS_TABLE_LOCAL #include GLASS_DEFAULTS_TABLE_LOCAL #endif -constexpr backend ideal(op o, uint32_t N, bool f64, uint32_t sm) { +constexpr backend ideal(op o, uint32_t N, bool f64, uint32_t sm, + bool allow_nvidia = true) { + if (is_blas2(o)) return blas2_ideal(o, N, f64, sm); #ifdef GLASS_DEFAULTS_HAVE_LOCAL - return local_ideal(o, N, f64, sm); + return local_ideal(o, N, f64, sm, allow_nvidia); #else - if (is_blas2(o)) return blas2_ideal(o, N, f64, sm); switch (sm) { // === BEGIN tune.py ladder dispatch === - case 870u: return ideal_sm87(o, N, f64); - case 1200u: return ideal_sm120(o, N, f64); + case 870u: return allow_nvidia ? ideal_sm87(o, N, f64) : native_sm87(o, N, f64); + case 1200u: return allow_nvidia ? ideal_sm120(o, N, f64) : native_sm120(o, N, f64); // === END tune.py ladder dispatch === - default: return ideal_generic(o, N, f64); + default: return allow_nvidia ? ideal_generic(o, N, f64) + : native_generic(o, N); } #endif } -} // namespace defaults - -// ─── bare-namespace body dispatch ──────────────────────────────────────────── -// Moved to glass-dispatch.cuh (included above): the `body` enum and the -// tune.py-regenerated `dispatch_body()` table live there so glass.cuh's bare -// face can consume them without this header's vendor-macro include-order -// sensitivity. Determinism-sensitive consumers pin `glass::block::` explicitly. - -/// Suggested backend for (op, N, T) on `SM`. `nvidia` only when the vendor lib is linked. -template -constexpr backend suggested_backend() { - constexpr bool f64 = sizeof(T) == 8; - backend id = defaults::ideal(Op, N, f64, SM); - if (id == backend::nvidia && !defaults::nv_available(Op)) - return defaults::without_nvidia(Op, N); - return id; -} - -/// Rectangular gemv: measured per exact (M, N) shape by the rect leg; unmeasured -/// shapes (and unmeasured arches) return `block`. Never returns `nvidia`. -template -constexpr backend suggested_backend_rect_gemv() { - return defaults::rect_gemv_ideal(M, N, sizeof(T) == 8, SM); -} - -/// Rectangular gemm (C is MxN, contraction K): measured per exact (M, K, N) shape. -template -constexpr backend suggested_backend_rect_gemm() { - return defaults::rect_gemm_ideal(M, K, N, sizeof(T) == 8, SM); -} - -/// Suggested block thread count for the `block` backend: factor/solve want 32 (extra -/// threads idle on the serial pivot); gemm grows with N; dot/gemv 64–128. -template -constexpr uint32_t suggested_block_threads() { - switch (Op) { - case op::chol: case op::trsv: case op::posv: return 32u; +constexpr uint32_t native_block_threads(op o, uint32_t N) { + switch (o) { + case op::potrf: case op::trsv: case op::posv: return 32u; case op::gemm: return N <= 8 ? 64u : N <= 16 ? 128u : 256u; case op::dot: return 64u; case op::gemv: return N <= 16 ? 64u : 128u; @@ -325,29 +338,78 @@ constexpr uint32_t suggested_block_threads() { return 64u; } -/// Suggested warps-per-block for the `warp` backend (intra-block problem packing). -template -constexpr uint32_t suggested_warps_per_block() { - return Op == op::dot ? 8u : 2u; // dot packs more (8–16); others 2–4 +constexpr uint32_t native_warps_per_block(op o) { + return o == op::dot ? 8u : 2u; } -/// Suggested threads-per-block for the `thread` backend: launch `<<>>`, -/// one problem per THREAD. Shrinks as N grows — the inverse of -/// `suggested_block_threads`: there, extra threads split ONE problem and idle on the -/// serial pivot; here every thread owns a whole problem, so the binding constraint is -/// the per-thread register footprint (~N*N live for a factor/solve; measured ceiling N<=7 -/// — see CLAUDE.md), and a smaller -/// block keeps occupancy up. Seed heuristic, NOT measured — `bench/tune.py`'s ladder -/// leg does not tune this knob (it sweeps TPB but only records the winning tier). -template -constexpr uint32_t suggested_threads_per_block() { - switch (Op) { - case op::chol: case op::posv: case op::trsv: case op::gemm: - return N <= 4 ? 128u : N <= 6 ? 64u : 32u; // N*N registers per thread +constexpr uint32_t native_threads_per_block(op o, uint32_t N) { + switch (o) { + case op::potrf: case op::posv: case op::trsv: case op::gemm: + return N <= 4 ? 128u : N <= 6 ? 64u : 32u; case op::dot: case op::gemv: - return 128u; // ~N live registers, pack hard + return 128u; } return 64u; } +constexpr execution_plan make_plan(backend id, op o, uint32_t N) { + switch (id) { + case backend::thread: { + const uint32_t t = native_threads_per_block(o, N); + return {family::native, scope::thread, t, t, 0u}; + } + case backend::warp: { + const uint32_t w = native_warps_per_block(o); + return {family::native, scope::warp, 32u * w, w, 0u}; + } + case backend::nvidia_thread: { + const uint32_t t = native_threads_per_block(o, N); + return {family::nvidia, scope::thread, t, t, 0u}; + } + case backend::nvidia_block: + return {family::nvidia, scope::block, + execution_plan::dynamic_requirement, 1u, + execution_plan::dynamic_requirement}; + case backend::block: + default: + return {family::native, scope::block, + native_block_threads(o, N), 1u, 0u}; + } +} + +} // namespace defaults + +/** + * @brief Recommend a measured placement and a legal launch plan. + * + * Square ladder operations take one dimension. Rectangular GEMV takes M,N; + * rectangular GEMM takes the conventional M,N,K order. `native_only` is the + * safe default and never depends on header include order; pass `mathdx` + * explicitly to admit NVIDIA block/thread candidates. + */ +template +GLASS_DISPATCH_HD constexpr execution_plan recommend( + dependency_set dependencies = dependency_set::native_only, + uint32_t sm = GLASS_TARGET_SM) { + static_assert(sizeof...(Dims) >= 1u, "recommend requires an operation shape"); + constexpr uint32_t d[] = {Dims...}; + constexpr bool is_gemm = Op == op::gemm; + constexpr bool is_gemv = Op == op::gemv; + static_assert((is_gemm && (sizeof...(Dims) == 1u || sizeof...(Dims) == 3u)) || + (is_gemv && (sizeof...(Dims) == 1u || sizeof...(Dims) == 2u)) || + ((!is_gemm && !is_gemv) && sizeof...(Dims) == 1u), + "recommend shape arity does not match the operation"); + + defaults::backend id = defaults::backend::block; + if constexpr (is_gemm && sizeof...(Dims) == 3u) { + id = defaults::rect_gemm_ideal(d[0], d[1], d[2], sizeof(T) == 8u, sm); + } else if constexpr (is_gemv && sizeof...(Dims) == 2u) { + id = defaults::rect_gemv_ideal(d[0], d[1], sizeof(T) == 8u, sm); + } else { + id = defaults::ideal(Op, d[0], sizeof(T) == 8u, sm, + dependencies == dependency_set::mathdx); + } + return defaults::make_plan(id, Op, d[0]); +} + } // namespace glass diff --git a/glass-dispatch.cuh b/glass-dispatch.cuh index 29e70a6..a076382 100644 --- a/glass-dispatch.cuh +++ b/glass-dispatch.cuh @@ -6,7 +6,8 @@ * for each (op, N, dtype) cell of the bare `glass::op` face. * * NAMESPACE CONTRACT (2026-07-30 restructure): explicit namespaces - * (`glass::block::`, `glass::warp::`, `glass::thread::`, `glass::nvidia::*`) + * (`glass::block::`, `glass::warp::`, `glass::thread::`, + * `glass::nvidia::{block,warp,thread}::`) * are the CONTRACT tier — bit-exact, never re-dispatched. The BARE `glass::op` * face keeps a block-scope CALLING contract (launch one block per problem, * any thread count) but its body is chosen from this measured table: a @@ -32,23 +33,32 @@ #define GLASS_DISPATCH_HD #endif -// SM the tables are keyed on: the build's SMS (GRiD-style builds) else the -// measured sm_120. (Historically lived in glass-defaults.cuh; shared now.) -#ifndef GLASS_DEFAULTS_SM +// One architecture selector for dispatch, advisors, and MathDx descriptors. +// Build systems should define GLASS_TARGET_SM (e.g. 1200 for sm_120). Legacy +// SMS remains an input alias during the source migration. An unspecified +// target uses the measured sm_120 seed table, matching prior GLASS releases. +#ifndef GLASS_TARGET_SM #ifdef SMS - #define GLASS_DEFAULTS_SM (SMS) + #define GLASS_TARGET_SM SMS #else - #define GLASS_DEFAULTS_SM (1200u) + #define GLASS_TARGET_SM 1200u #endif #endif +// MathDx descriptor templates historically consume SMS. Define it once from +// the same selector so advisors, native dispatch, and vendor descriptors can +// no longer silently target different architectures. +#ifndef SMS + #define SMS GLASS_TARGET_SM +#endif + namespace glass { // APPEND-ONLY (ordinals are load-bearing for the per-arch ladder tables in // glass-defaults.cuh): the six ladder ops first, then the body-sweep additions, // then the blas2 family (warp-vs-block only; measured by tune.py's blas2 leg). -enum class op : int { dot, gemv, gemm, chol, trsv, posv, eig3, softmax, - syrk, syr2k, ldlt, ldltsv }; +enum class op : int { dot, gemv, gemm, potrf, trsv, posv, eig3, softmax, + syrk, syr2k, ldlt, ldlt_solve }; // The bare face's implementation bodies under the fixed block-scope contract. // `warp_in_block` / `thread_in_block` = the op's warp/thread twin executed by @@ -69,7 +79,7 @@ GLASS_DISPATCH_HD constexpr body body_sm120(op o, uint32_t N, bool f64) { if (!f64) return N <= 16u ? body::block : N <= 32u ? body::warp_in_block : body::block; else return N <= 4u ? body::block : N <= 8u ? body::warp_in_block : N <= 16u ? body::block : N <= 32u ? body::warp_in_block : body::block; case op::gemm: return body::block; - case op::chol: + case op::potrf: if (!f64) return N <= 4u ? body::thread_in_block : body::block; else return body::block; case op::trsv: @@ -104,7 +114,7 @@ GLASS_DISPATCH_HD constexpr body body_sm87(op o, uint32_t N, bool f64) { case op::gemm: if (!f64) return N <= 4u ? body::warp_in_block : body::block; else return body::block; - case op::chol: return body::block; + case op::potrf: return body::block; case op::trsv: if (!f64) return N <= 4u ? body::thread_in_block : N <= 16u ? body::warp_in_block : body::block; else return N <= 8u ? body::block : N <= 16u ? body::warp_in_block : body::block; @@ -126,7 +136,7 @@ GLASS_DISPATCH_HD constexpr body body_sm87(op o, uint32_t N, bool f64) { // === BEGIN tune.py body dispatch === // Bodies for the bare block-scope face; unmeasured arches stay block. GLASS_DISPATCH_HD constexpr body dispatch_body(op o, uint32_t N, bool f64, - uint32_t sm = GLASS_DEFAULTS_SM) { + uint32_t sm = GLASS_TARGET_SM) { switch (sm) { case 870u: return body_sm87(o, N, f64); case 1200u: return body_sm120(o, N, f64); diff --git a/glass-nvidia.cuh b/glass-nvidia.cuh index 8b5af55..5324279 100644 --- a/glass-nvidia.cuh +++ b/glass-nvidia.cuh @@ -1,7 +1,7 @@ #pragma once /** * @file glass-nvidia.cuh - * @brief Umbrella header for the `glass::nvidia::` backend (CUB / cuBLASDx / cuSOLVERDx). + * @brief Umbrella header for explicit `glass::nvidia::{block,warp,thread}` backends. * * Include this (instead of, or in addition to, glass.cuh) to access the * vendor-accelerated single-block linear-algebra paths. It pulls in: @@ -15,13 +15,16 @@ * - L2 (l2.cuh) cuBLASDx-backed gemv + DEFINE_NVIDIA_GEMV* macros. * - L3 (l3.cuh) cuBLASDx-backed gemm / gemm_batched / row_strided_*. * - query.cuh Host-side constexpr BlockDim query API. - * - LAPACK (lapack.cuh) cuSOLVERDx chol/trsm/posv/getrf/gesv/geqrf/gels. + * - LAPACK (lapack.cuh) cuSOLVERDx block-scope + * chol/trsm/posv/getrf/gesv/geqrf/gels. + * - LAPACK thread cuSOLVERDx 0.4+ thread-scope versions of the same + * operations under `glass::nvidia::thread::`. * * The L2/L3/LAPACK wrappers gate themselves on GLASS_HAVE_CUBLASDX / * GLASS_HAVE_CUSOLVERDX, auto-detected from include order. Set MATHDX_ROOT and * define GLASS_BENCH_CUBLASDX / GLASS_BENCH_CUSOLVERDX to force-enable them. The - * `glass::nvidia::*` primary templates auto-dispatch between pure-SIMT and the - * vendor backend at compile time via the size heuristic / tuning table. + * `glass::nvidia::block::*` primary templates auto-dispatch between pure-SIMT + * and the vendor backend at compile time via the size heuristic / tuning table. */ #include "glass.cuh" @@ -42,6 +45,7 @@ #else #define GLASS_HAVE_CUBLASDX 0 #endif + #endif // cuSOLVERDx detection (for L3 LAPACK wrappers: potrf, trsm). @@ -61,6 +65,12 @@ #endif #endif +#if GLASS_HAVE_CUSOLVERDX && defined(CUSOLVERDX_VERSION) && CUSOLVERDX_VERSION >= 400 +#define GLASS_HAVE_CUSOLVERDX_THREAD 1 +#else +#define GLASS_HAVE_CUSOLVERDX_THREAD 0 +#endif + // types.cuh defines `glass::nvidia::layout` and the shared helper macros // (_GLASS_CUBLAS_LAYOUT, _GLASS_ASSERT_BLOCKDIM_GEQ). It must be included // before any of l1/l2/l3/lapack so the `layout` enum is in scope inside the @@ -132,7 +142,7 @@ namespace block { // but these aliases make consumer code self-documenting: // // constexpr std::size_t smem = - // glass::nvidia::required_smem_for_dispatch_gemm(); + // glass::nvidia::block::required_smem_for_dispatch_gemm(); // __shared__ char buf[smem]; // 0 bytes if the call SIMT-routes // // Codegen that accumulates scratch across many call sites can take @@ -257,14 +267,11 @@ namespace block { } // namespace block -/* Bare glass::nvidia:: face — same contract as the bare glass:: face - (glass.cuh): the block-scope vendor surface re-exported, so existing - glass::nvidia::op spellings resolve to the SAME entities as - glass::nvidia::block::op. The warp-scope vendor forms (cub::WarpReduce) - live in their own sub-namespace below, included at nvidia:: scope so the - spelling is glass::nvidia::warp:: (a warp tier is not a block-scope - body, so it does NOT nest under block::). */ -using namespace block; +#if GLASS_HAVE_CUSOLVERDX_THREAD +// One independent packed problem per CUDA thread; no shared scratch or +// block-wide synchronization. +#include "./src/nvidia/lapack_thread.cuh" +#endif // warp-scope CUB reductions: glass::nvidia::warp::{reduce, dot, nrm2} #include "./src/nvidia/l1_warp.cuh" diff --git a/glass.cuh b/glass.cuh index cab801e..f4b0bb9 100644 --- a/glass.cuh +++ b/glass.cuh @@ -28,7 +28,7 @@ * Include glass-cgrps.cuh for the cooperative-groups variants, or * glass-nvidia.cuh for the CUB / cuBLASDx / cuSOLVERDx-accelerated paths * (`glass::nvidia::block::` / `glass::nvidia::warp::`, with the same - * bare-name re-export inside `glass::nvidia::`). Also defines the host + * explicit-scope NVIDIA namespaces). Also defines the host * helper ::glass_gemm_dispatch_smem below. */ // Pre-include system headers at global scope so they are not pulled into the diff --git a/src/base/L3/gemm_reduced.cuh b/src/base/L3/gemm_reduced.cuh index 60e06ad..a11e868 100644 --- a/src/base/L3/gemm_reduced.cuh +++ b/src/base/L3/gemm_reduced.cuh @@ -12,8 +12,8 @@ // This is a thread-utilization experiment, NOT a FLOP reduction — total MAC // work is identical. The 2026-08-14 sm_120 sweep found two f64-only wins among // 96 cells, both at one 4x4x64 shape; no f32 cell won. Because the existing -// picker is dtype-independent, suggested_use_reduced() remains conservatively -// false everywhere. See bench/RESULTS.md for the dated measurement. +// measured default remains the standard algorithm everywhere. The explicit +// `*_reduced` operations remain available for controlled experiments. // // Thread-count invariance: each output is reduced by the SAME fixed 32-way tree // regardless of how many warps the block has, so results are bit-identical at @@ -26,29 +26,6 @@ // lane-0 rounding bit-for-bit) lives in L1/reduce.cuh so every L2/L3 *_reduced // engine can share it. The sub-warp fallback below uses it for invariance. -/** - * @brief Should a contraction-parallel `*_reduced` op be preferred over the serial one? - * - * Codegen / launch-time picker seeded by the measured crossover sweep - * (`bench/RESULTS.md`, reduced section). The quiet-GPU sm_120 sweep of - * 2026-08-14 found no f32 win in 48 cells and two f64 wins in 48 cells, both - * for `4x4x64` with 128 or 256 threads. That is too narrow and dtype-specific - * for this picker: its public parameters describe shape and launch, not scalar - * type. It returns `false` rather than silently selecting a path that regresses - * f32. A future dtype-aware picker can promote a repeatable region without - * changing the explicit `*_reduced` operations. `constexpr` lets - * `if constexpr` call sites fold with zero cost. - * - * @tparam n_out Output element count (e.g. M*K for gemm, M for gemv). - * @tparam K_contract Length of the contracted dimension. - * @tparam blockDim Launch thread count. - * @return true to use the `*_reduced` variant, false to use the serial op. - */ -template -__host__ __device__ constexpr bool suggested_use_reduced() { - return false; // sm_120 2026-08-14: f32 0/48; f64 2/48 at one shape; no dtype parameter -} - // Core: explicit (rank,size), compile-time dims + standard-BLAS layout flags // (C is M×N, contraction K; op(A) M×K, op(B) K×N — see gemm.cuh). HAS_BETA // selects whether C is read (false ⇒ overwrite, never touches C). @@ -115,7 +92,7 @@ __device__ void gemm_reduced_impl_ct(uint32_t rank, uint32_t size, * split the inner sum (combined with a single warp-shuffle reduce) instead of * one thread summing serially. A utilization win when the output count is * smaller than the block — see :doc:`../../user_guide/concepts/contraction_parallel` - * and `glass::suggested_use_reduced`. Total MAC work is unchanged. + * and `glass::recommend`. Total MAC work is unchanged. * * Thread-count invariant: bit-identical at any block size (a trailing partial * warp idles; below 32 threads a register path reproduces the same rounding). diff --git a/src/base/L3/posv.cuh b/src/base/L3/posv.cuh index 31cc09f..2d7ac17 100644 --- a/src/base/L3/posv.cuh +++ b/src/base/L3/posv.cuh @@ -8,7 +8,7 @@ * `posv` / `potrs` are thin single-block compositions of `potrf` * (`potrf.cuh`) and `trsv` (`trsv.cuh`). Both callees end with a trailing * `__syncthreads()`, so the factor and the two solves compose with NO inter-call - * barrier. Pure-SIMT companion to `glass::nvidia::posv`. Column-major throughout. + * barrier. Pure-SIMT companion to `glass::nvidia::block::posv`. Column-major throughout. * * NOTE: `glass::warp::posv` is NOT in this file — it lives in `trsm.cuh`, * after the `warp::potrf`/`warp::trsm` definitions it composes. diff --git a/src/base/dispatch.cuh b/src/base/dispatch.cuh index 201dc51..03c830d 100644 --- a/src/base/dispatch.cuh +++ b/src/base/dispatch.cuh @@ -176,7 +176,7 @@ __device__ void potrf(uint32_t dimA, uint32_t dimB, uint32_t dimC, uint32_t MAX_ template __device__ void potrf(T *s_A, int *s_fail = nullptr) { constexpr body b = CHECK ? body::block - : dispatch_body(op::chol, N, sizeof(T) == 8); + : dispatch_body(op::potrf, N, sizeof(T) == 8); if constexpr (b == body::warp_in_block) { if (dispatch_detail::full_first_warp()) { dispatch_detail::warp0([&] { warp::potrf(s_A, s_fail); }); diff --git a/src/nvidia/l1.cuh b/src/nvidia/l1.cuh index 39d83e4..a05198b 100644 --- a/src/nvidia/l1.cuh +++ b/src/nvidia/l1.cuh @@ -20,8 +20,8 @@ // // Example: // extern __shared__ float scratch[]; // must be >= sizeof(T) * THREADS -// glass::nvidia::reduce(x, scratch); // default sync -// glass::nvidia::reduce(...); // fused +// glass::nvidia::block::reduce(x, scratch); // default sync +// glass::nvidia::block::reduce(...); // fused // Debug-only check that the launched blockDim.x matches CUB's THREADS template // arg. Mismatch (in either direction) silently corrupts the BlockReduce result. @@ -146,4 +146,3 @@ inline constexpr std::size_t reduce_scratch_bytes() { return sizeof(typename cub::BlockReduce::TempStorage); } - diff --git a/src/nvidia/l2.cuh b/src/nvidia/l2.cuh index 0e9e361..cf2407c 100644 --- a/src/nvidia/l2.cuh +++ b/src/nvidia/l2.cuh @@ -9,7 +9,7 @@ // // All sizes are compile-time. Call one of the DEFINE_NVIDIA_GEMV* macros once // per (M, N, BLOCK_THREADS, layouts, SM) combination you need, then call -// glass::nvidia::gemv<...>(alpha, A, x, beta, y, smem) inside your kernel. +// glass::nvidia::block::gemv<...>(alpha, A, x, beta, y, smem) inside your kernel. // // Backward-compatible defaults: // BLOCK_THREADS = 0 -> let cuBLASDx pick block_dim from its database @@ -18,24 +18,20 @@ // // Example (basic): // DEFINE_NVIDIA_GEMV(6, 6) -// constexpr auto smem = glass::nvidia::gemv_scratch_bytes(); -// constexpr auto threads = glass::nvidia::gemv_threads(); +// constexpr auto smem = glass::nvidia::block::gemv_scratch_bytes(); +// constexpr auto threads = glass::nvidia::block::gemv_threads(); // kernel<<<1, threads, smem>>>(...); -// glass::nvidia::gemv(1.f, A, x, 0.f, y, smem_ptr); +// glass::nvidia::block::gemv(1.f, A, x, 0.f, y, smem_ptr); // // Example (caller-controlled BlockDim): // DEFINE_NVIDIA_GEMV_BLOCKDIM(6, 6, 352) // kernel<<<1, 352, smem>>>(...); -// glass::nvidia::gemv(1.f, A, x, 0.f, y, smem_ptr); - -#ifndef SMS -#define SMS 860 -#endif +// glass::nvidia::block::gemv(1.f, A, x, 0.f, y, smem_ptr); // --------------------------------------------------------------------------- // Primary templates — instantiated by the DEFINE_NVIDIA_GEMV* macros below. // -// AUTO-DISPATCH: like glass::nvidia::gemm<>, the gemv<> primary template now +// AUTO-DISPATCH: like glass::nvidia::block::gemm<>, the gemv<> primary template now // consults should_use_cublasdx_gemv(): // - returns false → routes to ::glass::gemv // (SIMT, no scratch). Layout LA maps to SIMT's ROW_MAJOR @@ -85,7 +81,7 @@ __device__ void gemv(T alpha, T* A, T* x, T beta, T* y, char* smem) alpha, A, x, beta, y); } else { static_assert(sizeof(T) == 0, - "glass::nvidia::gemv: " + "glass::nvidia::block::gemv: " "should_use_cublasdx_gemv<> returned true for this shape but no " "DEFINE_NVIDIA_GEMV* macro is in scope. Add one in your .cu, or " "override the dispatch via tuning_table.cuh / GLASS_TUNING_TABLE_LOCAL."); @@ -358,7 +354,7 @@ constexpr uint32_t gemv_threads() { return 256; } // --------------------------------------------------------------------------- // gemv_strided: packs strided A into compact shared scratch, then delegates -// to the standard nvidia::gemv<...>. Forwards all template parameters +// to the standard nvidia::block::gemv<...>. Forwards all template parameters // (BLOCK_THREADS, layouts, SM) to the inner call. // // smem layout: [A_compact: M*N*sizeof(T)] [cuBLASDx smem for gemv<...>] diff --git a/src/nvidia/l3.cuh b/src/nvidia/l3.cuh index bd666e1..08659cb 100644 --- a/src/nvidia/l3.cuh +++ b/src/nvidia/l3.cuh @@ -9,7 +9,7 @@ // // All sizes are compile-time. Call one of the DEFINE_NVIDIA_GEMM* macros once per // (M, N, K, BLOCK_THREADS, layouts, SM) combination you need, then call -// glass::nvidia::gemm<...>(alpha, A, B, beta, C, smem) inside your kernel. +// glass::nvidia::block::gemm<...>(alpha, A, B, beta, C, smem) inside your kernel. // // Backward-compatible defaults: // BLOCK_THREADS = 0 -> let cuBLASDx pick block_dim from its database @@ -18,20 +18,20 @@ // // Example (basic): // DEFINE_NVIDIA_GEMM(6, 6, 6) -// constexpr auto smem = glass::nvidia::gemm_scratch_bytes(); -// constexpr auto threads = glass::nvidia::gemm_threads(); +// constexpr auto smem = glass::nvidia::block::gemm_scratch_bytes(); +// constexpr auto threads = glass::nvidia::block::gemm_threads(); // kernel<<<1, threads, smem>>>(...); -// glass::nvidia::gemm(1.f, A, B, 0.f, C, smem_ptr); +// glass::nvidia::block::gemm(1.f, A, B, 0.f, C, smem_ptr); // // Example (caller-controlled BlockDim — fixes the deadlock when launching with // a thread count not chosen by cuBLASDx's database): // DEFINE_NVIDIA_GEMM_BLOCKDIM(6, 6, 6, 352) // kernel<<<1, 352, smem>>>(...); -// glass::nvidia::gemm(1.f, A, B, 0.f, C, smem_ptr); +// glass::nvidia::block::gemm(1.f, A, B, 0.f, C, smem_ptr); // // Example (transpose B — A * B^T): // DEFINE_NVIDIA_GEMM_BLOCKDIM_TRANSB(6, 6, 6, 352) -// glass::nvidia::gemm(...); @@ -39,7 +39,7 @@ // Example (multi-arch dispatch with explicit SM): // DEFINE_NVIDIA_GEMM_BLOCKDIM_SM(6, 6, 6, 352, 890) // DEFINE_NVIDIA_GEMM_BLOCKDIM_SM(6, 6, 6, 352, 1200) -// glass::nvidia::gemm(...); -#ifndef SMS -#define SMS 860 -#endif - // --------------------------------------------------------------------------- // Primary templates — instantiated by the DEFINE_NVIDIA_GEMM* macros below. // @@ -67,7 +63,7 @@ // directing the user to call DEFINE_NVIDIA_GEMM*. The cuBLASDx // specialization the macro emits will override this primary body. // -// Net effect: callers can always write `glass::nvidia::gemm(...)`. +// Net effect: callers can always write `glass::nvidia::block::gemm(...)`. // Small shapes "just work" via SIMT; large shapes guide you to the macro. // // To force a particular backend regardless of the heuristic: @@ -130,7 +126,7 @@ __device__ void gemm(T alpha, T* A, T* B, T beta, T* C, char* smem) alpha, A, B, beta, C); } else { static_assert(sizeof(T) == 0, - "glass::nvidia::gemm is not " + "glass::nvidia::block::gemm is not " "available — should_use_cublasdx<> says cuBLASDx wins for this " "shape, so add a DEFINE_NVIDIA_GEMM* macro in your .cu file. " "(See the Batched-1D concept guide in docs and bench/autotune.py.)"); @@ -443,7 +439,7 @@ constexpr uint32_t gemm_threads() { return 256; } // --------------------------------------------------------------------------- // gemm_strided: packs strided A and B into compact shared scratch, then -// delegates to the standard nvidia::gemm<...>. Forwards all template parameters +// delegates to the standard nvidia::block::gemm<...>. Forwards all template parameters // (BLOCK_THREADS, layouts, SM) to the inner call so any DEFINE_NVIDIA_GEMM* // variant works underneath. // @@ -567,7 +563,7 @@ constexpr std::size_t gemm_strided_scratch_bytes() // { base + 0*M*N, base + 1*M*N, ..., base + (BATCH-1)*M*N }. // // Required launch: kernel<<>> -// Required smem: glass::nvidia::gemm_batched_scratch_bytes() +// Required smem: glass::nvidia::block::gemm_batched_scratch_bytes() // --------------------------------------------------------------------------- /** @@ -609,7 +605,7 @@ __device__ void gemm_batched(T alpha, T* const* A, T* const* B, T beta, T* const* C, char* smem) { static_assert(sizeof(T) == 0, - "glass::nvidia::gemm_batched not available — " + "glass::nvidia::block::gemm_batched not available — " "add DEFINE_NVIDIA_GEMM_BATCHED_BLOCKDIM(M,N,K,BATCH,TC) in your .cu file."); } @@ -692,7 +688,7 @@ constexpr uint32_t gemm_batched_threads() { return 256; } float beta, float* const* C, char* smem) \ { \ assert(blockDim.x >= per_batch_threads && blockDim.y >= BATCH && \ - "glass::nvidia::gemm_batched: launch dim3(>=TC, >=BATCH) required"); \ + "glass::nvidia::block::gemm_batched: launch dim3(>=TC, >=BATCH) required"); \ const uint32_t b = threadIdx.y; \ char* my_smem = smem + b * per_batch_smem; \ float* a = A[b]; \ diff --git a/src/nvidia/l3_simt.cuh b/src/nvidia/l3_simt.cuh index 3ea03cb..e31483f 100644 --- a/src/nvidia/l3_simt.cuh +++ b/src/nvidia/l3_simt.cuh @@ -76,11 +76,11 @@ template 0, "glass::nvidia::gemm_batched_1d: BATCH must be > 0"); - static_assert(TC > 0, "glass::nvidia::gemm_batched_1d: TC must be > 0"); + static_assert(BATCH > 0, "glass::nvidia::block::gemm_batched_1d: BATCH must be > 0"); + static_assert(TC > 0, "glass::nvidia::block::gemm_batched_1d: TC must be > 0"); #ifndef NDEBUG assert((blockDim.x * blockDim.y * blockDim.z) >= TC * BATCH && - "glass::nvidia::gemm_batched_1d: launched threads < TC*BATCH"); + "glass::nvidia::block::gemm_batched_1d: launched threads < TC*BATCH"); #endif constexpr bool RM_A = (LA == layout::row_major); constexpr bool RM_B = (LB == layout::row_major); @@ -189,11 +189,11 @@ template 0, "glass::nvidia::gemm_strided_batched_1d: BATCH must be > 0"); - static_assert(TC > 0, "glass::nvidia::gemm_strided_batched_1d: TC must be > 0"); + static_assert(BATCH > 0, "glass::nvidia::block::gemm_strided_batched_1d: BATCH must be > 0"); + static_assert(TC > 0, "glass::nvidia::block::gemm_strided_batched_1d: TC must be > 0"); #ifndef NDEBUG assert((blockDim.x * blockDim.y * blockDim.z) >= TC * BATCH && - "glass::nvidia::gemm_strided_batched_1d: launched threads < TC*BATCH"); + "glass::nvidia::block::gemm_strided_batched_1d: launched threads < TC*BATCH"); #endif constexpr bool RM_A = (LA == layout::row_major); constexpr bool RM_B = (LB == layout::row_major); diff --git a/src/nvidia/lapack.cuh b/src/nvidia/lapack.cuh index 3149331..7a13c96 100644 --- a/src/nvidia/lapack.cuh +++ b/src/nvidia/lapack.cuh @@ -1,7 +1,7 @@ #pragma once /** * @file lapack.cuh - * @brief cuSOLVERDx-backed single-block LAPACK wrappers for `glass::nvidia::`. + * @brief cuSOLVERDx-backed single-block LAPACK wrappers for `glass::nvidia::block::`. * * Block-level, compile-time-size factorizations and solves: Cholesky * (potrf), triangular solve (trsm), SPD solve (posv / potrs), unpivoted @@ -39,14 +39,10 @@ // // Example: // DEFINE_NVIDIA_CHOL_BLOCKDIM(7, 352) -// constexpr auto smem = glass::nvidia::potrf_scratch_bytes(); -// constexpr auto threads = glass::nvidia::potrf_threads(); +// constexpr auto smem = glass::nvidia::block::potrf_scratch_bytes(); +// constexpr auto threads = glass::nvidia::block::potrf_threads(); // kernel<<<1, threads, smem>>>(d_A); -// glass::nvidia::potrf(A, smem_ptr); - -#ifndef SMS -#define SMS 860 -#endif +// glass::nvidia::block::potrf(A, smem_ptr); // --------------------------------------------------------------------------- // Primary templates @@ -73,7 +69,7 @@ template not available — " + "glass::nvidia::block::potrf not available — " "add DEFINE_NVIDIA_CHOL* in your .cu file."); } @@ -117,7 +113,7 @@ template not available — " + "glass::nvidia::block::trsm not available — " "add DEFINE_NVIDIA_TRSM* in your .cu file."); } @@ -462,7 +458,7 @@ template not available — " + "glass::nvidia::block::posv not available — " "add DEFINE_NVIDIA_POSV* in your .cu file."); } @@ -616,7 +612,7 @@ template not available — " + "glass::nvidia::block::potrs not available — " "add DEFINE_NVIDIA_POTRS* in your .cu file."); } @@ -747,7 +743,7 @@ template not available — " + "glass::nvidia::block::getrf_no_pivot not available — " "add DEFINE_NVIDIA_GETRF* in your .cu file."); } @@ -874,7 +870,7 @@ template not available — " + "glass::nvidia::block::getrs_no_pivot not available — " "add DEFINE_NVIDIA_GETRS* in your .cu file."); } @@ -1007,7 +1003,7 @@ template not available — " + "glass::nvidia::block::gesv_no_pivot not available — " "add DEFINE_NVIDIA_GESV* in your .cu file."); } @@ -1157,7 +1153,7 @@ template not available — " + "glass::nvidia::block::geqrf not available — " "add DEFINE_NVIDIA_GEQRF* in your .cu file."); } @@ -1291,7 +1287,7 @@ template not available — " + "glass::nvidia::block::gels not available — " "add DEFINE_NVIDIA_GELS* in your .cu file."); } diff --git a/src/nvidia/lapack_thread.cuh b/src/nvidia/lapack_thread.cuh new file mode 100644 index 0000000..3693426 --- /dev/null +++ b/src/nvidia/lapack_thread.cuh @@ -0,0 +1,177 @@ +#pragma once +/** + * @file lapack_thread.cuh + * @brief cuSOLVERDx thread-execution LAPACK wrappers for + * `glass::nvidia::thread::`. + * + * Each calling CUDA thread owns one complete, compile-time-size problem. The + * operands may live in global, shared, or local memory; the wrappers allocate + * no dynamic shared memory and perform no block-wide synchronization. This + * makes the surface suitable for batches of small independent systems. + * + * The API mirrors the operations exposed by `glass::nvidia::block`, but omits + * block-only scratch, BlockDim, and trailing-sync parameters. All matrices are + * packed column-major. Requires cuSOLVERDx 0.4 or newer and the same MathDx + * device-link flags as the block backend. + */ +#include + +namespace thread { + +/** Factor an N-by-N SPD matrix in place as A = L*L^T. */ +template +__device__ inline void potrf(T* A) +{ + using solver = decltype( + cusolverdx::Size() + + cusolverdx::Precision() + + cusolverdx::Type() + + cusolverdx::Function() + + cusolverdx::FillMode() + + cusolverdx::Arrangement() + + cusolverdx::Thread() + + cusolverdx::SM()); + int info = 0; + solver().execute(A, &info); +} + +/** Solve L*X = alpha*B in place for a lower-triangular M-by-M L. */ +template +__device__ inline void trsm(T alpha, const T* L, T* B) +{ + for (uint32_t i = 0; i < M * N; ++i) { + B[i] *= alpha; + } + using solver = decltype( + cusolverdx::Size() + + cusolverdx::Precision() + + cusolverdx::Type() + + cusolverdx::Function() + + cusolverdx::Side() + + cusolverdx::FillMode() + + cusolverdx::TransposeMode() + + cusolverdx::Diag() + + cusolverdx::Arrangement() + + cusolverdx::Thread() + + cusolverdx::SM()); + solver().execute(L, B); +} + +/** Factor A and solve A*X = B in place for NRHS right-hand sides. */ +template +__device__ inline void posv(T* A, T* B) +{ + using solver = decltype( + cusolverdx::Size() + + cusolverdx::Precision() + + cusolverdx::Type() + + cusolverdx::Function() + + cusolverdx::FillMode() + + cusolverdx::Arrangement() + + cusolverdx::Thread() + + cusolverdx::SM()); + int info = 0; + solver().execute(A, B, &info); +} + +/** Solve L*L^T*X = B from a precomputed lower Cholesky factor. */ +template +__device__ inline void potrs(const T* L, T* B) +{ + using solver = decltype( + cusolverdx::Size() + + cusolverdx::Precision() + + cusolverdx::Type() + + cusolverdx::Function() + + cusolverdx::FillMode() + + cusolverdx::Arrangement() + + cusolverdx::Thread() + + cusolverdx::SM()); + solver().execute(L, B); +} + +/** Compute an unpivoted LU factorization in place. */ +template +__device__ inline void getrf_no_pivot(T* A) +{ + using solver = decltype( + cusolverdx::Size() + + cusolverdx::Precision() + + cusolverdx::Type() + + cusolverdx::Function() + + cusolverdx::Arrangement() + + cusolverdx::Thread() + + cusolverdx::SM()); + int info = 0; + solver().execute(A, &info); +} + +/** Solve A*X = B from a precomputed unpivoted LU factorization. */ +template +__device__ inline void getrs_no_pivot(const T* LU, T* B) +{ + using solver = decltype( + cusolverdx::Size() + + cusolverdx::Precision() + + cusolverdx::Type() + + cusolverdx::Function() + + cusolverdx::Arrangement() + + cusolverdx::Thread() + + cusolverdx::SM()); + solver().execute(LU, B); +} + +/** Factor A without pivoting and solve A*X = B in place. */ +template +__device__ inline void gesv_no_pivot(T* A, T* B) +{ + using solver = decltype( + cusolverdx::Size() + + cusolverdx::Precision() + + cusolverdx::Type() + + cusolverdx::Function() + + cusolverdx::Arrangement() + + cusolverdx::Thread() + + cusolverdx::SM()); + int info = 0; + solver().execute(A, B, &info); +} + +/** Compute a packed column-major M-by-N QR factorization in place. */ +template +__device__ inline void geqrf(T* A, T* tau) +{ + using solver = decltype( + cusolverdx::Size() + + cusolverdx::Precision() + + cusolverdx::Type() + + cusolverdx::Function() + + cusolverdx::Arrangement() + + cusolverdx::Thread() + + cusolverdx::SM()); + solver().execute(A, tau); +} + +/** Solve an M-by-N least-squares problem with NRHS right-hand sides. */ +template +__device__ inline void gels(T* A, T* tau, T* B) +{ + using solver = decltype( + cusolverdx::Size() + + cusolverdx::Precision() + + cusolverdx::Type() + + cusolverdx::Function() + + cusolverdx::Arrangement() + + cusolverdx::Thread() + + cusolverdx::SM()); + solver().execute(A, tau, B); +} + +} // namespace thread diff --git a/src/nvidia/query.cuh b/src/nvidia/query.cuh index d561a36..deed07e 100644 --- a/src/nvidia/query.cuh +++ b/src/nvidia/query.cuh @@ -13,14 +13,10 @@ // see query_simt.cuh (included unconditionally by glass-nvidia.cuh). // // Example: -// static_assert(glass::nvidia::min_block_threads() > 0); -// constexpr uint32_t TC = glass::nvidia::min_block_threads(); +// static_assert(glass::nvidia::block::min_block_threads() > 0); +// constexpr uint32_t TC = glass::nvidia::block::min_block_threads(); // // -> emit DEFINE_NVIDIA_GEMM_BLOCKDIM(6, 6, 6, TC) and launch with TC. -#ifndef SMS -#define SMS 860 -#endif - // -- gemm queries ----------------------------------------------------------- // Returns the natural block_dim product cuBLASDx picks for an (M,N,K,SM) GEMM @@ -128,4 +124,3 @@ constexpr bool gemv_block_threads_valid() { return BLOCK_THREADS >= gemv_min_block_threads(); } - diff --git a/src/nvidia/query_simt.cuh b/src/nvidia/query_simt.cuh index 4984c61..76526fa 100644 --- a/src/nvidia/query_simt.cuh +++ b/src/nvidia/query_simt.cuh @@ -8,10 +8,6 @@ // include in builds without the cuBLASDx headers. Companion to query.cuh // (which provides cuBLASDx-dependent helpers like gemm_min_block_threads). -#ifndef SMS -#define SMS 860 -#endif - // -- backend dispatch (P1-3) ------------------------------------------------ // Returns true iff cuBLASDx is expected to outperform the SIMT path for the @@ -19,7 +15,7 @@ // tuning_table.cuh; falls back to a conservative shape heuristic for shapes // not measured for that SM. // -// Used by glass::nvidia::gemm to decide whether to dispatch to cuBLASDx +// Used by glass::nvidia::block::gemm to decide whether to dispatch to cuBLASDx // (requires a DEFINE_NVIDIA_GEMM* specialization) or fall through to the // SIMT base path (no DEFINE needed). Today only T==float is tuned; other // types always return false (SIMT). @@ -55,11 +51,11 @@ constexpr bool should_use_cublasdx() { } // Diagnostic helper. Prints which backend -// `glass::nvidia::gemm` will dispatch to. Callable from +// `glass::nvidia::block::gemm` will dispatch to. Callable from // host or device (printf works in CUDA device code). // -// glass::nvidia::print_dispatch(); -// // -> "glass::nvidia::gemm: SIMT fallback" +// glass::nvidia::block::print_dispatch(); +// // -> "glass::nvidia::block::gemm: SIMT fallback" // // Useful when debugging "why is my GEMM slow" or "why does the linker complain // that gemm is undefined" (answer: the heuristic identified it @@ -80,7 +76,7 @@ constexpr bool should_use_cublasdx() { template __host__ __device__ inline void print_dispatch() { - printf("glass::nvidia::gemm: %s\n", + printf("glass::nvidia::block::gemm: %s\n", M, N, K, SM_VAL, should_use_cublasdx() ? "cuBLASDx (needs DEFINE_NVIDIA_GEMM*)" @@ -229,7 +225,7 @@ constexpr bool should_use_cublasdx_batched() { */ template __host__ __device__ inline void print_dispatch_gemv() { - printf("glass::nvidia::gemv: %s\n", + printf("glass::nvidia::block::gemv: %s\n", M, N, SM_VAL, should_use_cublasdx_gemv() ? "cuBLASDx (needs DEFINE_NVIDIA_GEMV*)" @@ -252,7 +248,7 @@ __host__ __device__ inline void print_dispatch_gemv() { template __host__ __device__ inline void print_dispatch_gemm_strided() { - printf("glass::nvidia::gemm_strided: %s\n", + printf("glass::nvidia::block::gemm_strided: %s\n", M, N, K, A_RS, B_RS, SM_VAL, should_use_cublasdx_gemm_strided() ? "cuBLASDx (needs DEFINE_NVIDIA_GEMM*)" @@ -273,7 +269,7 @@ __host__ __device__ inline void print_dispatch_gemm_strided() { template __host__ __device__ inline void print_dispatch_gemv_strided() { - printf("glass::nvidia::gemv_strided: %s\n", + printf("glass::nvidia::block::gemv_strided: %s\n", M, N, ROW_STRIDE, SM_VAL, should_use_cublasdx_gemv_strided() ? "cuBLASDx (needs DEFINE_NVIDIA_GEMV*)" @@ -296,7 +292,7 @@ __host__ __device__ inline void print_dispatch_gemv_strided() { template __host__ __device__ inline void print_dispatch_batched() { - printf("glass::nvidia::gemm_batched_1d: %s\n", + printf("glass::nvidia::block::gemm_batched_1d: %s\n", M, N, K, BATCH, SM_VAL, should_use_cublasdx_batched() ? "cuBLASDx (no auto-dispatch; see 2D gemm_batched)" diff --git a/src/nvidia/types.cuh b/src/nvidia/types.cuh index be1beed..787c455 100644 --- a/src/nvidia/types.cuh +++ b/src/nvidia/types.cuh @@ -1,7 +1,7 @@ #pragma once /** * @file types.cuh - * @brief Public types and shared helper macros for the `glass::nvidia::` wrappers. + * @brief Public types and shared helper macros for the `glass::nvidia::*` wrappers. * * Defines the user-facing `glass::nvidia::layout` enum (per-matrix memory * order, used as the LA/LB/LC template arguments of gemm/gemv/...) plus the @@ -13,7 +13,7 @@ #include /** - * @brief Matrix memory layout for the cuBLASDx-backed `glass::nvidia::` wrappers. + * @brief Matrix memory layout for the cuBLASDx-backed `glass::nvidia::block::` wrappers. * * Maps directly to `cublasdx::Arrangement<>`: `col_major` (Fortran/cuBLAS * default) and `row_major` (C-style). Passed per matrix as the LA/LB/LC diff --git a/test/README.md b/test/README.md index edc22a4..aeaff01 100644 --- a/test/README.md +++ b/test/README.md @@ -23,7 +23,7 @@ gracefully** when it is absent. | `test_l1.py` | L1 vector ops (axpy, copy, dot, reduce, norms, elementwise, …) | | `test_l2.py` | L2 matrix-vector ops (gemv, ger, strided/segmented) | | `test_l3.py` | L3 matrix ops (gemm family, inv, chol, trsm, batched-1D) | -| `test_nvidia_dispatch.py` | `glass::nvidia::` SIMT-vs-cuBLASDx auto-dispatch (needs MathDx) | +| `test_nvidia_dispatch.py` | `glass::nvidia::block::` SIMT-vs-cuBLASDx dispatch (needs MathDx) | | `test_trailing_sync.py` | the `TRAILING_SYNC` template parameter across the surface | | `cuda/*.cu` | the CUDA programs the Python tests invoke (`helpers.cuh` shared) | | `conftest.py` | arch detection, compile caching, fixtures, `run_op` harness | diff --git a/test/api-contracts.json b/test/api-contracts.json index ec35abc..3b6cc89 100644 --- a/test/api-contracts.json +++ b/test/api-contracts.json @@ -5,144 +5,34 @@ "policy": "test/api-coverage-policy.json", "contracts": [ { - "id": "suggested_backend-8c00afaa3420", - "name": "suggested_backend", + "id": "recommend-07b02a9e09f5", + "name": "recommend", "file": "glass-defaults.cuh", - "line": 294, - "surface": "glass::", - "signature": "glass::suggested_backend()", - "params": 0, - "required_params": 0, - "template_params": 4, - "minimum_explicit_template_args": 3, - "evidence": [ - { - "file": "test/cuda/test_defaults.cu", - "line": 87, - "name": "suggested_backend", - "surface": "glass::", - "args": 0, - "explicit_template_args": 4 - } - ] - }, - { - "id": "suggested_backend_rect_gemv-a580ca391916", - "name": "suggested_backend_rect_gemv", - "file": "glass-defaults.cuh", - "line": 305, + "line": 391, "surface": "glass::", - "signature": "glass::suggested_backend_rect_gemv()", - "params": 0, + "signature": "glass::recommend(dependency_set dependencies=dependency_set::native_only, uint32_t sm=GLASS_TARGET_SM)", + "params": 2, "required_params": 0, - "template_params": 4, + "template_params": 3, "minimum_explicit_template_args": 3, "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 95, - "name": "suggested_backend_rect_gemv", - "surface": "glass::", - "args": 0, - "explicit_template_args": 4 - } - ] - }, - { - "id": "suggested_backend_rect_gemm-4925837b6492", - "name": "suggested_backend_rect_gemm", - "file": "glass-defaults.cuh", - "line": 311, - "surface": "glass::", - "signature": "glass::suggested_backend_rect_gemm()", - "params": 0, - "required_params": 0, - "template_params": 5, - "minimum_explicit_template_args": 4, - "evidence": [ - { - "file": "test/cuda/test_defaults.cu", - "line": 96, - "name": "suggested_backend_rect_gemm", - "surface": "glass::", - "args": 0, - "explicit_template_args": 5 - } - ] - }, - { - "id": "suggested_block_threads-9cdd283cce09", - "name": "suggested_block_threads", - "file": "glass-defaults.cuh", - "line": 318, - "surface": "glass::", - "signature": "glass::suggested_block_threads()", - "params": 0, - "required_params": 0, - "template_params": 4, - "minimum_explicit_template_args": 2, - "evidence": [ - { - "file": "test/cuda/test_defaults.cu", - "line": 149, - "name": "suggested_block_threads", - "surface": "glass::", - "args": 0, - "explicit_template_args": 3 - } - ] - }, - { - "id": "suggested_warps_per_block-8a7ccdd6543d", - "name": "suggested_warps_per_block", - "file": "glass-defaults.cuh", - "line": 330, - "surface": "glass::", - "signature": "glass::suggested_warps_per_block()", - "params": 0, - "required_params": 0, - "template_params": 4, - "minimum_explicit_template_args": 1, - "evidence": [ - { - "file": "test/cuda/test_defaults.cu", - "line": 153, - "name": "suggested_warps_per_block", - "surface": "glass::", - "args": 0, - "explicit_template_args": 1 - } - ] - }, - { - "id": "suggested_threads_per_block-f6bdd4b0d410", - "name": "suggested_threads_per_block", - "file": "glass-defaults.cuh", - "line": 343, - "surface": "glass::", - "signature": "glass::suggested_threads_per_block()", - "params": 0, - "required_params": 0, - "template_params": 4, - "minimum_explicit_template_args": 1, - "evidence": [ - { - "file": "examples/08_backend_picker.cu", - "line": 47, - "name": "suggested_threads_per_block", + "line": 98, + "name": "recommend", "surface": "glass::", - "args": 0, + "args": 2, "explicit_template_args": 3 } ] }, { - "id": "dispatch_body-038f4a26e42c", + "id": "dispatch_body-a7d364cc76bf", "name": "dispatch_body", "file": "glass-dispatch.cuh", - "line": 128, + "line": 138, "surface": "glass::", - "signature": "glass::dispatch_body(op o, uint32_t N, bool f64, uint32_t sm=(1200u))", + "signature": "glass::dispatch_body(op o, uint32_t N, bool f64, uint32_t sm=1200u)", "params": 4, "required_params": 3, "template_params": 0, @@ -150,10 +40,10 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 106, + "line": 121, "name": "dispatch_body", "surface": "glass::", - "args": 3, + "args": 4, "explicit_template_args": null } ] @@ -194,7 +84,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 162, + "line": 186, "name": "argreduce_scratch_bytes", "surface": "glass::", "args": 1, @@ -304,7 +194,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 162, + "line": 186, "name": "argreduce_fast_scratch_bytes", "surface": "glass::", "args": 1, @@ -1338,7 +1228,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 159, + "line": 183, "name": "dot_fast_scratch_bytes", "surface": "glass::", "args": 1, @@ -2108,7 +1998,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 161, + "line": 185, "name": "iamax_scratch_bytes", "surface": "glass::", "args": 1, @@ -2130,7 +2020,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 161, + "line": 185, "name": "iamax_fast_scratch_bytes", "surface": "glass::", "args": 1, @@ -3758,7 +3648,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 172, + "line": 196, "name": "softmax_scratch_bytes", "surface": "glass::", "args": 1, @@ -4550,7 +4440,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 166, + "line": 190, "name": "trmv_scratch_bytes", "surface": "glass::", "args": 1, @@ -4638,7 +4528,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 163, + "line": 187, "name": "congruence_scratch_bytes", "surface": "glass::", "args": 0, @@ -4924,7 +4814,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 175, + "line": 199, "name": "eigh_sweeps", "surface": "glass::", "args": 0, @@ -5262,33 +5152,11 @@ } ] }, - { - "id": "suggested_use_reduced-3a6ad0262edd", - "name": "suggested_use_reduced", - "file": "src/base/L3/gemm_reduced.cuh", - "line": 48, - "surface": "glass::block::", - "signature": "glass::block::suggested_use_reduced()", - "params": 0, - "required_params": 0, - "template_params": 3, - "minimum_explicit_template_args": 3, - "evidence": [ - { - "file": "test/cuda/test_defaults.cu", - "line": 177, - "name": "suggested_use_reduced", - "surface": "glass::", - "args": 0, - "explicit_template_args": 3 - } - ] - }, { "id": "gemm_reduced-7c5d367bdf21", "name": "gemm_reduced", "file": "src/base/L3/gemm_reduced.cuh", - "line": 136, + "line": 113, "surface": "glass::block::", "signature": "glass::block::gemm_reduced(T alpha, T *A, T *B, T beta, T *C)", "params": 5, @@ -5310,7 +5178,7 @@ "id": "gemm_reduced-f3c24aab0373", "name": "gemm_reduced", "file": "src/base/L3/gemm_reduced.cuh", - "line": 163, + "line": 140, "surface": "glass::block::", "signature": "glass::block::gemm_reduced(T alpha, T *A, T *B, T *C)", "params": 4, @@ -5332,7 +5200,7 @@ "id": "gemm_reduced-3920da2d1dbf", "name": "gemm_reduced", "file": "src/base/L3/gemm_reduced.cuh", - "line": 198, + "line": 175, "surface": "glass::warp::", "signature": "glass::warp::gemm_reduced(T alpha, T *A, T *B, T beta, T *C)", "params": 5, @@ -5354,7 +5222,7 @@ "id": "gemm_reduced-b2eb3c65cd00", "name": "gemm_reduced", "file": "src/base/L3/gemm_reduced.cuh", - "line": 224, + "line": 201, "surface": "glass::warp::", "signature": "glass::warp::gemm_reduced(T alpha, T *A, T *B, T *C)", "params": 4, @@ -5628,7 +5496,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 164, + "line": 188, "name": "gn_step_scratch_bytes", "surface": "glass::", "args": 0, @@ -5716,7 +5584,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 170, + "line": 194, "name": "inv_scratch_bytes", "surface": "glass::", "args": 1, @@ -5738,7 +5606,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 171, + "line": 195, "name": "inv_pivoted_scratch_bytes", "surface": "glass::", "args": 1, @@ -5804,7 +5672,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 174, + "line": 198, "name": "inv_fused_scratch_bytes", "surface": "glass::", "args": 2, @@ -5892,7 +5760,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 165, + "line": 189, "name": "inv_dense_scratch_bytes", "surface": "glass::", "args": 1, @@ -6002,7 +5870,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 169, + "line": 193, "name": "ldlt_scratch_bytes", "surface": "glass::", "args": 1, @@ -6640,7 +6508,7 @@ "evidence": [ { "file": "test/cuda/test_defaults.cu", - "line": 176, + "line": 200, "name": "syev_eps", "surface": "glass::", "args": 0, @@ -13064,7 +12932,7 @@ "evidence": [ { "file": "test/cuda/test_l3_nvidia.cu", - "line": 33, + "line": 39, "name": "reduce", "surface": "glass::nvidia::block::", "args": 2, @@ -13108,7 +12976,7 @@ "evidence": [ { "file": "test/cuda/test_l3_nvidia.cu", - "line": 34, + "line": 40, "name": "nrm2", "surface": "glass::nvidia::block::", "args": 3, @@ -13130,7 +12998,7 @@ "evidence": [ { "file": "test/cuda/test_l3_nvidia.cu", - "line": 25, + "line": 31, "name": "reduce_scratch_bytes", "surface": "glass::nvidia::block::", "args": 0, @@ -13218,7 +13086,7 @@ "evidence": [ { "file": "test/cuda/test_l3_nvidia.cu", - "line": 27, + "line": 33, "name": "warp_reduce_scratch_bytes", "surface": "glass::nvidia::warp::", "args": 0, @@ -13230,7 +13098,7 @@ "id": "gemv-0f13edf944b2", "name": "gemv", "file": "src/nvidia/l2.cuh", - "line": 80, + "line": 76, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemv(T alpha, T *A, T *x, T beta, T *y, char *smem)", "params": 6, @@ -13252,7 +13120,7 @@ "id": "gemv_scratch_bytes-51443e641eda", "name": "gemv_scratch_bytes", "file": "src/nvidia/l2.cuh", - "line": 117, + "line": 113, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemv_scratch_bytes()", "params": 0, @@ -13274,7 +13142,7 @@ "id": "gemv_threads-5113c9385d24", "name": "gemv_threads", "file": "src/nvidia/l2.cuh", - "line": 141, + "line": 137, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemv_threads()", "params": 0, @@ -13296,7 +13164,7 @@ "id": "gemv_strided-0b638c57deb4", "name": "gemv_strided", "file": "src/nvidia/l2.cuh", - "line": 408, + "line": 404, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemv_strided(T alpha, T *A, T *x, T beta, T *y, char *smem)", "params": 6, @@ -13318,7 +13186,7 @@ "id": "gemv_strided_scratch_bytes-6b40842e0b0b", "name": "gemv_strided_scratch_bytes", "file": "src/nvidia/l2.cuh", - "line": 453, + "line": 449, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemv_strided_scratch_bytes()", "params": 0, @@ -13328,7 +13196,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 291, + "line": 290, "name": "gemv_strided_scratch_bytes", "surface": "glass::nvidia::block::", "args": 0, @@ -13340,7 +13208,7 @@ "id": "gemm-9d55cdee47ad", "name": "gemm", "file": "src/nvidia/l3.cuh", - "line": 118, + "line": 114, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemm(T alpha, T *A, T *B, T beta, T *C, char *smem)", "params": 6, @@ -13362,7 +13230,7 @@ "id": "gemm_scratch_bytes-ec16e9242b25", "name": "gemm_scratch_bytes", "file": "src/nvidia/l3.cuh", - "line": 163, + "line": 159, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemm_scratch_bytes()", "params": 0, @@ -13384,7 +13252,7 @@ "id": "gemm_threads-aa44c8bc7790", "name": "gemm_threads", "file": "src/nvidia/l3.cuh", - "line": 188, + "line": 184, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemm_threads()", "params": 0, @@ -13406,7 +13274,7 @@ "id": "gemm_strided-4214eb49c1d2", "name": "gemm_strided", "file": "src/nvidia/l3.cuh", - "line": 493, + "line": 489, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemm_strided(T alpha, T *A, T *B, T beta, T *C, char *smem)", "params": 6, @@ -13428,7 +13296,7 @@ "id": "gemm_strided_scratch_bytes-85c8cdecf190", "name": "gemm_strided_scratch_bytes", "file": "src/nvidia/l3.cuh", - "line": 549, + "line": 545, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemm_strided_scratch_bytes()", "params": 0, @@ -13438,7 +13306,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 290, + "line": 289, "name": "gemm_strided_scratch_bytes", "surface": "glass::nvidia::block::", "args": 0, @@ -13450,7 +13318,7 @@ "id": "gemm_batched-e52504d3a715", "name": "gemm_batched", "file": "src/nvidia/l3.cuh", - "line": 608, + "line": 604, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemm_batched(T alpha, T *const *A, T *const *B, T beta, T *const *C, char *smem)", "params": 6, @@ -13460,7 +13328,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 298, + "line": 297, "name": "gemm_batched", "surface": "glass::nvidia::block::", "args": 6, @@ -13472,7 +13340,7 @@ "id": "gemm_batched_scratch_bytes-85fadb076c65", "name": "gemm_batched_scratch_bytes", "file": "src/nvidia/l3.cuh", - "line": 640, + "line": 636, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemm_batched_scratch_bytes()", "params": 0, @@ -13482,7 +13350,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 283, + "line": 282, "name": "gemm_batched_scratch_bytes", "surface": "glass::nvidia::block::", "args": 0, @@ -13494,7 +13362,7 @@ "id": "gemm_batched_threads-ec5194093f54", "name": "gemm_batched_threads", "file": "src/nvidia/l3.cuh", - "line": 666, + "line": 662, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemm_batched_threads()", "params": 0, @@ -13504,7 +13372,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 284, + "line": 283, "name": "gemm_batched_threads", "surface": "glass::nvidia::block::", "args": 0, @@ -13526,7 +13394,7 @@ "evidence": [ { "file": "test/cuda/test_l3_nvidia.cu", - "line": 40, + "line": 46, "name": "gemm_batched_1d", "surface": "glass::nvidia::block::", "args": 5, @@ -13548,7 +13416,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 285, + "line": 284, "name": "gemm_batched_1d_scratch_bytes", "surface": "glass::nvidia::block::", "args": 0, @@ -13570,7 +13438,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 286, + "line": 285, "name": "gemm_batched_1d_threads", "surface": "glass::nvidia::block::", "args": 0, @@ -13592,7 +13460,7 @@ "evidence": [ { "file": "test/cuda/test_l3_nvidia.cu", - "line": 54, + "line": 60, "name": "gemm_strided_batched_1d", "surface": "glass::nvidia::block::", "args": 5, @@ -13614,7 +13482,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 288, + "line": 287, "name": "gemm_strided_batched_1d_scratch_bytes", "surface": "glass::nvidia::block::", "args": 0, @@ -13636,7 +13504,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 289, + "line": 288, "name": "gemm_strided_batched_1d_threads", "surface": "glass::nvidia::block::", "args": 0, @@ -13648,7 +13516,7 @@ "id": "potrf-bf90c8e1b518", "name": "potrf", "file": "src/nvidia/lapack.cuh", - "line": 73, + "line": 69, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::potrf(T *A, char *smem)", "params": 2, @@ -13670,7 +13538,7 @@ "id": "potrf_scratch_bytes-db713b6ac58b", "name": "potrf_scratch_bytes", "file": "src/nvidia/lapack.cuh", - "line": 85, + "line": 81, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::potrf_scratch_bytes()", "params": 0, @@ -13692,7 +13560,7 @@ "id": "potrf_threads-2264183bdcc1", "name": "potrf_threads", "file": "src/nvidia/lapack.cuh", - "line": 92, + "line": 88, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::potrf_threads()", "params": 0, @@ -13714,7 +13582,7 @@ "id": "trsm-5c9290421a12", "name": "trsm", "file": "src/nvidia/lapack.cuh", - "line": 117, + "line": 113, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::trsm(T alpha, T *L, T *B, char *smem)", "params": 4, @@ -13736,7 +13604,7 @@ "id": "trsm_scratch_bytes-d2d6d0b5a6b1", "name": "trsm_scratch_bytes", "file": "src/nvidia/lapack.cuh", - "line": 130, + "line": 126, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::trsm_scratch_bytes()", "params": 0, @@ -13758,7 +13626,7 @@ "id": "trsm_threads-40be83918022", "name": "trsm_threads", "file": "src/nvidia/lapack.cuh", - "line": 138, + "line": 134, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::trsm_threads()", "params": 0, @@ -13780,7 +13648,7 @@ "id": "posv-b6fc104efc5a", "name": "posv", "file": "src/nvidia/lapack.cuh", - "line": 462, + "line": 458, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::posv(T *A, T *B, char *smem)", "params": 3, @@ -13802,7 +13670,7 @@ "id": "posv_scratch_bytes-380eeedab49c", "name": "posv_scratch_bytes", "file": "src/nvidia/lapack.cuh", - "line": 475, + "line": 471, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::posv_scratch_bytes()", "params": 0, @@ -13824,7 +13692,7 @@ "id": "posv_threads-830f3fd519f0", "name": "posv_threads", "file": "src/nvidia/lapack.cuh", - "line": 483, + "line": 479, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::posv_threads()", "params": 0, @@ -13846,7 +13714,7 @@ "id": "potrs-cd7450d44244", "name": "potrs", "file": "src/nvidia/lapack.cuh", - "line": 616, + "line": 612, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::potrs(const T *L, T *B, char *smem)", "params": 3, @@ -13868,7 +13736,7 @@ "id": "potrs_scratch_bytes-bdcd059eb3b5", "name": "potrs_scratch_bytes", "file": "src/nvidia/lapack.cuh", - "line": 629, + "line": 625, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::potrs_scratch_bytes()", "params": 0, @@ -13890,7 +13758,7 @@ "id": "potrs_threads-311d60447994", "name": "potrs_threads", "file": "src/nvidia/lapack.cuh", - "line": 637, + "line": 633, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::potrs_threads()", "params": 0, @@ -13912,7 +13780,7 @@ "id": "getrf_no_pivot-299a78878fa8", "name": "getrf_no_pivot", "file": "src/nvidia/lapack.cuh", - "line": 747, + "line": 743, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::getrf_no_pivot(T *A, char *smem)", "params": 2, @@ -13934,7 +13802,7 @@ "id": "getrf_no_pivot_scratch_bytes-b7f28d10ff4c", "name": "getrf_no_pivot_scratch_bytes", "file": "src/nvidia/lapack.cuh", - "line": 759, + "line": 755, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::getrf_no_pivot_scratch_bytes()", "params": 0, @@ -13956,7 +13824,7 @@ "id": "getrf_no_pivot_threads-36323d3b0e92", "name": "getrf_no_pivot_threads", "file": "src/nvidia/lapack.cuh", - "line": 766, + "line": 762, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::getrf_no_pivot_threads()", "params": 0, @@ -13978,7 +13846,7 @@ "id": "getrs_no_pivot-7c1a4c2dd8d5", "name": "getrs_no_pivot", "file": "src/nvidia/lapack.cuh", - "line": 874, + "line": 870, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::getrs_no_pivot(const T *LU, T *B, char *smem)", "params": 3, @@ -14000,7 +13868,7 @@ "id": "getrs_no_pivot_scratch_bytes-af42106a0cbc", "name": "getrs_no_pivot_scratch_bytes", "file": "src/nvidia/lapack.cuh", - "line": 887, + "line": 883, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::getrs_no_pivot_scratch_bytes()", "params": 0, @@ -14022,7 +13890,7 @@ "id": "getrs_no_pivot_threads-f1c9f3f57939", "name": "getrs_no_pivot_threads", "file": "src/nvidia/lapack.cuh", - "line": 895, + "line": 891, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::getrs_no_pivot_threads()", "params": 0, @@ -14044,7 +13912,7 @@ "id": "gesv_no_pivot-b738c4f88549", "name": "gesv_no_pivot", "file": "src/nvidia/lapack.cuh", - "line": 1007, + "line": 1003, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gesv_no_pivot(T *A, T *B, char *smem)", "params": 3, @@ -14066,7 +13934,7 @@ "id": "gesv_no_pivot_scratch_bytes-b1c2d0df3353", "name": "gesv_no_pivot_scratch_bytes", "file": "src/nvidia/lapack.cuh", - "line": 1020, + "line": 1016, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gesv_no_pivot_scratch_bytes()", "params": 0, @@ -14088,7 +13956,7 @@ "id": "gesv_no_pivot_threads-1046318c3894", "name": "gesv_no_pivot_threads", "file": "src/nvidia/lapack.cuh", - "line": 1028, + "line": 1024, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gesv_no_pivot_threads()", "params": 0, @@ -14110,7 +13978,7 @@ "id": "geqrf-a8b236df00c4", "name": "geqrf", "file": "src/nvidia/lapack.cuh", - "line": 1157, + "line": 1153, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::geqrf(T *A, T *tau, char *smem)", "params": 3, @@ -14132,7 +14000,7 @@ "id": "geqrf_scratch_bytes-27a5b606b707", "name": "geqrf_scratch_bytes", "file": "src/nvidia/lapack.cuh", - "line": 1170, + "line": 1166, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::geqrf_scratch_bytes()", "params": 0, @@ -14154,7 +14022,7 @@ "id": "geqrf_threads-b1b833b1b5a5", "name": "geqrf_threads", "file": "src/nvidia/lapack.cuh", - "line": 1178, + "line": 1174, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::geqrf_threads()", "params": 0, @@ -14176,7 +14044,7 @@ "id": "gels-566d248e95d9", "name": "gels", "file": "src/nvidia/lapack.cuh", - "line": 1291, + "line": 1287, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gels(T *A, T *tau, T *B, char *smem)", "params": 4, @@ -14198,7 +14066,7 @@ "id": "gels_scratch_bytes-41e3f65a63c1", "name": "gels_scratch_bytes", "file": "src/nvidia/lapack.cuh", - "line": 1304, + "line": 1300, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gels_scratch_bytes()", "params": 0, @@ -14220,7 +14088,7 @@ "id": "gels_threads-6f5b13971bd2", "name": "gels_threads", "file": "src/nvidia/lapack.cuh", - "line": 1312, + "line": 1308, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gels_threads()", "params": 0, @@ -14238,11 +14106,209 @@ } ] }, + { + "id": "potrf-ef14c211f825", + "name": "potrf", + "file": "src/nvidia/lapack_thread.cuh", + "line": 23, + "surface": "glass::nvidia::thread::", + "signature": "glass::nvidia::thread::potrf(T *A)", + "params": 1, + "required_params": 1, + "template_params": 3, + "minimum_explicit_template_args": 2, + "evidence": [ + { + "file": "test/cuda/test_nvidia_thread.cu", + "line": 38, + "name": "potrf", + "surface": "glass::nvidia::thread::", + "args": 1, + "explicit_template_args": 2 + } + ] + }, + { + "id": "trsm-9d124f8912a1", + "name": "trsm", + "file": "src/nvidia/lapack_thread.cuh", + "line": 40, + "surface": "glass::nvidia::thread::", + "signature": "glass::nvidia::thread::trsm(T alpha, const T *L, T *B)", + "params": 3, + "required_params": 3, + "template_params": 4, + "minimum_explicit_template_args": 3, + "evidence": [ + { + "file": "test/cuda/test_nvidia_thread.cu", + "line": 45, + "name": "trsm", + "surface": "glass::nvidia::thread::", + "args": 3, + "explicit_template_args": 3 + } + ] + }, + { + "id": "posv-8caf82a1d4b2", + "name": "posv", + "file": "src/nvidia/lapack_thread.cuh", + "line": 63, + "surface": "glass::nvidia::thread::", + "signature": "glass::nvidia::thread::posv(T *A, T *B)", + "params": 2, + "required_params": 2, + "template_params": 4, + "minimum_explicit_template_args": 3, + "evidence": [ + { + "file": "test/cuda/test_nvidia_thread.cu", + "line": 53, + "name": "posv", + "surface": "glass::nvidia::thread::", + "args": 2, + "explicit_template_args": 3 + } + ] + }, + { + "id": "potrs-826eb6c75cb1", + "name": "potrs", + "file": "src/nvidia/lapack_thread.cuh", + "line": 81, + "surface": "glass::nvidia::thread::", + "signature": "glass::nvidia::thread::potrs(const T *L, T *B)", + "params": 2, + "required_params": 2, + "template_params": 4, + "minimum_explicit_template_args": 3, + "evidence": [ + { + "file": "test/cuda/test_nvidia_thread.cu", + "line": 61, + "name": "potrs", + "surface": "glass::nvidia::thread::", + "args": 2, + "explicit_template_args": 3 + } + ] + }, + { + "id": "getrf_no_pivot-0e9536fd5e0b", + "name": "getrf_no_pivot", + "file": "src/nvidia/lapack_thread.cuh", + "line": 98, + "surface": "glass::nvidia::thread::", + "signature": "glass::nvidia::thread::getrf_no_pivot(T *A)", + "params": 1, + "required_params": 1, + "template_params": 3, + "minimum_explicit_template_args": 2, + "evidence": [ + { + "file": "test/cuda/test_nvidia_thread.cu", + "line": 69, + "name": "getrf_no_pivot", + "surface": "glass::nvidia::thread::", + "args": 1, + "explicit_template_args": 2 + } + ] + }, + { + "id": "getrs_no_pivot-b445a0e26892", + "name": "getrs_no_pivot", + "file": "src/nvidia/lapack_thread.cuh", + "line": 114, + "surface": "glass::nvidia::thread::", + "signature": "glass::nvidia::thread::getrs_no_pivot(const T *LU, T *B)", + "params": 2, + "required_params": 2, + "template_params": 4, + "minimum_explicit_template_args": 3, + "evidence": [ + { + "file": "test/cuda/test_nvidia_thread.cu", + "line": 79, + "name": "getrs_no_pivot", + "surface": "glass::nvidia::thread::", + "args": 2, + "explicit_template_args": 3 + } + ] + }, + { + "id": "gesv_no_pivot-4485251296f7", + "name": "gesv_no_pivot", + "file": "src/nvidia/lapack_thread.cuh", + "line": 130, + "surface": "glass::nvidia::thread::", + "signature": "glass::nvidia::thread::gesv_no_pivot(T *A, T *B)", + "params": 2, + "required_params": 2, + "template_params": 4, + "minimum_explicit_template_args": 3, + "evidence": [ + { + "file": "test/cuda/test_nvidia_thread.cu", + "line": 87, + "name": "gesv_no_pivot", + "surface": "glass::nvidia::thread::", + "args": 2, + "explicit_template_args": 3 + } + ] + }, + { + "id": "geqrf-7d43a9aab93a", + "name": "geqrf", + "file": "src/nvidia/lapack_thread.cuh", + "line": 147, + "surface": "glass::nvidia::thread::", + "signature": "glass::nvidia::thread::geqrf(T *A, T *tau)", + "params": 2, + "required_params": 2, + "template_params": 4, + "minimum_explicit_template_args": 3, + "evidence": [ + { + "file": "test/cuda/test_nvidia_thread.cu", + "line": 96, + "name": "geqrf", + "surface": "glass::nvidia::thread::", + "args": 2, + "explicit_template_args": 3 + } + ] + }, + { + "id": "gels-bda360d11cd0", + "name": "gels", + "file": "src/nvidia/lapack_thread.cuh", + "line": 163, + "surface": "glass::nvidia::thread::", + "signature": "glass::nvidia::thread::gels(T *A, T *tau, T *B)", + "params": 3, + "required_params": 3, + "template_params": 5, + "minimum_explicit_template_args": 4, + "evidence": [ + { + "file": "test/cuda/test_nvidia_thread.cu", + "line": 104, + "name": "gels", + "surface": "glass::nvidia::thread::", + "args": 3, + "explicit_template_args": 4 + } + ] + }, { "id": "gemm_min_block_threads-84949d4ce7f8", "name": "gemm_min_block_threads", "file": "src/nvidia/query.cuh", - "line": 45, + "line": 41, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemm_min_block_threads()", "params": 0, @@ -14252,7 +14318,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 273, + "line": 272, "name": "gemm_min_block_threads", "surface": "glass::nvidia::block::", "args": 0, @@ -14264,7 +14330,7 @@ "id": "gemm_block_threads_valid-748a4079b356", "name": "gemm_block_threads_valid", "file": "src/nvidia/query.cuh", - "line": 78, + "line": 74, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemm_block_threads_valid()", "params": 0, @@ -14274,7 +14340,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 274, + "line": 273, "name": "gemm_block_threads_valid", "surface": "glass::nvidia::block::", "args": 0, @@ -14286,7 +14352,7 @@ "id": "gemv_min_block_threads-4fd6d10d3cd3", "name": "gemv_min_block_threads", "file": "src/nvidia/query.cuh", - "line": 99, + "line": 95, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemv_min_block_threads()", "params": 0, @@ -14296,7 +14362,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 275, + "line": 274, "name": "gemv_min_block_threads", "surface": "glass::nvidia::block::", "args": 0, @@ -14308,7 +14374,7 @@ "id": "gemv_block_threads_valid-7b557edf6603", "name": "gemv_block_threads_valid", "file": "src/nvidia/query.cuh", - "line": 127, + "line": 123, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemv_block_threads_valid()", "params": 0, @@ -14318,7 +14384,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 276, + "line": 275, "name": "gemv_block_threads_valid", "surface": "glass::nvidia::block::", "args": 0, @@ -14330,7 +14396,7 @@ "id": "should_use_cublasdx-0410bcb19e1a", "name": "should_use_cublasdx", "file": "src/nvidia/query_simt.cuh", - "line": 47, + "line": 43, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::should_use_cublasdx()", "params": 0, @@ -14340,7 +14406,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 268, + "line": 267, "name": "should_use_cublasdx", "surface": "glass::nvidia::block::", "args": 0, @@ -14352,7 +14418,7 @@ "id": "print_dispatch-1062ecc4ecd2", "name": "print_dispatch", "file": "src/nvidia/query_simt.cuh", - "line": 82, + "line": 78, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::print_dispatch()", "params": 0, @@ -14362,7 +14428,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 342, + "line": 341, "name": "print_dispatch", "surface": "glass::nvidia::block::", "args": 0, @@ -14374,7 +14440,7 @@ "id": "gemm_batched_1d_block_threads_valid-8343bb4edeac", "name": "gemm_batched_1d_block_threads_valid", "file": "src/nvidia/query_simt.cuh", - "line": 114, + "line": 110, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::gemm_batched_1d_block_threads_valid()", "params": 0, @@ -14384,7 +14450,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 287, + "line": 286, "name": "gemm_batched_1d_block_threads_valid", "surface": "glass::nvidia::block::", "args": 0, @@ -14396,7 +14462,7 @@ "id": "should_use_cublasdx_gemv-b0e609713889", "name": "should_use_cublasdx_gemv", "file": "src/nvidia/query_simt.cuh", - "line": 146, + "line": 142, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::should_use_cublasdx_gemv()", "params": 0, @@ -14406,7 +14472,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 269, + "line": 268, "name": "should_use_cublasdx_gemv", "surface": "glass::nvidia::block::", "args": 0, @@ -14418,7 +14484,7 @@ "id": "should_use_cublasdx_gemv_strided-196bd802a570", "name": "should_use_cublasdx_gemv_strided", "file": "src/nvidia/query_simt.cuh", - "line": 166, + "line": 162, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::should_use_cublasdx_gemv_strided()", "params": 0, @@ -14428,7 +14494,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 270, + "line": 269, "name": "should_use_cublasdx_gemv_strided", "surface": "glass::nvidia::block::", "args": 0, @@ -14440,7 +14506,7 @@ "id": "should_use_cublasdx_gemm_strided-7cc5648eb226", "name": "should_use_cublasdx_gemm_strided", "file": "src/nvidia/query_simt.cuh", - "line": 188, + "line": 184, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::should_use_cublasdx_gemm_strided()", "params": 0, @@ -14450,7 +14516,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 271, + "line": 270, "name": "should_use_cublasdx_gemm_strided", "surface": "glass::nvidia::block::", "args": 0, @@ -14462,7 +14528,7 @@ "id": "should_use_cublasdx_batched-bf0b82bbe784", "name": "should_use_cublasdx_batched", "file": "src/nvidia/query_simt.cuh", - "line": 210, + "line": 206, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::should_use_cublasdx_batched()", "params": 0, @@ -14472,7 +14538,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 272, + "line": 271, "name": "should_use_cublasdx_batched", "surface": "glass::nvidia::block::", "args": 0, @@ -14484,7 +14550,7 @@ "id": "print_dispatch_gemv-deb653621bd1", "name": "print_dispatch_gemv", "file": "src/nvidia/query_simt.cuh", - "line": 231, + "line": 227, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::print_dispatch_gemv()", "params": 0, @@ -14494,7 +14560,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 347, + "line": 346, "name": "print_dispatch_gemv", "surface": "glass::nvidia::block::", "args": 0, @@ -14506,7 +14572,7 @@ "id": "print_dispatch_gemm_strided-aeb16d737889", "name": "print_dispatch_gemm_strided", "file": "src/nvidia/query_simt.cuh", - "line": 254, + "line": 250, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::print_dispatch_gemm_strided()", "params": 0, @@ -14516,7 +14582,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 349, + "line": 348, "name": "print_dispatch_gemm_strided", "surface": "glass::nvidia::block::", "args": 0, @@ -14528,7 +14594,7 @@ "id": "print_dispatch_gemv_strided-f6145fb961a4", "name": "print_dispatch_gemv_strided", "file": "src/nvidia/query_simt.cuh", - "line": 275, + "line": 271, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::print_dispatch_gemv_strided()", "params": 0, @@ -14538,7 +14604,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 348, + "line": 347, "name": "print_dispatch_gemv_strided", "surface": "glass::nvidia::block::", "args": 0, @@ -14550,7 +14616,7 @@ "id": "print_dispatch_batched-d55ef7cc6ad6", "name": "print_dispatch_batched", "file": "src/nvidia/query_simt.cuh", - "line": 298, + "line": 294, "surface": "glass::nvidia::block::", "signature": "glass::nvidia::block::print_dispatch_batched()", "params": 0, @@ -14560,7 +14626,7 @@ "evidence": [ { "file": "test/cuda/test_nvidia_dispatch.cu", - "line": 350, + "line": 349, "name": "print_dispatch_batched", "surface": "glass::nvidia::block::", "args": 0, @@ -14570,8 +14636,8 @@ } ], "summary": { - "covered": 662, - "total": 662, + "covered": 665, + "total": 665, "percent": 100.0, "ambiguous_calls": 38 } diff --git a/test/api-coverage-policy.json b/test/api-coverage-policy.json index b18d27c..43b3c7d 100644 --- a/test/api-coverage-policy.json +++ b/test/api-coverage-policy.json @@ -3,25 +3,30 @@ "basis": "Every Doxygen-documented function overload in an installed public header is a contract unless excluded here with a reason.", "exclude_files": { "src/base/barrier.cuh": "Barrier policies, ct_size, and beta_blend are implementation infrastructure, not callable user operations.", - "src/nvidia/tuning_table.cuh": "Generated dispatch-table implementation; users query it through should_use_* and suggested_* helpers." + "src/nvidia/tuning_table.cuh": "Generated dispatch-table implementation; users query it through the explicit NVIDIA block helpers and recommend()." }, "exclude_namespace_suffixes": { "detail": "Namespaces named *_detail contain implementation helpers rather than supported entry points." }, "exclude_symbols": { - "glass-defaults.cuh:nv_available": "Implementation helper behind suggested_backend.", "glass-defaults.cuh:ideal_sm120": "Generated architecture table implementation.", "glass-defaults.cuh:ideal_sm87": "Generated architecture table implementation.", + "glass-defaults.cuh:native_sm120": "Generated native-only architecture table implementation.", + "glass-defaults.cuh:native_sm87": "Generated native-only architecture table implementation.", "glass-defaults.cuh:blas2_sm120": "Generated architecture table implementation.", - "glass-defaults.cuh:is_blas2": "Implementation helper behind suggested_backend.", - "glass-defaults.cuh:blas2_ideal": "Implementation helper behind suggested_backend.", + "glass-defaults.cuh:is_blas2": "Implementation helper behind recommend().", + "glass-defaults.cuh:blas2_ideal": "Implementation helper behind recommend().", "glass-defaults.cuh:rect_gemv_sm120": "Generated architecture table implementation.", "glass-defaults.cuh:rect_gemm_sm120": "Generated architecture table implementation.", - "glass-defaults.cuh:rect_gemv_ideal": "Implementation helper behind suggested_backend_rect_gemv.", - "glass-defaults.cuh:rect_gemm_ideal": "Implementation helper behind suggested_backend_rect_gemm.", - "glass-defaults.cuh:ideal_generic": "Fallback implementation behind suggested_backend.", - "glass-defaults.cuh:without_nvidia": "Fallback implementation behind suggested_backend.", - "glass-defaults.cuh:ideal": "Implementation helper behind suggested_backend.", + "glass-defaults.cuh:rect_gemv_ideal": "Implementation helper behind recommend().", + "glass-defaults.cuh:rect_gemm_ideal": "Implementation helper behind recommend().", + "glass-defaults.cuh:ideal_generic": "Fallback implementation behind recommend().", + "glass-defaults.cuh:native_generic": "Fallback implementation behind recommend().", + "glass-defaults.cuh:ideal": "Implementation helper behind recommend().", + "glass-defaults.cuh:native_block_threads": "Launch-packing implementation behind recommend().", + "glass-defaults.cuh:native_warps_per_block": "Launch-packing implementation behind recommend().", + "glass-defaults.cuh:native_threads_per_block": "Launch-packing implementation behind recommend().", + "glass-defaults.cuh:make_plan": "Plan-construction implementation behind recommend().", "glass-dispatch.cuh:body_sm120": "Generated architecture table implementation.", "glass-dispatch.cuh:body_sm87": "Generated architecture table implementation.", "src/base/L1/reduce.cuh:operator()": "Reduction functor implementation.", diff --git a/test/conftest.py b/test/conftest.py index 560714e..8a5f2bd 100644 --- a/test/conftest.py +++ b/test/conftest.py @@ -8,6 +8,7 @@ import hashlib import os import pathlib +import platform import shlex import subprocess import sys @@ -28,6 +29,11 @@ def detect_arch() -> str: """Return nvcc arch flag like 'sm_86' by querying nvidia-smi.""" + override = os.environ.get("CUDA_ARCH") + if override: + if override.startswith("sm_") and override[3:].isdigit(): + return override + raise ValueError("CUDA_ARCH must look like sm_87") try: out = subprocess.check_output( ["nvidia-smi", "--query-gpu=compute_cap", "--format=csv,noheader"], @@ -189,7 +195,8 @@ def _hash_sources(cu_path: pathlib.Path) -> str: # ─── compilation ────────────────────────────────────────────────────────────── def compile_binary(name: str, build_dir: pathlib.Path, arch: str, - extra_flags: list = None) -> pathlib.Path: + extra_flags: list = None, + solver_fatbin: pathlib.Path | None = None) -> pathlib.Path: """Compile a CUDA test binary, skipping if the source hash is unchanged.""" cu_src = CUDA_DIR / f"{name}.cu" out_bin = build_dir / name @@ -202,6 +209,8 @@ def compile_binary(name: str, build_dir: pathlib.Path, arch: str, identity.update(_hash_sources(cu_src).encode()) identity.update(arch.encode()) identity.update("\0".join(extra_flags or []).encode()) + if solver_fatbin: + identity.update(solver_fatbin.read_bytes()) try: identity.update(subprocess.check_output(["nvcc", "--version"])) except Exception: @@ -212,22 +221,36 @@ def compile_binary(name: str, build_dir: pathlib.Path, arch: str, return out_bin build_dir.mkdir(parents=True, exist_ok=True) - cmd = [ + common = [ "nvcc", "-std=c++17", f"-arch={arch}", "-I", str(GLASS_DIR), "-I", str(GLASS_DIR / "src"), "-I", str(CUDA_DIR), - "-o", str(out_bin), - str(cu_src), ] - if extra_flags: - cmd += extra_flags - result = subprocess.run(cmd, capture_output=True, text=True) - if result.returncode != 0: - print(f"\nCompilation failed for {name}:\n{result.stderr}", file=sys.stderr) - raise RuntimeError(f"nvcc failed for {name}") + if solver_fatbin: + # MathDx's host archive is x86-64-only. Its LTO-IR device fatbin is + # architecture-neutral, so aarch64 uses the same three-stage link as + # bench/tune.py: device compile, fatbin device link, then host link. + obj = build_dir / f"{name}.o" + dlink = build_dir / f"{name}_dlink.o" + commands = [ + common + ["-rdc=true", "-dlto", "-dc", "-o", str(obj), + str(cu_src)] + (extra_flags or []), + ["nvcc", f"-arch={arch}", "-dlto", "-dlink", str(obj), + str(solver_fatbin), "-o", str(dlink)], + ["nvcc", f"-arch={arch}", str(obj), str(dlink), + "-lcublas", "-lcusolver", "-lcudart", "-o", str(out_bin)], + ] + else: + commands = [common + ["-o", str(out_bin), str(cu_src)] + + (extra_flags or [])] + for cmd in commands: + result = subprocess.run(cmd, capture_output=True, text=True) + if result.returncode != 0: + print(f"\nCompilation failed for {name}:\n{result.stderr}", file=sys.stderr) + raise RuntimeError(f"nvcc failed for {name}") hash_file.write_text(current_hash) return out_bin @@ -242,9 +265,9 @@ class LazyBins(Mapping): "ldlt", "getrf", "iamax", "fused", "warp", "thread", "posv", "reduced", "tensor", "factor_check", "congruence", "solve", "reduced_blas", "base_f64", "defaults", "dispatch", "l1_round2", "block_access", "symmetrize", "symm_rot", - "syev", "robotics", "api_vector", "api_dense", "api_factor", "api_robotics", "l3_nvidia", "nvidia_dispatch", "trailing_sync", "nvidia_f64", + "syev", "robotics", "api_vector", "api_dense", "api_factor", "api_robotics", "l3_nvidia", "nvidia_dispatch", "trailing_sync", "nvidia_f64", "nvidia_thread", } - optional = {"l3_nvidia", "nvidia_dispatch", "trailing_sync", "nvidia_f64"} + optional = {"l3_nvidia", "nvidia_dispatch", "trailing_sync", "nvidia_f64", "nvidia_thread"} def __init__(self): self.cache: dict[str, pathlib.Path] = {} @@ -259,27 +282,36 @@ def _mathdx(): def _compile(self, key: str) -> pathlib.Path: mathdx, cublasdx = self._mathdx() + target_sm = CUDA_ARCH.replace("sm_", "") + "0" flags: list[str] = [] if key == "nvidia_dispatch" and not cublasdx: raise KeyError(key) if key in {"nvidia_dispatch", "trailing_sync"} and cublasdx: flags = ["--expt-relaxed-constexpr", "-DGLASS_BENCH_CUBLASDX", + f"-DGLASS_TARGET_SM={target_sm}", "-I", str(mathdx / "include"), "-I", str(mathdx / "external/cutlass/include")] - if key == "nvidia_f64": + if key in {"nvidia_f64", "nvidia_thread"}: + archive = mathdx / "lib/libcusolverdx.a" if mathdx else None + fatbin = mathdx / "lib/libcusolverdx.fatbin" if mathdx else None solver = bool(cublasdx and (mathdx / "include/cusolverdx.hpp").exists() and (mathdx / "include/cusolverdx_io.hpp").exists() - and (mathdx / "lib/libcusolverdx.a").exists()) + and ((archive and archive.exists()) or + (fatbin and fatbin.exists()))) if not solver: raise KeyError(key) - sms = CUDA_ARCH.replace("sm_", "") + "0" flags = ["--expt-relaxed-constexpr", "-DGLASS_BENCH_CUBLASDX", "-DGLASS_BENCH_CUSOLVERDX", - "-DCUSOLVERDX_IGNORE_NVBUG_5288270_ASSERT", f"-DSMS={sms}", + "-DCUSOLVERDX_IGNORE_NVBUG_5288270_ASSERT", + f"-DGLASS_TARGET_SM={target_sm}", "-I", str(mathdx / "include"), - "-I", str(mathdx / "external/cutlass/include"), - "-rdc=true", "-dlto", "-L", str(mathdx / "lib"), - "-lcusolverdx", "-lcublas", "-lcusolver", "-lcudart"] + "-I", str(mathdx / "external/cutlass/include")] + if platform.machine() == "x86_64" and archive and archive.exists(): + flags += ["-rdc=true", "-dlto", "-L", str(mathdx / "lib"), + "-lcusolverdx", "-lcublas", "-lcusolver", "-lcudart"] + else: + return compile_binary(f"test_{key}", BUILD_DIR, CUDA_ARCH, + flags, solver_fatbin=fatbin) return compile_binary(f"test_{key}", BUILD_DIR, CUDA_ARCH, flags) def __getitem__(self, key: str) -> pathlib.Path: @@ -352,6 +384,14 @@ def bin_nvidia_f64(bins): return bins["nvidia_f64"] +@pytest.fixture(scope="session") +def bin_nvidia_thread(bins): + """Per-thread cuSOLVERDx 0.4+ path, or skip without a recent MathDx.""" + if "nvidia_thread" not in bins: + pytest.skip("test_nvidia_thread needs MathDx cuSOLVERDx 0.4+") + return bins["nvidia_thread"] + + @pytest.fixture(scope="session") def bin_base_f64(bins): """Double-precision base (glass::) + warp (glass::warp::) ops.""" diff --git a/test/coverage-obligations.json b/test/coverage-obligations.json index a40d5bf..2e6cea5 100644 --- a/test/coverage-obligations.json +++ b/test/coverage-obligations.json @@ -158,6 +158,14 @@ "test/test_nvidia_dispatch.py::test_gemm_batched_indexed_atomic*" ] }, + { + "id": "nvidia_thread_lapack", + "shard": "mathdx", + "description": "Every cuSOLVERDx thread-scope LAPACK wrapper matches an independent NumPy factorization or residual oracle in f32 and f64.", + "evidence": [ + "test/test_nvidia_thread.py::test_nvidia_thread_operation*" + ] + }, { "id": "trailing_sync", "shard": "integration", diff --git a/test/cuda/test_defaults.cu b/test/cuda/test_defaults.cu index 2427ba1..b68f3de 100644 --- a/test/cuda/test_defaults.cu +++ b/test/cuda/test_defaults.cu @@ -1,80 +1,91 @@ // test_defaults.cu — compile-time validation of glass-defaults.cuh. The helpers are // constexpr, so the static_asserts ARE the test: if this compiles, the picks match the -// sweep (bench/RESULTS.md). No MathDx needed — this TU links no vendor lib, so -// suggested_backend<> exercises the no-nvidia COLLAPSE, while ideal_sm120() is checked -// directly for the nvidia-tier picks (it's availability-independent). +// sweep (bench/RESULTS.md). No MathDx is linked: recommend() still checks both +// measured dependency policies because it returns metadata only. #include #include "glass.cuh" #include "glass-defaults.cuh" -using glass::op; using glass::backend; +using glass::op; namespace gd = glass::defaults; +using backend = gd::backend; -// ── measured sm_120 ladder (the ideal tier, independent of what's linked) ── -// (2026-07-18 retune — first sweep with the THREAD contender: it takes the -// low-DOF corner of every op except gemm.) -// gemm f32: warp <=8, block 12, warp 16, block <=24, nvidia 25..32, block >=48 -// (2026-08-15 drift-fixed capture: the warp/block boundary is genuine fine -// structure — warp decisive at 8 and 16, block at 24; N=12 sits 2.03% over -// the ±2% SIMT tie band, a band-edge razor cell — see bench/tune_pick.py) +// Generated-table ordinals are serialized by archived tuner artifacts: append only. +static_assert(static_cast(backend::warp) == 0, "backend ordinal: warp"); +static_assert(static_cast(backend::block) == 1, "backend ordinal: block"); +static_assert(static_cast(backend::nvidia_block) == 2, "backend ordinal: nvidia_block"); +static_assert(static_cast(backend::thread) == 3, "backend ordinal: thread"); +static_assert(static_cast(backend::nvidia_thread) == 4, + "backend ordinal: nvidia_thread appended"); + +// ── measured sm_120 ladder (2026-08-30, independent of what's linked) ── +// The higher-repetition throughput replication agreed on 131/132 policy +// winners. The lone disagreement was dot f32 N=16 inside the SIMT tie band; +// these pins follow the 500-repetition capture used to generate the table. static_assert(gd::ideal_sm120(op::gemm, 8, false) == backend::warp, "gemm8 f32"); -static_assert(gd::ideal_sm120(op::gemm, 12, false) == backend::block, "gemm12 f32 (band-edge: block by 2.03%, just outside the +/-2% tie band)"); +static_assert(gd::ideal_sm120(op::gemm, 12, false) == backend::warp, "gemm12 f32"); static_assert(gd::ideal_sm120(op::gemm, 24, false) == backend::block, "gemm24 f32"); -static_assert(gd::ideal_sm120(op::gemm, 32, false) == backend::nvidia, "gemm32 f32"); +static_assert(gd::ideal_sm120(op::gemm, 32, false) == backend::nvidia_block, "gemm32 f32"); static_assert(gd::ideal_sm120(op::gemm, 96, false) == backend::block, "gemm96 f32 (smem cap)"); -// chol f32: thread<=6, warp<=24, nvidia>=32 (through 128); at N=24 raw nv -// wins by only 1.03x — under the ±5% MathDx-clearance margin → warp ships -// (pre-drift-fix captures had nvidia from 16 up: the vendor leg timed last, -// on drift-accelerated inputs) -static_assert(gd::ideal_sm120(op::chol, 4, false) == backend::thread, "chol4 f32"); -static_assert(gd::ideal_sm120(op::chol, 8, false) == backend::warp, "chol8 f32"); -static_assert(gd::ideal_sm120(op::chol, 24, false) == backend::warp, "chol24 f32 (nv 1.03x, under the 5% margin)"); -static_assert(gd::ideal_sm120(op::chol, 128, false) == backend::nvidia, "chol128 f32"); -// trsv f32: thread<=16, nvidia 17..32, warp above +// NVIDIA thread wins 14 throughput cells after the valid-input confirmation +// vetoes three repeated-mutation ladder picks. +static_assert(gd::ideal_sm120(op::potrf, 4, false) == backend::thread, "potrf4 f32"); +static_assert(gd::ideal_sm120(op::potrf, 8, false) == backend::nvidia_thread, "potrf8 f32 -> NVIDIA thread"); +static_assert(gd::ideal_sm120(op::potrf, 24, false) == backend::warp, "potrf24 f32"); +static_assert(gd::ideal_sm120(op::potrf, 128, false) == backend::nvidia_block, "potrf128 f32"); static_assert(gd::ideal_sm120(op::trsv, 12, false) == backend::thread, "trsv12 f32"); -static_assert(gd::ideal_sm120(op::trsv, 24, false) == backend::nvidia, "trsv24 f32"); +static_assert(gd::ideal_sm120(op::trsv, 24, false) == backend::nvidia_thread, "trsv24 f32 -> NVIDIA thread"); +static_assert(gd::ideal_sm120(op::trsv, 32, false) == backend::nvidia_block, "trsv32 f32 -> NVIDIA block"); static_assert(gd::ideal_sm120(op::trsv, 64, false) == backend::warp, "trsv64 f32"); -// dot f32: thread<=12, warp above (warp decisive by 7.5% at 16 in the -// drift-fixed capture) ; gemv: thread<=6, warp<=32, block@48 +static_assert(gd::ideal_sm120(op::trsv, 6, true) == backend::thread, + "trsv6 f64 -> native after valid-input veto"); static_assert(gd::ideal_sm120(op::dot, 8, false) == backend::thread, "dot8"); +static_assert(gd::ideal_sm120(op::dot, 16, false) == backend::warp, "dot16 higher-repetition tie verdict"); +static_assert(gd::ideal_sm120(op::dot, 24, false) == backend::thread, "dot24"); static_assert(gd::ideal_sm120(op::dot, 128, false) == backend::warp, "dot128"); static_assert(gd::ideal_sm120(op::gemv, 4, false) == backend::thread, "gemv4"); static_assert(gd::ideal_sm120(op::gemv, 32, false) == backend::warp, "gemv32"); static_assert(gd::ideal_sm120(op::gemv, 48, false) == backend::block, "gemv48"); -// f64: thread reaches N<=16 on chol/trsv/posv (block/warp f64 small-N is slow -// enough that even the spilled thread path wins); the 2026-08-15 drift-fixed -// capture moved the big-N f64 factor cells nvidia→block (block wins outright -// once every contender times pristine inputs: chol48 by 16%, posv64 by 10%) -static_assert(gd::ideal_sm120(op::chol, 8, true) == backend::thread, "chol8 f64"); -static_assert(gd::ideal_sm120(op::chol, 48, true) == backend::block, "chol48 f64 (block outright, 1.16x over nv)"); +static_assert(gd::ideal_sm120(op::potrf, 8, true) == backend::nvidia_thread, "potrf8 f64 -> NVIDIA thread"); +static_assert(gd::ideal_sm120(op::potrf, 48, true) == backend::block, "potrf48 f64"); static_assert(gd::ideal_sm120(op::gemm, 64, true) == backend::block, "gemm64 f64"); +static_assert(gd::ideal_sm120(op::posv, 8, true) == backend::nvidia_thread, "posv8 f64 -> NVIDIA thread"); +static_assert(gd::ideal_sm120(op::posv, 8, false) == backend::thread, + "posv8 f32 -> native after valid-input veto"); static_assert(gd::ideal_sm120(op::posv, 12, true) == backend::thread, "posv12 f64"); -static_assert(gd::ideal_sm120(op::posv, 64, true) == backend::block, "posv64 f64 (block 1.10x over nv; row spread 8.1%, margin clears)"); +static_assert(gd::ideal_sm120(op::posv, 64, true) == backend::block, "posv64 f64"); -// ── sm_87 (Jetson AGX Orin, 50W standard mode; mega_sweep_50W_merged.txt) ── -// The integrated-memory Orin keeps the thread tier winning further out than -// sm_120 does, and the vendor tier (reachable on Tegra only via the cuSOLVERDx -// LTO-IR fatbin device link) takes the small-N factor/solve band outright. +// ── sm_87 (Jetson AGX Orin, pinned 50W mode; 2026-08-30) ── +// The vendor thread path is linked through MathDx's architecture-neutral +// LTO-IR fatbin. The valid-input confirmation retains 15 of the original 19 +// repeated-mutation ladder winners. static_assert(gd::ideal_sm87(op::dot, 8, false) == backend::thread, "dot8 f32"); static_assert(gd::ideal_sm87(op::dot, 128, false) == backend::warp, "dot128 f32"); -static_assert(gd::ideal_sm87(op::chol, 8, false) == backend::thread, "chol8 f32"); -static_assert(gd::ideal_sm87(op::chol, 48, false) == backend::nvidia, "chol48 f32 -> vendor"); -static_assert(gd::ideal_sm87(op::posv, 32, false) == backend::nvidia, "posv32 f32 -> vendor"); +static_assert(gd::ideal_sm87(op::potrf, 8, false) == backend::nvidia_thread, "potrf8 f32 -> NVIDIA thread"); +static_assert(gd::ideal_sm87(op::potrf, 12, false) == backend::nvidia_thread, "potrf12 f32 -> NVIDIA thread"); +static_assert(gd::ideal_sm87(op::potrf, 48, false) == backend::nvidia_block, "potrf48 f32 -> vendor"); +static_assert(gd::ideal_sm87(op::trsv, 16, false) == backend::nvidia_thread, "trsv16 f32 -> NVIDIA thread"); +static_assert(gd::ideal_sm87(op::posv, 32, false) == backend::nvidia_block, "posv32 f32 -> vendor"); static_assert(gd::ideal_sm87(op::posv, 16, false) == backend::thread, "posv16 f32"); -static_assert(gd::ideal_sm87(op::gemm, 64, false) == backend::nvidia, "gemm64 f32 -> vendor"); +static_assert(gd::ideal_sm87(op::gemm, 64, false) == backend::nvidia_block, "gemm64 f32 -> vendor"); static_assert(gd::ideal_sm87(op::gemm, 64, true) == backend::warp, "gemm64 f64 (SIMT tie: warp within 1% of block to N=96)"); static_assert(gd::ideal_sm87(op::gemm, 128, true) == backend::block, "gemm128 f64 (block's only real win, 24% faster)"); -static_assert(gd::ideal_sm87(op::chol, 24, true) == backend::thread, "chol24 f64 (thread reaches further than sm_120)"); +static_assert(gd::ideal_sm87(op::potrf, 8, true) == backend::nvidia_thread, "potrf8 f64 -> NVIDIA thread"); +static_assert(gd::ideal_sm87(op::potrf, 12, true) == backend::thread, + "potrf12 f64 -> native after valid-input veto"); +static_assert(gd::ideal_sm87(op::potrf, 24, true) == backend::thread, "potrf24 f64 (thread reaches further than sm_120)"); +static_assert(gd::ideal_sm87(op::posv, 8, true) == backend::thread, + "posv8 f64 -> native after valid-input veto"); // ── per-arch dispatch: a measured SM hits its table, an unmeasured SM falls to generic ── static_assert(gd::ideal(op::gemm, 32, false, 1200u) == gd::ideal_sm120(op::gemm, 32, false), "sm_120 dispatches to its table"); static_assert(gd::ideal(op::posv, 64, true, 1200u) == gd::ideal_sm120(op::posv, 64, true), "sm_120 dispatches to its table (f64)"); -static_assert(gd::ideal(op::chol, 48, false, 870u) == gd::ideal_sm87(op::chol, 48, false), "sm_87 dispatches to its table"); +static_assert(gd::ideal(op::potrf, 48, false, 870u) == gd::ideal_sm87(op::potrf, 48, false), "sm_87 dispatches to its table"); static_assert(gd::ideal(op::posv, 64, true, 870u) == gd::ideal_sm87(op::posv, 64, true), "sm_87 dispatches to its table (f64)"); // (sentinel SMs no sweep will ever produce — a real new arch, e.g. sm_87 on Jetson, // gets its own table + dispatch case from tune.py and must NOT be asserted generic here) static_assert(gd::ideal(op::gemm, 32, false, 0u) == gd::ideal_generic(op::gemm, 32, false), "unmeasured SM falls to generic"); -static_assert(gd::ideal(op::chol, 24, false, 1u) == gd::ideal_generic(op::chol, 24, false), "unmeasured SM falls to generic"); +static_assert(gd::ideal(op::potrf, 24, false, 1u) == gd::ideal_generic(op::potrf, 24, false), "unmeasured SM falls to generic"); // ── blas2 family (warp-vs-block; tune.py blas2 leg, blas2_sweep_20260718_0327) ── static_assert(gd::blas2_sm120(op::syrk, 16, false) == backend::block, "syrk16 f32 -> block (2.2% gap just outside SIMT tie band, 2026-08-12 capture; band-edge cell)"); @@ -83,18 +94,22 @@ static_assert(gd::blas2_sm120(op::ldlt, 32, false) == backend::warp, "ldlt32 f static_assert(gd::blas2_sm120(op::ldlt, 32, true) == backend::block, "ldlt32 f64 -> block"); static_assert(gd::blas2_sm120(op::syr2k, 8, true) == backend::block, "syr2k8 f64 -> block (2.5% gap just outside SIMT tie band, 2026-08-12 capture; band-edge cell)"); static_assert(gd::ideal(op::syrk, 16, false, 1200u) == gd::blas2_sm120(op::syrk, 16, false), "blas2 ops route through ideal()"); -static_assert(gd::ideal(op::ldltsv, 32, false, 870u) == backend::block, "blas2 unmeasured arch -> block incumbent"); -static_assert(glass::suggested_backend() == backend::warp, "public picker reaches blas2 table"); +static_assert(gd::ideal(op::ldlt_solve, 32, false, 870u) == backend::block, "blas2 unmeasured arch -> block incumbent"); +static_assert(glass::recommend(glass::dependency_set::native_only, 1200u).execution_scope == glass::scope::warp, + "public plan reaches blas2 table"); // ── rect exact-shape pickers (tune.py rect leg, rect_sweep_20260718_0328) ── static_assert(gd::rect_gemv_sm120( 64, 8, false) == backend::warp, "gemv 64x8 f32 tall -> warp"); static_assert(gd::rect_gemv_sm120(128, 16, false) == backend::block, "gemv 128x16 f32 -> block"); static_assert(gd::rect_gemv_sm120(128, 16, true) == backend::warp, "gemv 128x16 f64 -> warp"); -static_assert(gd::rect_gemm_sm120( 6, 6, 64, false) == backend::block, "gemm 6x6x64 wide -> block"); -static_assert(gd::rect_gemm_sm120(32, 8, 32, false) == backend::warp, "gemm 32x8x32 -> warp"); -static_assert(glass::suggested_backend_rect_gemv<64, 8, float, 1200u>() == backend::warp, "public rect gemv picker"); -static_assert(glass::suggested_backend_rect_gemm<7, 7, 7, float, 1200u>() == backend::block, "unmeasured rect shape -> block"); -static_assert(glass::suggested_backend_rect_gemv<64, 8, float, 870u>() == backend::block, "rect unmeasured arch -> block"); +static_assert(gd::rect_gemm_sm120( 6, 64, 6, false) == backend::block, "gemm M=6,N=64,K=6 wide -> block"); +static_assert(gd::rect_gemm_sm120(32, 32, 8, false) == backend::warp, "gemm M=32,N=32,K=8 -> warp"); +static_assert(glass::recommend(glass::dependency_set::native_only, 1200u).execution_scope == glass::scope::warp, + "public rectangular GEMV plan"); +static_assert(glass::recommend(glass::dependency_set::native_only, 1200u).execution_scope == glass::scope::block, + "unmeasured rectangular GEMM shape -> block"); +static_assert(glass::recommend(glass::dependency_set::native_only, 870u).execution_scope == glass::scope::block, + "rectangular unmeasured arch -> block"); // ── bare-namespace face: measured body pins (2026-08-14 sweep, sm_120) ── // dispatch_body() now carries the measured body_sm120 table @@ -103,27 +118,27 @@ static_assert(glass::suggested_backend_rect_gemv<64, 8, float, 870u>() == backen // bounded at the largest measured N). Spot-pin the moved cells + the rule's // conservative refusals: using glass::body; -static_assert(glass::dispatch_body(op::dot, 4, false) == body::block, "dot4 f32 -> block body"); -static_assert(glass::dispatch_body(op::dot, 8, false) == body::thread_in_block, "dot8 f32 -> thread body"); -static_assert(glass::dispatch_body(op::dot, 16, false) == body::thread_in_block, "dot16 f32 -> thread body"); -static_assert(glass::dispatch_body(op::dot, 32, false) == body::warp_in_block, "dot32 f32 -> warp body"); -static_assert(glass::dispatch_body(op::dot, 64, false) == body::warp_in_block, "dot64 f32 -> warp body"); -static_assert(glass::dispatch_body(op::dot, 128, false) == body::block, "dot128 f32 BOUNDED -> block"); -static_assert(glass::dispatch_body(op::trsv, 16, false) == body::warp_in_block, "trsv16 f32 -> warp body"); -static_assert(glass::dispatch_body(op::trsv, 64, false) == body::block, "trsv64 f32 stays block"); -static_assert(glass::dispatch_body(op::posv, 4, false) == body::thread_in_block, "posv4 f32 -> thread body"); -static_assert(glass::dispatch_body(op::posv, 16, true) == body::block, "posv f64 all block"); -static_assert(glass::dispatch_body(op::eig3, 3, true) == body::thread_in_block, "eig3 f64 -> thread body"); -static_assert(glass::dispatch_body(op::eig3, 3, false) == body::block, "eig3 f32 TB-unstable -> block"); -static_assert(glass::dispatch_body(op::softmax, 16, false) == body::warp_in_block, "softmax16 f32 -> warp body"); -static_assert(glass::dispatch_body(op::softmax, 4096, false) == body::block, "softmax large-n BOUNDED -> block"); -static_assert(glass::dispatch_body(op::gemm, 16, false) == body::block, "gemm never moves"); +static_assert(glass::dispatch_body(op::dot, 4, false, 1200u) == body::block, "dot4 f32 -> block body"); +static_assert(glass::dispatch_body(op::dot, 8, false, 1200u) == body::thread_in_block, "dot8 f32 -> thread body"); +static_assert(glass::dispatch_body(op::dot, 16, false, 1200u) == body::thread_in_block, "dot16 f32 -> thread body"); +static_assert(glass::dispatch_body(op::dot, 32, false, 1200u) == body::warp_in_block, "dot32 f32 -> warp body"); +static_assert(glass::dispatch_body(op::dot, 64, false, 1200u) == body::warp_in_block, "dot64 f32 -> warp body"); +static_assert(glass::dispatch_body(op::dot, 128, false, 1200u) == body::block, "dot128 f32 BOUNDED -> block"); +static_assert(glass::dispatch_body(op::trsv, 16, false, 1200u) == body::warp_in_block, "trsv16 f32 -> warp body"); +static_assert(glass::dispatch_body(op::trsv, 64, false, 1200u) == body::block, "trsv64 f32 stays block"); +static_assert(glass::dispatch_body(op::posv, 4, false, 1200u) == body::thread_in_block, "posv4 f32 -> thread body"); +static_assert(glass::dispatch_body(op::posv, 16, true, 1200u) == body::block, "posv f64 all block"); +static_assert(glass::dispatch_body(op::eig3, 3, true, 1200u) == body::thread_in_block, "eig3 f64 -> thread body"); +static_assert(glass::dispatch_body(op::eig3, 3, false, 1200u) == body::block, "eig3 f32 TB-unstable -> block"); +static_assert(glass::dispatch_body(op::softmax, 16, false, 1200u) == body::warp_in_block, "softmax16 f32 -> warp body"); +static_assert(glass::dispatch_body(op::softmax, 4096, false, 1200u) == body::block, "softmax large-n BOUNDED -> block"); +static_assert(glass::dispatch_body(op::gemm, 16, false, 1200u) == body::block, "gemm never moves"); // sm_87 body table (body_dispatch_sweep_20260803_0936.txt, 50W, archived externally): the same rule // moves 23 cells there; softmax/eig3 land identically, dot's warp band runs wider. static_assert(glass::dispatch_body(op::dot, 8, false, 870u) == body::thread_in_block, "sm_87 dot8 -> thread body"); static_assert(glass::dispatch_body(op::dot, 32, false, 870u) == body::warp_in_block, "sm_87 dot32 -> warp body"); static_assert(glass::dispatch_body(op::dot, 128, false, 870u) == body::block, "sm_87 dot128 BOUNDED -> block"); -static_assert(glass::dispatch_body(op::chol, 16, false, 870u) == body::block, "sm_87 chol never moves"); +static_assert(glass::dispatch_body(op::potrf, 16, false, 870u) == body::block, "sm_87 potrf never moves"); static_assert(glass::dispatch_body(op::eig3, 3, true, 870u) == body::thread_in_block, "sm_87 eig3 f64 -> thread body"); static_assert(glass::dispatch_body(op::softmax, 16, false, 870u) == body::warp_in_block, "sm_87 softmax16 -> warp body"); // unmeasured arch: every cell stays the block body @@ -137,21 +152,30 @@ static_assert(&glass::symmetrize == &glass::block::symmetrize == &glass::block::warp::dot, "warp alias"); static_assert(&glass::thread::dot == &glass::block::thread::dot, "thread alias"); -// ── no-nvidia collapse (this TU links no vendor lib) ── -static_assert(glass::suggested_backend() == backend::warp, "chol24 collapses to warp"); -static_assert(glass::suggested_backend() == backend::block, "chol64 collapses to block"); -static_assert(glass::suggested_backend() == backend::block, "gemm32 collapses to block"); -static_assert(glass::suggested_backend() == backend::warp, "trsv24 collapses to warp"); -static_assert(glass::suggested_backend() == backend::warp, "dot stays warp"); -static_assert(glass::suggested_backend() == backend::block, "gemv48 stays block"); - -// ── launch-config helpers ── -static_assert(glass::suggested_block_threads() == 32u, "chol TB=32"); -static_assert(glass::suggested_block_threads() == 32u, "posv TB=32"); -static_assert(glass::suggested_block_threads() == 64u, "gemm8 TB=64"); -static_assert(glass::suggested_block_threads() == 256u, "gemm32 TB=256"); -static_assert(glass::suggested_warps_per_block() == 8u, "dot WPB=8"); -static_assert(glass::suggested_warps_per_block() == 2u, "chol WPB=2"); +// ── public dependency policies ── +constexpr auto native_potrf = glass::recommend(); +static_assert(native_potrf.implementation == glass::family::native && + native_potrf.execution_scope == glass::scope::warp && + native_potrf.block_threads == 64u && native_potrf.problems_per_block == 2u, + "native-only plan uses the measured native runner-up"); +constexpr auto mathdx_potrf = glass::recommend( + glass::dependency_set::mathdx, 1200u); +static_assert(mathdx_potrf.implementation == glass::family::nvidia && + mathdx_potrf.execution_scope == glass::scope::thread, + "MathDx plan admits the measured NVIDIA-thread winner"); +constexpr auto native_posv = glass::recommend(); +static_assert(native_posv.implementation == glass::family::native && + native_posv.execution_scope == glass::scope::thread, + "native-only plan preserves the measured native thread winner"); +constexpr auto native_gemm = glass::recommend(); +static_assert(native_gemm.implementation == glass::family::native && + native_gemm.execution_scope == glass::scope::block && + native_gemm.block_threads == 256u && native_gemm.problems_per_block == 1u, + "native-only plan includes the block launch"); +constexpr auto native_dot = glass::recommend(glass::dependency_set::native_only, 1200u); +static_assert(native_dot.execution_scope == glass::scope::thread && + native_dot.block_threads == native_dot.problems_per_block, + "thread plan packs one problem per thread"); // ── host-side query/size helpers: constexpr, so the asserts ARE the test. // Property-based (positive, monotone in threads/size) rather than exact — @@ -174,6 +198,4 @@ constexpr uint32_t k_inv_dims[] = {4u, 6u}; static_assert(glass::inv_fused_scratch_bytes(2, k_inv_dims) > 0, "K-way fused inv scratch positive"); static_assert(glass::eigh_sweeps() > glass::eigh_sweeps(), "f64 needs more Jacobi sweeps"); static_assert(glass::syev_eps() > 0 && glass::syev_eps() < glass::syev_eps(), "syev eps ordered by precision"); -static_assert(!glass::suggested_use_reduced<4, 8, 128>(), "reduced corner empty on sm_120 (bench/RESULTS.md reduced section)"); - int main() { printf("ok\n"); return 0; } diff --git a/test/cuda/test_dispatch.cu b/test/cuda/test_dispatch.cu index 81e16a6..e677864 100644 --- a/test/cuda/test_dispatch.cu +++ b/test/cuda/test_dispatch.cu @@ -220,7 +220,7 @@ static void drive_chol(const char* cell) { CUDA_CHECK(cudaMalloc(&da, N * N * sizeof(T))); CUDA_CHECK(cudaMalloc(&dout, N * N * sizeof(T))); CUDA_CHECK(cudaMemcpy(da, ha.data(), N * N * sizeof(T), cudaMemcpyHostToDevice)); - glass::body b = glass::dispatch_body(glass::op::chol, N, sizeof(T) == 8); + glass::body b = glass::dispatch_body(glass::op::potrf, N, sizeof(T) == 8); for (int tb : TBS) { std::vector r_bare(N * N), r_blk(N * N); k_chol<<<1, tb>>>(da, dout); diff --git a/test/cuda/test_l3_nvidia.cu b/test/cuda/test_l3_nvidia.cu index 2fb75ff..ecfff38 100644 --- a/test/cuda/test_l3_nvidia.cu +++ b/test/cuda/test_l3_nvidia.cu @@ -16,6 +16,12 @@ #include "helpers.cuh" #include "../../glass-nvidia.cuh" +// This binary deliberately compiles without MathDx flags. The explicit +// cuSOLVERDx thread surface must disappear cleanly while SIMT NVIDIA helpers +// remain available. +static_assert(GLASS_HAVE_CUSOLVERDX_THREAD == 0, + "MathDx thread API unexpectedly enabled in the optional-dependency build"); + static constexpr int TC = 32; // Scratch queries are host constexpr APIs. Instantiate them in host context; diff --git a/test/cuda/test_nvidia_dispatch.cu b/test/cuda/test_nvidia_dispatch.cu index 6f5f70c..c17b1ca 100644 --- a/test/cuda/test_nvidia_dispatch.cu +++ b/test/cuda/test_nvidia_dispatch.cu @@ -2,7 +2,7 @@ // // Companion to test_l3_nvidia.cu (which exercises the SIMT-only batched APIs). // This file targets the round-2 additions: -// * Gap A — glass::nvidia::gemv<> auto-dispatches SIMT vs cuBLASDx +// * Gap A — glass::nvidia::block::gemv<> auto-dispatches SIMT vs cuBLASDx // * Gap B — gemv_strided<> auto-dispatches; uses stride directly on SIMT // * Gap C — gemm_strided<> auto-dispatches; skips compact-pack on SIMT // * Gap D — gemm maps onto SIMT TRANSPOSE_B=true @@ -263,7 +263,6 @@ namespace glass { namespace nvidia { namespace block { // ── coverage pin block: the full query/size surface, constexpr so the asserts // ARE the test; plus the explicit-intent print_dispatch_* diagnostics below. ── -namespace gn = glass::nvidia; namespace gnb = glass::nvidia::block; static_assert(!gnb::should_use_cublasdx(), "f64 never routes to cuBLASDx"); static_assert(!gnb::should_use_cublasdx_gemv(), "gemv f64 -> SIMT"); @@ -274,12 +273,12 @@ static_assert(gnb::gemm_min_block_threads() > 0, "gemm min th static_assert(gnb::gemm_block_threads_valid(), "1024 threads valid for gemm16"); static_assert(gnb::gemv_min_block_threads() > 0, "gemv min threads"); static_assert(gnb::gemv_block_threads_valid(), "1024 threads valid for gemv16"); -static_assert(gn::required_smem_for_dispatch_gemm() == +static_assert(gnb::required_smem_for_dispatch_gemm() == gnb::gemm_scratch_bytes(), "explicit-intent alias == scratch"); -static_assert(gn::required_smem_for_dispatch_gemv() > 0 || - gn::required_smem_for_dispatch_gemv() == 0, "gemv dispatch smem evaluable"); -static_assert(gn::required_smem_for_dispatch_gemm_strided() >= 0u, "gemm_strided dispatch smem evaluable"); -static_assert(gn::required_smem_for_dispatch_gemv_strided() >= 0u, "gemv_strided dispatch smem evaluable"); +static_assert(gnb::required_smem_for_dispatch_gemv() > 0 || + gnb::required_smem_for_dispatch_gemv() == 0, "gemv dispatch smem evaluable"); +static_assert(gnb::required_smem_for_dispatch_gemm_strided() >= 0u, "gemm_strided dispatch smem evaluable"); +static_assert(gnb::required_smem_for_dispatch_gemv_strided() >= 0u, "gemv_strided dispatch smem evaluable"); static_assert(gnb::gemm_batched_scratch_bytes() >= 0u, "batched scratch evaluable (stub 0 without DEFINE)"); static_assert(gnb::gemm_batched_threads() > 0, "batched threads"); static_assert(gnb::gemm_batched_1d_scratch_bytes() >= 0u, "batched_1d scratch evaluable"); @@ -291,7 +290,7 @@ static_assert(gnb::gemm_strided_scratch_bytes() >= 0u, "gemm_str static_assert(gnb::gemv_strided_scratch_bytes() >= 0u, "gemv_strided scratch evaluable"); static_assert(gnb::gemv_strided_scratch_bytes() >= 0u, "gemv_strided explicit-row-stride scratch evaluable"); -static_assert(gn::reduce_scratch_bytes() > 0, "CUB reduce scratch"); +static_assert(gnb::reduce_scratch_bytes() > 0, "CUB reduce scratch"); __global__ void k_gemm_batched(float* const* A, float* const* B, float* const* C) { extern __shared__ char s[]; diff --git a/test/cuda/test_nvidia_thread.cu b/test/cuda/test_nvidia_thread.cu new file mode 100644 index 0000000..796514a --- /dev/null +++ b/test/cuda/test_nvidia_thread.cu @@ -0,0 +1,278 @@ +// Correctness runner for the cuSOLVERDx 0.4+ per-thread LAPACK surface. +// Every CUDA thread owns one packed column-major problem; pytest reconstructs +// the deterministic inputs and checks the emitted factors/solutions in NumPy. + +#include +#include +#include +#include + +#include "glass-nvidia.cuh" +#include "glass-defaults.cuh" + +static_assert(GLASS_HAVE_CUSOLVERDX_THREAD == 1, + "test_nvidia_thread requires cuSOLVERDx thread execution"); +static_assert(glass::recommend( + glass::dependency_set::mathdx, 1200u).implementation == + glass::family::nvidia && + glass::recommend( + glass::dependency_set::mathdx, 1200u).execution_scope == + glass::scope::thread, + "sm_120 measured picker reaches NVIDIA thread"); +static_assert(glass::recommend( + glass::dependency_set::mathdx, 870u).implementation == + glass::family::nvidia && + glass::recommend( + glass::dependency_set::mathdx, 870u).execution_scope == + glass::scope::thread, + "sm_87 measured picker reaches NVIDIA thread"); + +namespace gnt = glass::nvidia::thread; +constexpr int BATCHES = 7; +constexpr int THREADS = 32; + +template +__global__ void k_potrf(T* A) +{ + const int b = blockIdx.x * blockDim.x + threadIdx.x; + if (b < BATCHES) gnt::potrf(A + b * N * N); +} + +template +__global__ void k_trsm(const T* L, T* B) +{ + const int b = blockIdx.x * blockDim.x + threadIdx.x; + if (b < BATCHES) gnt::trsm(T(0.7), L + b * N * N, + B + b * N * 2); +} + +template +__global__ void k_posv(T* A, T* B) +{ + const int b = blockIdx.x * blockDim.x + threadIdx.x; + if (b < BATCHES) gnt::posv(A + b * N * N, + B + b * N * 2); +} + +template +__global__ void k_potrs(const T* L, T* B) +{ + const int b = blockIdx.x * blockDim.x + threadIdx.x; + if (b < BATCHES) gnt::potrs(L + b * N * N, + B + b * N * 2); +} + +template +__global__ void k_getrf(T* A) +{ + const int b = blockIdx.x * blockDim.x + threadIdx.x; + if (b < BATCHES) gnt::getrf_no_pivot(A + b * N * N); +} + +template +__global__ void k_getrs(T* A, T* B) +{ + const int b = blockIdx.x * blockDim.x + threadIdx.x; + if (b < BATCHES) { + T* Ab = A + b * N * N; + gnt::getrf_no_pivot(Ab); + gnt::getrs_no_pivot(Ab, B + b * N * 2); + } +} + +template +__global__ void k_gesv(T* A, T* B) +{ + const int b = blockIdx.x * blockDim.x + threadIdx.x; + if (b < BATCHES) gnt::gesv_no_pivot(A + b * N * N, + B + b * N * 2); +} + +template +__global__ void k_geqrf(T* A, T* tau) +{ + constexpr int M = N + 2; + const int b = blockIdx.x * blockDim.x + threadIdx.x; + if (b < BATCHES) gnt::geqrf(A + b * M * N, tau + b * N); +} + +template +__global__ void k_gels(T* A, T* tau, T* B) +{ + constexpr int M = N + 2; + const int b = blockIdx.x * blockDim.x + threadIdx.x; + if (b < BATCHES) gnt::gels(A + b * M * N, tau + b * N, + B + b * M * 2); +} + +template +void fill_spd(int n, std::vector& A) +{ + for (int b = 0; b < BATCHES; ++b) { + for (int j = 0; j < n; ++j) { + for (int i = 0; i < n; ++i) { + T sum = T(0); + for (int k = 0; k < n; ++k) { + const T ri = T(0.03) * T(1 + ((i + 2 * k + b) % 5)); + const T rj = T(0.03) * T(1 + ((j + 2 * k + b) % 5)); + sum += ri * rj; + } + if (i == j) sum += T(n) + T(0.2) * T(b); + A[b * n * n + i + j * n] = sum; + } + } + } +} + +template +void fill_general(int n, std::vector& A) +{ + for (int b = 0; b < BATCHES; ++b) { + for (int j = 0; j < n; ++j) { + for (int i = 0; i < n; ++i) { + T v = T(0.02) * T((i + 2 * j + 3 * b) % 7); + if (i == j) v += T(n) + T(0.25) * T(b); + A[b * n * n + i + j * n] = v; + } + } + } +} + +template +void fill_lower(int n, std::vector& L) +{ + for (int b = 0; b < BATCHES; ++b) { + for (int j = 0; j < n; ++j) { + for (int i = 0; i < n; ++i) { + T v = T(0); + if (i == j) v = T(1.5) + T(0.1) * T(i + b); + else if (i > j) v = T(0.03) * T(1 + ((i + j + b) % 5)); + L[b * n * n + i + j * n] = v; + } + } + } +} + +template +void fill_rhs(int rows, std::vector& B) +{ + for (int b = 0; b < BATCHES; ++b) + for (int j = 0; j < 2; ++j) + for (int i = 0; i < rows; ++i) + B[b * rows * 2 + i + j * rows] = + T(0.2) + T(0.04) * T((2 * i + 3 * j + b) % 6); +} + +template +void fill_rect(int m, int n, std::vector& A) +{ + for (int b = 0; b < BATCHES; ++b) { + for (int j = 0; j < n; ++j) { + for (int i = 0; i < m; ++i) { + T v = T(0.04) * T(1 + ((i + 3 * j + b) % 7)); + if (i == j) v += T(1.5) + T(0.05) * T(b); + A[b * m * n + i + j * m] = v; + } + } + } +} + +template +int run(const char* op) +{ + constexpr int M = N + 2; + std::vector hA(BATCHES * M * M, T(0)); + std::vector hB(BATCHES * M * 2, T(0)); + std::vector htau(BATCHES * N, T(0)); + + bool rectangular = !std::strcmp(op, "geqrf") || !std::strcmp(op, "gels"); + if (rectangular) fill_rect(M, N, hA); + else if (!std::strcmp(op, "potrf") || !std::strcmp(op, "posv")) fill_spd(N, hA); + else if (!std::strcmp(op, "trsm") || !std::strcmp(op, "potrs")) fill_lower(N, hA); + else fill_general(N, hA); + fill_rhs(rectangular ? M : N, hB); + + T *dA = nullptr, *dB = nullptr, *dtau = nullptr; + cudaError_t err = cudaMalloc(&dA, hA.size() * sizeof(T)); + if (err == cudaSuccess) err = cudaMalloc(&dB, hB.size() * sizeof(T)); + if (err == cudaSuccess) err = cudaMalloc(&dtau, htau.size() * sizeof(T)); + if (err == cudaSuccess) err = cudaMemcpy(dA, hA.data(), hA.size() * sizeof(T), cudaMemcpyHostToDevice); + if (err == cudaSuccess) err = cudaMemcpy(dB, hB.data(), hB.size() * sizeof(T), cudaMemcpyHostToDevice); + if (err == cudaSuccess) err = cudaMemcpy(dtau, htau.data(), htau.size() * sizeof(T), cudaMemcpyHostToDevice); + if (err != cudaSuccess) { + std::fprintf(stderr, "CUDA setup failed: %s\n", cudaGetErrorString(err)); + cudaFree(dA); cudaFree(dB); cudaFree(dtau); + return 1; + } + + bool launched = true; + if (!std::strcmp(op, "potrf")) k_potrf<<<1, THREADS>>>(dA); + else if (!std::strcmp(op, "trsm")) k_trsm<<<1, THREADS>>>(dA, dB); + else if (!std::strcmp(op, "posv")) k_posv<<<1, THREADS>>>(dA, dB); + else if constexpr (FULL_SURFACE) { + if (!std::strcmp(op, "potrs")) k_potrs<<<1, THREADS>>>(dA, dB); + else if (!std::strcmp(op, "getrf")) k_getrf<<<1, THREADS>>>(dA); + else if (!std::strcmp(op, "getrs")) k_getrs<<<1, THREADS>>>(dA, dB); + else if (!std::strcmp(op, "gesv")) k_gesv<<<1, THREADS>>>(dA, dB); + else if (!std::strcmp(op, "geqrf")) k_geqrf<<<1, THREADS>>>(dA, dtau); + else if (!std::strcmp(op, "gels")) k_gels<<<1, THREADS>>>(dA, dtau, dB); + else launched = false; + } else { + launched = false; + } + if (!launched) { + std::fprintf(stderr, "unknown operation: %s\n", op); + cudaFree(dA); cudaFree(dB); cudaFree(dtau); + return 2; + } + + err = cudaDeviceSynchronize(); + if (err != cudaSuccess) { + std::fprintf(stderr, "CUDA operation failed: %s\n", cudaGetErrorString(err)); + cudaFree(dA); cudaFree(dB); cudaFree(dtau); + return 1; + } + + const bool emit_a = !std::strcmp(op, "potrf") || !std::strcmp(op, "getrf") || + !std::strcmp(op, "geqrf"); + const int count = emit_a ? BATCHES * (rectangular ? M * N : N * N) + : BATCHES * (rectangular ? M * 2 : N * 2); + std::vector& out = emit_a ? hA : hB; + err = cudaMemcpy(out.data(), emit_a ? dA : dB, count * sizeof(T), cudaMemcpyDeviceToHost); + if (err != cudaSuccess) { + std::fprintf(stderr, "CUDA copy failed: %s\n", cudaGetErrorString(err)); + cudaFree(dA); cudaFree(dB); cudaFree(dtau); + return 1; + } + for (int i = 0; i < count; ++i) std::printf("%.17g ", static_cast(out[i])); + std::printf("\n"); + cudaFree(dA); cudaFree(dB); cudaFree(dtau); + return 0; +} + +template +int dispatch_size(const char* op, int n) +{ + if (n == 4) return run(op); + if (n == 6) return run(op); + if (n == 8) return run(op); + if (n == 12) return run(op); + if (n == 16) return run(op); + if (n == 24) return run(op); + if (n == 32) return run(op); + std::fprintf(stderr, "N must be one of 4,6,8,12,16,24,32\n"); + return 2; +} + +int main(int argc, char** argv) +{ + if (argc != 4) { + std::fprintf(stderr, "usage: %s OP <4|6|8|12|16|24|32>\n", argv[0]); + return 2; + } + const int n = std::atoi(argv[3]); + if (!std::strcmp(argv[2], "f32")) return dispatch_size(argv[1], n); + if (!std::strcmp(argv[2], "f64")) return dispatch_size(argv[1], n); + std::fprintf(stderr, "dtype must be f32 or f64\n"); + return 2; +} diff --git a/test/gpu-proof.json b/test/gpu-proof.json index 2cf492e..ee2aa2b 100644 --- a/test/gpu-proof.json +++ b/test/gpu-proof.json @@ -5,7 +5,7 @@ "devices": [ { "compute_capability": "12.0", - "driver_version": "610.43.02", + "driver_version": "610.57.04", "index": "0", "memory": "32607 MiB", "name": "NVIDIA GeForce RTX 5090", @@ -13,19 +13,19 @@ } ] }, - "platform": "Linux-7.0.0-28-generic-x86_64-with-glibc2.39", + "platform": "Linux-7.0.0-30-generic-x86_64-with-glibc2.39", "plugin_version": "0.4.0", "pytest_version": "9.1.1", "python_version": "3.12.3" }, "fingerprint": { "algorithm": "sha256-manifest-v2", - "digest": "64ca4b316c1cd769b804f5924b9d6d37b214841a0d1b67f723c0820cb25f70be", + "digest": "087f0b4341f951f27bc61d099be54029159e4c3af6a824105c507f681f5a6b26", "excluded_paths": [ "gpu-proof.json" ], "extra_paths": [], - "file_count": 133, + "file_count": 135, "included_paths": [ "glass-cgrps.cuh", "glass-defaults.cuh", @@ -39,15 +39,15 @@ }, "mode": "local", "repo": { - "branch": "main", - "commit_sha": "751d364a4d65991fb1ef9f1ba3d11619571e085c", + "branch": "feature/nvidia-thread-backend", + "commit_sha": "6f01ee827dfabde60c5686d004b00dd57e9d9dff", "dirty": false, "github_username": "plancherb1", "remote_url": "git@github.com:A2R-Lab/GLASS.git" }, "schema_version": "3", "session": { - "ended_at": "2026-08-18T03:47:44Z", + "ended_at": "2026-08-30T21:24:47Z", "node_ids": [ "test/test_l1.py::test_axpy[cg-8-normal]", "test/test_l1.py::test_axpy[cg-64-mixed]", @@ -4331,6 +4331,19 @@ "test/test_dispatch.py::test_bare_face_matches_block[posv_f32]", "test/test_dispatch.py::test_bare_face_matches_block[eig3_f64]", "test/test_dispatch.py::test_bare_face_matches_block[softmax_f32]", + "test/test_api_hygiene.py::test_nvidia_scope_is_always_explicit", + "test/test_api_hygiene.py::test_removed_advisors_do_not_reenter_public_headers", + "test/test_api_hygiene.py::test_one_target_architecture_selector", + "test/test_tuning_tools.py::test_ladder_preserves_measured_native_runner_up", + "test/test_tuning_tools.py::test_valid_input_confirmation_is_a_veto_not_a_promotion", + "test/test_tuning_tools.py::test_valid_input_confirmation_requires_every_selected_cell", + "test/test_tuning_tools.py::test_valid_input_confirmation_rejects_decision_scale_jitter", + "test/test_tuning_tools.py::test_local_override_emits_both_dependency_policies", + "test/test_tuning_tools.py::test_local_ladder_override_does_not_mask_other_tables", + "test/test_bench_common.py::test_foreign_pids_subtracts_own_and_baseline", + "test/test_bench_common.py::test_foreign_pids_all_tolerated", + "test/test_bench_common.py::test_watch_process_tolerates_baseline_pids", + "test/test_bench_common.py::test_watch_process_trips_on_new_pid", "test/test_banded.py::test_bdmv[1-2-3]", "test/test_banded.py::test_bdmv[1-6-4]", "test/test_banded.py::test_bdmv[7-2-3]", @@ -4679,6 +4692,72 @@ "test/test_nvidia_f64.py::test_getrf_getrs_no_pivot", "test/test_nvidia_f64.py::test_geqrf", "test/test_nvidia_f64.py::test_gels", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[potrf-f32-float32-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[potrf-f32-float32-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[potrf-f64-float64-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[potrf-f64-float64-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[trsm-f32-float32-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[trsm-f32-float32-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[trsm-f64-float64-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[trsm-f64-float64-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[posv-f32-float32-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[posv-f32-float32-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[posv-f64-float64-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[posv-f64-float64-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[potrs-f32-float32-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[potrs-f32-float32-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[potrs-f64-float64-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[potrs-f64-float64-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[getrf-f32-float32-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[getrf-f32-float32-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[getrf-f64-float64-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[getrf-f64-float64-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[getrs-f32-float32-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[getrs-f32-float32-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[getrs-f64-float64-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[getrs-f64-float64-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[gesv-f32-float32-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[gesv-f32-float32-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[gesv-f64-float64-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[gesv-f64-float64-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[geqrf-f32-float32-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[geqrf-f32-float32-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[geqrf-f64-float64-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[geqrf-f64-float64-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[gels-f32-float32-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[gels-f32-float32-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[gels-f64-float64-4]", + "test/test_nvidia_thread.py::test_nvidia_thread_operation[gels-f64-float64-8]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[potrf-f32-float32-6]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[potrf-f32-float32-12]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[potrf-f32-float32-16]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[potrf-f32-float32-24]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[potrf-f32-float32-32]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[potrf-f64-float64-6]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[potrf-f64-float64-12]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[potrf-f64-float64-16]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[potrf-f64-float64-24]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[potrf-f64-float64-32]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[trsm-f32-float32-6]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[trsm-f32-float32-12]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[trsm-f32-float32-16]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[trsm-f32-float32-24]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[trsm-f32-float32-32]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[trsm-f64-float64-6]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[trsm-f64-float64-12]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[trsm-f64-float64-16]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[trsm-f64-float64-24]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[trsm-f64-float64-32]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[posv-f32-float32-6]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[posv-f32-float32-12]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[posv-f32-float32-16]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[posv-f32-float32-24]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[posv-f32-float32-32]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[posv-f64-float64-6]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[posv-f64-float64-12]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[posv-f64-float64-16]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[posv-f64-float64-24]", + "test/test_nvidia_thread.py::test_nvidia_thread_timing_domain[posv-f64-float64-32]", "test/test_examples.py::test_simt_example[01_axpy_simt.cu]", "test/test_examples.py::test_simt_example[02_gemm_conventions.cu]", "test/test_examples.py::test_simt_example[03_reductions_norms.cu]", @@ -4780,6 +4859,9 @@ "test/test_warp.py", "test/test_defaults.py", "test/test_dispatch.py", + "test/test_api_hygiene.py", + "test/test_tuning_tools.py", + "test/test_bench_common.py", "-q", "--gpu-proof-enable", "--gpu-proof-out", @@ -4789,7 +4871,7 @@ "--gpu-proof-shard", "tiers", "--gpu-proof-shard-fingerprint-paths", - "glass.cuh,glass-cgrps.cuh,glass-defaults.cuh,glass-dispatch.cuh,src/base/L1,src/base/barrier.cuh,src/base/dispatch.cuh,src/base/flags.cuh,src/base/L2,src/base/L3,src/cgrps,test/conftest.py,test/cuda/helpers.cuh,test/expected_skips.txt,src/base/est/svd3.cuh,test/test_thread.py,test/test_warp.py,test/test_defaults.py,test/test_dispatch.py,test/cuda/test_thread.cu,test/cuda/test_warp.cu,test/cuda/test_defaults.cu,test/cuda/test_dispatch.cu", + "glass.cuh,glass-cgrps.cuh,glass-defaults.cuh,glass-dispatch.cuh,src/base/L1,src/base/barrier.cuh,src/base/dispatch.cuh,src/base/flags.cuh,src/base/L2,src/base/L3,src/cgrps,test/conftest.py,test/cuda/helpers.cuh,test/expected_skips.txt,src/base/est/svd3.cuh,bench/bench_common.py,bench/tune.py,bench/tune_pick.py,bench/autotune.py,test/test_thread.py,test/test_warp.py,test/test_defaults.py,test/test_dispatch.py,test/test_api_hygiene.py,test/test_tuning_tools.py,test/test_bench_common.py,test/cuda/test_thread.cu,test/cuda/test_warp.cu,test/cuda/test_defaults.cu,test/cuda/test_dispatch.cu", "--gpu-proof-fingerprint-paths", "glass.cuh,glass-cgrps.cuh,glass-nvidia.cuh,glass-defaults.cuh,glass-dispatch.cuh,src,test/cuda,test/conftest.py" ], @@ -4830,6 +4912,7 @@ [ "test/test_nvidia_dispatch.py", "test/test_nvidia_f64.py", + "test/test_nvidia_thread.py", "-q", "--gpu-proof-enable", "--gpu-proof-out", @@ -4839,7 +4922,7 @@ "--gpu-proof-shard", "mathdx", "--gpu-proof-shard-fingerprint-paths", - "glass.cuh,glass-cgrps.cuh,glass-defaults.cuh,glass-dispatch.cuh,src/base/L1,src/base/barrier.cuh,src/base/dispatch.cuh,src/base/flags.cuh,src/base/L2,src/base/L3,src/cgrps,test/conftest.py,test/cuda/helpers.cuh,test/expected_skips.txt,src/nvidia,glass-nvidia.cuh,test/test_nvidia_dispatch.py,test/test_nvidia_f64.py,test/cuda/test_nvidia_dispatch.cu,test/cuda/test_nvidia_f64.cu,test/cuda/test_l3_nvidia.cu", + "glass.cuh,glass-cgrps.cuh,glass-defaults.cuh,glass-dispatch.cuh,src/base/L1,src/base/barrier.cuh,src/base/dispatch.cuh,src/base/flags.cuh,src/base/L2,src/base/L3,src/cgrps,test/conftest.py,test/cuda/helpers.cuh,test/expected_skips.txt,src/nvidia,glass-nvidia.cuh,test/test_nvidia_dispatch.py,test/test_nvidia_f64.py,test/test_nvidia_thread.py,test/cuda/test_nvidia_dispatch.cu,test/cuda/test_nvidia_f64.cu,test/cuda/test_nvidia_thread.cu,test/cuda/test_l3_nvidia.cu", "--gpu-proof-fingerprint-paths", "glass.cuh,glass-cgrps.cuh,glass-nvidia.cuh,glass-defaults.cuh,glass-dispatch.cuh,src,test/cuda,test/conftest.py" ], @@ -4862,75 +4945,75 @@ ], "shards": [ { - "ended_at": "2026-08-18T03:01:09Z", + "ended_at": "2026-08-30T20:28:12Z", "node_count": 414, "signer": "plancherb1", "source": "vector.json", - "started_at": "2026-08-18T02:54:17Z" + "started_at": "2026-08-30T20:21:13Z" }, { - "ended_at": "2026-08-18T03:27:49Z", + "ended_at": "2026-08-30T20:57:16Z", "node_count": 1869, "signer": "plancherb1", "source": "dense.json", - "started_at": "2026-08-18T03:01:09Z" + "started_at": "2026-08-30T20:28:13Z" }, { - "ended_at": "2026-08-18T03:32:11Z", + "ended_at": "2026-08-30T21:03:28Z", "node_count": 798, "signer": "plancherb1", "source": "factor.json", - "started_at": "2026-08-18T03:27:50Z" + "started_at": "2026-08-30T20:57:17Z" }, { - "ended_at": "2026-08-18T03:44:00Z", - "node_count": 1201, + "ended_at": "2026-08-30T21:18:14Z", + "node_count": 1214, "signer": "plancherb1", "source": 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"test/test_trailing_sync.py::test_trailing_sync_surface[l1_warp_f64]", "outcome": "passed", "phase": "call" }, { "checks": [], - "duration_s": 0.1655, + "duration_s": 0.2491, "node_id": "test/test_trailing_sync.py::test_trailing_sync_surface[l3_simt_batched]", "outcome": "passed", "phase": "call" }, { "checks": [], - "duration_s": 0.1726, + "duration_s": 0.2396, "node_id": "test/test_trailing_sync.py::test_trailing_sync_surface[l3_simt_strided_batched]", "outcome": "passed", "phase": "call" }, { "checks": [], - "duration_s": 0.1643, + "duration_s": 0.241, "node_id": "test/test_trailing_sync.py::test_trailing_sync_surface[l3_factor_solve]", "outcome": "passed", "phase": "call" }, { "checks": [], - "duration_s": 0.1716, + "duration_s": 0.2374, "node_id": "test/test_trailing_sync.py::test_trailing_sync_cublasdx_gemm", "outcome": "passed", "phase": "call" diff --git a/test/run_gpu_proof.sh b/test/run_gpu_proof.sh index 45737c7..bdf919c 100755 --- a/test/run_gpu_proof.sh +++ b/test/run_gpu_proof.sh @@ -71,11 +71,12 @@ SHARD_DRIVERS[factor]="test/cuda/test_fused.cu test/cuda/test_factor_check.cu \ test/cuda/test_base_f64.cu test/cuda/test_api_factor.cu" SHARD_PATHS[factor]="$ROOTS_BASE,$DENSE_BASE,$TEST_BASE" -SHARD_FILES[tiers]="test/test_thread.py test/test_warp.py test/test_defaults.py test/test_dispatch.py" +SHARD_FILES[tiers]="test/test_thread.py test/test_warp.py test/test_defaults.py test/test_dispatch.py \ + test/test_api_hygiene.py test/test_tuning_tools.py test/test_bench_common.py" SHARD_DRIVERS[tiers]="test/cuda/test_thread.cu test/cuda/test_warp.cu \ test/cuda/test_defaults.cu test/cuda/test_dispatch.cu" # svd3.cuh: the dispatch face routes eig3 into its est/ body. -SHARD_PATHS[tiers]="$ROOTS_BASE,$DENSE_BASE,$TEST_BASE,src/base/est/svd3.cuh" +SHARD_PATHS[tiers]="$ROOTS_BASE,$DENSE_BASE,$TEST_BASE,src/base/est/svd3.cuh,bench/bench_common.py,bench/tune.py,bench/tune_pick.py,bench/autotune.py" SHARD_FILES[solvers]="test/test_banded.py test/test_bdsv.py test/test_pcg.py test/test_qp.py" SHARD_DRIVERS[solvers]="test/cuda/test_banded.cu test/cuda/test_bdsv.cu \ @@ -86,8 +87,9 @@ SHARD_FILES[robotics]="test/test_robotics.py test/test_api_robotics.py" SHARD_DRIVERS[robotics]="test/cuda/test_robotics.cu test/cuda/test_api_robotics.cu" SHARD_PATHS[robotics]="$ROOTS_BASE,$DENSE_BASE,$TEST_BASE,src/base/spatial,src/base/lie,src/base/proj,src/base/geom,src/base/est" -SHARD_FILES[mathdx]="test/test_nvidia_dispatch.py test/test_nvidia_f64.py" -SHARD_DRIVERS[mathdx]="test/cuda/test_nvidia_dispatch.cu test/cuda/test_nvidia_f64.cu test/cuda/test_l3_nvidia.cu" +SHARD_FILES[mathdx]="test/test_nvidia_dispatch.py test/test_nvidia_f64.py test/test_nvidia_thread.py" +SHARD_DRIVERS[mathdx]="test/cuda/test_nvidia_dispatch.cu test/cuda/test_nvidia_f64.cu \ + test/cuda/test_nvidia_thread.cu test/cuda/test_l3_nvidia.cu" SHARD_PATHS[mathdx]="$ROOTS_BASE,$DENSE_BASE,$TEST_BASE,src/nvidia,glass-nvidia.cuh" SHARD_FILES[integration]="test/test_examples.py test/test_trailing_sync.py" diff --git a/test/test_api_hygiene.py b/test/test_api_hygiene.py new file mode 100644 index 0000000..dec144b --- /dev/null +++ b/test/test_api_hygiene.py @@ -0,0 +1,36 @@ +"""Cheap source-level guards for the public naming contract.""" + +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[1] + + +def test_nvidia_scope_is_always_explicit(): + umbrella = (ROOT / "glass-nvidia.cuh").read_text() + assert "using namespace block;" not in umbrella + + +def test_removed_advisors_do_not_reenter_public_headers(): + public = "\n".join( + (ROOT / name).read_text() + for name in ("glass.cuh", "glass-defaults.cuh", "glass-nvidia.cuh") + ) + removed = ( + "suggested_backend", + "suggested_block_threads", + "suggested_warps_per_block", + "suggested_threads_per_block", + "suggested_use_reduced", + ) + assert not [name for name in removed if name in public] + + +def test_one_target_architecture_selector(): + dispatch = (ROOT / "glass-dispatch.cuh").read_text() + assert "GLASS_TARGET_SM" in dispatch + assert "#define SMS GLASS_TARGET_SM" in dispatch + nvidia_headers = "\n".join( + path.read_text() for path in (ROOT / "src" / "nvidia").glob("*.cuh") + ) + assert "#define SMS" not in nvidia_headers diff --git a/test/test_examples.py b/test/test_examples.py index dcc8396..05d4478 100644 --- a/test/test_examples.py +++ b/test/test_examples.py @@ -46,8 +46,10 @@ def test_nvidia_example(tmp_path): mathdx = os.environ.get("MATHDX_ROOT") if not (mathdx and (pathlib.Path(mathdx) / "include" / "cublasdx.hpp").exists()): pytest.skip("05_nvidia_gemm needs MATHDX_ROOT (cuBLASDx)") + target_sm = CUDA_ARCH.removeprefix("sm_") + "0" _compile_and_run(tmp_path, "05_nvidia_gemm.cu", extra_flags=[ - "--expt-relaxed-constexpr", "-DGLASS_BENCH_CUBLASDX", "-DSMS=860", + "--expt-relaxed-constexpr", "-DGLASS_BENCH_CUBLASDX", + f"-DGLASS_TARGET_SM={target_sm}", "-I", str(pathlib.Path(mathdx) / "include"), "-I", str(pathlib.Path(mathdx) / "external" / "cutlass" / "include"), ]) diff --git a/test/test_nvidia_dispatch.py b/test/test_nvidia_dispatch.py index e5a1c10..a2f1ef0 100644 --- a/test/test_nvidia_dispatch.py +++ b/test/test_nvidia_dispatch.py @@ -3,7 +3,7 @@ Companion to test_l3_nvidia.py (which tests the SIMT batched APIs from l3_simt.cuh). This module targets the round-2 additions: - * Gap A — glass::nvidia::gemv<> auto-dispatches SIMT vs cuBLASDx + * Gap A — glass::nvidia::block::gemv<> auto-dispatches SIMT vs cuBLASDx * Gap B — gemv_strided<> auto-dispatches; SIMT uses stride directly * Gap C — gemm_strided<> auto-dispatches; SIMT skips compact-pack * Gap D — gemm<...,LB=row_major,...> maps onto SIMT TRANSPOSE_B=true @@ -43,8 +43,8 @@ def test_dispatch_query(bin_nvidia_dispatch): rc, stdout, _ = _run(bin_nvidia_dispatch, "dispatch_q") assert rc == 0 # 6x6x6 → SIMT, 16x16x16 → cuBLASDx (matches the shipped tuning + heuristic). - assert "glass::nvidia::gemm j: + out[b, i, j] = dtype(0.03) * dtype(1 + ((i + j + b) % 5)) + return out + + +def _rhs(rows, dtype): + out = np.empty((BATCHES, rows, 2), dtype=dtype) + for b in range(BATCHES): + for i in range(rows): + for j in range(2): + out[b, i, j] = dtype(0.2) + dtype(0.04) * dtype((2 * i + 3 * j + b) % 6) + return out + + +def _rect(m, n, dtype): + out = np.empty((BATCHES, m, n), dtype=dtype) + for b in range(BATCHES): + for i in range(m): + for j in range(n): + v = dtype(0.04) * dtype(1 + ((i + 3 * j + b) % 7)) + if i == j: + v += dtype(1.5) + dtype(0.05) * dtype(b) + out[b, i, j] = v + return out + + +def _run(binary, op, precision, n): + result = subprocess.run( + [str(binary), op, precision, str(n)], capture_output=True, text=True + ) + assert result.returncode == 0, result.stderr + return np.fromstring(result.stdout, sep=" ", dtype=np.float64) + + +def _assert_operation(binary, op, precision, dtype, n): + raw = _run(binary, op, precision, n) + rtol = 4e-4 if dtype == np.float32 else 2e-11 + atol = 5e-5 if dtype == np.float32 else 2e-12 + rhs = _rhs(n, dtype).astype(np.float64) + + if op == "potrf": + got = raw.reshape(BATCHES, n, n).transpose(0, 2, 1) + original = _spd(n, dtype).astype(np.float64) + for b in range(BATCHES): + lower = np.tril(got[b]) + np.testing.assert_allclose(lower @ lower.T, original[b], rtol=rtol, atol=atol) + return + + if op == "trsm": + got = raw.reshape(BATCHES, 2, n).transpose(0, 2, 1) + lower = _lower(n, dtype).astype(np.float64) + for b in range(BATCHES): + np.testing.assert_allclose(lower[b] @ got[b], 0.7 * rhs[b], rtol=rtol, atol=atol) + return + + if op in {"posv", "potrs"}: + got = raw.reshape(BATCHES, 2, n).transpose(0, 2, 1) + if op == "posv": + matrix = _spd(n, dtype).astype(np.float64) + else: + lower = _lower(n, dtype).astype(np.float64) + matrix = lower @ lower.transpose(0, 2, 1) + for b in range(BATCHES): + np.testing.assert_allclose(matrix[b] @ got[b], rhs[b], rtol=rtol, atol=atol) + return + + if op == "getrf": + got = raw.reshape(BATCHES, n, n).transpose(0, 2, 1) + original = _general(n, dtype).astype(np.float64) + for b in range(BATCHES): + lower = np.tril(got[b], -1) + np.eye(n) + upper = np.triu(got[b]) + np.testing.assert_allclose(lower @ upper, original[b], rtol=rtol, atol=atol) + return + + if op in {"getrs", "gesv"}: + got = raw.reshape(BATCHES, 2, n).transpose(0, 2, 1) + matrix = _general(n, dtype).astype(np.float64) + for b in range(BATCHES): + np.testing.assert_allclose(matrix[b] @ got[b], rhs[b], rtol=rtol, atol=atol) + return + + m = n + 2 + matrix = _rect(m, n, dtype).astype(np.float64) + if op == "geqrf": + got = raw.reshape(BATCHES, n, m).transpose(0, 2, 1) + for b in range(BATCHES): + vendor_r = np.triu(got[b][:n, :]) + _, reference_r = np.linalg.qr(matrix[b], mode="reduced") + np.testing.assert_allclose( + np.abs(vendor_r), np.abs(reference_r), rtol=rtol, atol=atol + ) + return + + got = raw.reshape(BATCHES, 2, m).transpose(0, 2, 1)[:, :n, :] + rhs_rect = _rhs(m, dtype).astype(np.float64) + for b in range(BATCHES): + reference, *_ = np.linalg.lstsq(matrix[b], rhs_rect[b], rcond=None) + np.testing.assert_allclose(got[b], reference, rtol=rtol, atol=atol) + + +@pytest.mark.parametrize("n", [4, 8]) +@pytest.mark.parametrize("precision,dtype", [("f32", np.float32), ("f64", np.float64)]) +@pytest.mark.parametrize("op", OPS) +def test_nvidia_thread_operation(bin_nvidia_thread, op, precision, dtype, n): + _assert_operation(bin_nvidia_thread, op, precision, dtype, n) + + +@pytest.mark.parametrize("n", [6, 12, 16, 24, 32]) +@pytest.mark.parametrize("precision,dtype", [("f32", np.float32), ("f64", np.float64)]) +@pytest.mark.parametrize("op", ["potrf", "trsm", "posv"]) +def test_nvidia_thread_timing_domain(bin_nvidia_thread, op, precision, dtype, n): + """Every timing candidate is admitted by its numerical oracle first.""" + _assert_operation(bin_nvidia_thread, op, precision, dtype, n) diff --git a/test/test_tuning_tools.py b/test/test_tuning_tools.py new file mode 100644 index 0000000..759ca56 --- /dev/null +++ b/test/test_tuning_tools.py @@ -0,0 +1,97 @@ +"""CPU-only contract tests for the measured execution-plan generator.""" + +from __future__ import annotations + +import pathlib +import sys + + +ROOT = pathlib.Path(__file__).resolve().parents[1] +sys.path.insert(0, str(ROOT / "bench")) + +import autotune # noqa: E402 +import tune # noqa: E402 + + +SYNTHETIC_SWEEP = """\ +################ NPROB=8192 reps=300 dtype=f32 ################ +potrf N=8 | BLOCK | WARP | THREAD || block tb32=10.0 warp w2=8.0 thread t32=7.0 nv=6.0 nvt t32=3.0 -> NVIDIA_THREAD +""" + +SYNTHETIC_NVT_VALID = """\ +NVT_VALID op=potrf N=8 dtype=f32 nprob=8192 slots=64 block=8.0000 block_shape=128 block_spread=0.50 warp=7.5000 warp_shape=8 warp_spread=0.60 thread=7.0000 thread_shape=64 thread_spread=0.40 nvidia_thread=7.2000 nvt_shape=64 nvt_spread=0.70 +""" + + +def test_ladder_preserves_measured_native_runner_up(): + full = tune.winners_from_sweep(SYNTHETIC_SWEEP, 0.05) + native = tune.winners_from_sweep(SYNTHETIC_SWEEP, 0.05, native_only=True) + + assert full[("f32", "potrf")][8] == "nvidia_thread" + assert native[("f32", "potrf")][8] == "thread" + + +def test_valid_input_confirmation_is_a_veto_not_a_promotion(): + full = tune.winners_from_sweep(SYNTHETIC_SWEEP, 0.05) + gated, vetoes = tune.apply_nvt_valid_veto(full, SYNTHETIC_NVT_VALID, 0.05) + + assert gated[("f32", "potrf")][8] == "thread" + assert vetoes == 1 + + native_main = (SYNTHETIC_SWEEP + .replace("nv=6.0", "nv=7.5") + .replace("nvt t32=3.0", "nvt t32=7.5")) + already_native = tune.winners_from_sweep(native_main, 0.05) + gated, vetoes = tune.apply_nvt_valid_veto( + already_native, + SYNTHETIC_NVT_VALID.replace("nvidia_thread=7.2000", "nvidia_thread=2.0000"), + 0.05, + ) + assert gated[("f32", "potrf")][8] == "thread" + assert vetoes == 0 + + +def test_valid_input_confirmation_requires_every_selected_cell(): + full = tune.winners_from_sweep(SYNTHETIC_SWEEP, 0.05) + try: + tune.apply_nvt_valid_veto(full, "", 0.05) + except SystemExit as error: + assert "lacks valid-input confirmation" in str(error) + else: + raise AssertionError("missing confirmation must fail closed") + + +def test_valid_input_confirmation_rejects_decision_scale_jitter(): + full = tune.winners_from_sweep(SYNTHETIC_SWEEP, 0.05) + noisy = (SYNTHETIC_NVT_VALID + .replace("nvidia_thread=7.2000", "nvidia_thread=6.5000") + .replace("nvt_spread=0.70", "nvt_spread=5.10")) + try: + tune.apply_nvt_valid_veto(full, noisy, 0.05) + except SystemExit as error: + assert "cannot resolve" in str(error) + else: + raise AssertionError("decision-scale confirmation jitter must fail closed") + + +def test_local_override_emits_both_dependency_policies(tmp_path): + capture = tmp_path / "capture.txt" + output = tmp_path / "defaults.cuh" + capture.write_text(SYNTHETIC_SWEEP) + + autotune.emit_defaults_table(capture, output, 1200, margin=0.05) + generated = output.read_text() + + assert "bool allow_nvidia" in generated + assert "if (allow_nvidia)" in generated + assert "backend::nvidia_thread" in generated + assert "if (!allow_nvidia)" in generated + assert "backend::thread" in generated + + +def test_local_ladder_override_does_not_mask_other_tables(): + defaults = (ROOT / "glass-defaults.cuh").read_text() + blas2_dispatch = "if (is_blas2(o)) return blas2_ideal" + override = "#ifdef GLASS_DEFAULTS_HAVE_LOCAL" + + assert defaults.index(blas2_dispatch) < defaults.index(override)