From bf094b0c9cfd3e9f3d29d8ca0a201d861a59bf61 Mon Sep 17 00:00:00 2001 From: good-circle Date: Fri, 18 Sep 2026 20:55:03 +0800 Subject: [PATCH 1/2] difftest: skip REF on nemu_trap Mark NutCoreTrap commits as skip so the reference does not execute the custom-trap encoding. DiffTest still stops the sim on a0=0/1; otherwise the comparison is skipped. Forward isNutCoreTrap through in-order EXU so WBU can set skip. --- src/main/scala/nutcore/NutCoreTrap.scala | 3 +++ src/main/scala/nutcore/backend/ooo/ROB.scala | 3 ++- src/main/scala/nutcore/backend/seq/EXU.scala | 1 + src/main/scala/nutcore/backend/seq/WBU.scala | 3 ++- 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/main/scala/nutcore/NutCoreTrap.scala b/src/main/scala/nutcore/NutCoreTrap.scala index dbd327cd..570f11bd 100644 --- a/src/main/scala/nutcore/NutCoreTrap.scala +++ b/src/main/scala/nutcore/NutCoreTrap.scala @@ -25,6 +25,9 @@ object NutCoreTrap extends HasInstrType { def StateInvOpcode = 2.U def StateRunning = 3.U + // custom-trap: opcode=1101011, funct3=000. Matches NEMU nemu_trap (e.g. 0x0005006b). + // DUT executes it as add (typically rd=x0). DiffTest uses a0 to tell control + // markers (0x100/0x101, keep running) from exit codes (0/1, stop the sim). def TRAP = BitPat("b????????????_?????_000_?????_1101011") val table = Array(TRAP -> List(InstrI, FuType.alu, ALUOpType.add)) } diff --git a/src/main/scala/nutcore/backend/ooo/ROB.scala b/src/main/scala/nutcore/backend/ooo/ROB.scala index 4effc778..655672cd 100644 --- a/src/main/scala/nutcore/backend/ooo/ROB.scala +++ b/src/main/scala/nutcore/backend/ooo/ROB.scala @@ -504,7 +504,8 @@ class ROB(implicit val p: NutCoreConfig) extends NutCoreModule with HasInstrType difftest_commit.valid := (if (i == 0) retireATerm else retireMultiTerms) difftest_commit.pc := SignExt(decode(ringBufferTail)(i).cf.pc, AddrBits) difftest_commit.instr := decode(ringBufferTail)(i).cf.instr - difftest_commit.skip := isMMIO(ringBufferTail)(i) && valid(ringBufferTail)(i) + // DiffTest still stops the sim on a0=0/1; otherwise skip comparison. + difftest_commit.skip := (isMMIO(ringBufferTail)(i) || decode(ringBufferTail)(i).ctrl.isNutCoreTrap) && valid(ringBufferTail)(i) difftest_commit.isRVC := decode(ringBufferTail)(i).cf.isRVC difftest_commit.rfwen := io.wb(i).rfWen && io.wb(i).rfDest =/= 0.U // && valid(ringBufferTail)(i) && commited(ringBufferTail)(i) difftest_commit.fpwen := false.B diff --git a/src/main/scala/nutcore/backend/seq/EXU.scala b/src/main/scala/nutcore/backend/seq/EXU.scala index 428ba047..8f6f7b4a 100644 --- a/src/main/scala/nutcore/backend/seq/EXU.scala +++ b/src/main/scala/nutcore/backend/seq/EXU.scala @@ -90,6 +90,7 @@ class EXU(implicit val p: NutCoreConfig) extends NutCoreModule { o.rfWen := i.rfWen && (!lsuTlbPF && !lsu.io.loadAddrMisaligned && !lsu.io.storeAddrMisaligned || !fuValids(FuType.lsu)) && !(csr.io.wenFix && fuValids(FuType.csr)) o.rfDest := i.rfDest o.fuType := i.fuType + o.isNutCoreTrap := i.isNutCoreTrap } io.out.bits.decode.cf.pc := io.in.bits.cf.pc io.out.bits.decode.cf.instr := io.in.bits.cf.instr diff --git a/src/main/scala/nutcore/backend/seq/WBU.scala b/src/main/scala/nutcore/backend/seq/WBU.scala index 3cdaf8bb..af0fa0b3 100644 --- a/src/main/scala/nutcore/backend/seq/WBU.scala +++ b/src/main/scala/nutcore/backend/seq/WBU.scala @@ -51,7 +51,8 @@ class WBU(implicit val p: NutCoreConfig) extends NutCoreModule{ difftest_commit.valid := io.in.valid difftest_commit.pc := SignExt(io.in.bits.decode.cf.pc, AddrBits) difftest_commit.instr := io.in.bits.decode.cf.instr - difftest_commit.skip := io.in.bits.isMMIO + // DiffTest still stops the sim on a0=0/1; otherwise skip comparison. + difftest_commit.skip := io.in.bits.isMMIO || io.in.bits.decode.ctrl.isNutCoreTrap difftest_commit.isRVC := io.in.bits.decode.cf.instr(1,0)=/="b11".U difftest_commit.rfwen := io.wb.rfWen && io.wb.rfDest =/= 0.U // && valid(ringBufferTail)(i) && commited(ringBufferTail)(i) difftest_commit.fpwen := false.B From cb8e8a2e2173062b8eb99eaec91aaa0f37718878 Mon Sep 17 00:00:00 2001 From: good-circle Date: Sun, 20 Sep 2026 02:07:35 +0800 Subject: [PATCH 2/2] submodule: bump difftest for nemu_trap skip Pin OpenXiangShan/difftest to 128ace159 (circle-patch1) so control markers 0x100/0x101 keep the sim running. --- difftest | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/difftest b/difftest index 29e80f85..128ace15 160000 --- a/difftest +++ b/difftest @@ -1 +1 @@ -Subproject commit 29e80f8525735d1cb77f30fd2a3ea5eff3e6528c +Subproject commit 128ace1590f72c9ce0f3617f56dc54432aded9fa