diff --git a/.github/workflows/pages-deploy.yml b/.github/workflows/pages-deploy.yml
index 5e8d93bd..1445740d 100644
--- a/.github/workflows/pages-deploy.yml
+++ b/.github/workflows/pages-deploy.yml
@@ -6,6 +6,8 @@ on:
       - www/**
       - docs/screenshots/**
       - docs/brand/**
+      - ipynb-examples/**
+      - justfile
 
 jobs:
   build:
@@ -13,11 +15,11 @@ jobs:
     steps:
     - uses: actions/checkout@v7
     - uses: astral-sh/setup-uv@c771a70e6277c0a99b617c7a806ffedaca235ff9 # v9.0.0
-    - name: Generate pages with Sphinx
+    - name: Generate pages with Sphinx and Jupyter
       run: uv run just www
     - name: Upload static files as artifact
       id: deployment
-      uses: actions/upload-pages-artifact@v3
+      uses: actions/upload-pages-artifact@v5
       with:
         path: www/_build/html
 
@@ -35,4 +37,4 @@ jobs:
     steps:
       - name: Deploy to GitHub Pages
         id: deployment
-        uses: actions/deploy-pages@v4
+        uses: actions/deploy-pages@v5
diff --git a/.gitignore b/.gitignore
index 160d2b3c..f3b7511c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,57 +1,27 @@
 *.py[cod]
-
-# coverage
-.coverage/
-coverage.xml
-
-# C extensions
-*.so
+__pycache__
 
 # Packages
-*.egg-info
-dist
-build
-parts
-bin
-var
-sdist
-.installed.cfg
-lib
-lib64
-__pycache__
+dist/
 
 # Unit test / coverage reports
 .coverage
+coverage.xml
+
+# Apple and Windows crap
+.DS_Store
+Thumbs.db
 
-# Translations
-*.mo
+# Sphinx
+_build/
 
-# Mr Developer
-.mr.developer.cfg
-.project
-.pydevproject
+# Jupyter
+.ipynb_checkpoints
+.jupyterlite.doit.db
+_output/
 
 # pycharm
 .idea
 
-# Apple crap
-.DS_Store
-
-# Stuff specifically for PyRTL
-spice.net
-_build
-
-# Verilog files
-# There must be a very good reason for someone to add a verilog file to the repo
-.v
-
 # VS Code
 .vscode
-
-# Python venv
-pyvenv.cfg
-
-# Jupyter
-.ipynb_checkpoints
-.jupyterlite.doit.db
-_output
diff --git a/README.md b/README.md
index 1d5794f7..307c7bed 100644
--- a/README.md
+++ b/README.md
@@ -8,7 +8,7 @@ PyRTL
 [![Build Status](https://github.com/UCSBarchlab/PyRTL/actions/workflows/python-test.yml/badge.svg)](https://github.com/UCSBarchlab/PyRTL/actions/workflows/python-test.yml)
 [![Code Coverage](https://codecov.io/github/UCSBarchlab/PyRTL/coverage.svg?branch=development)](https://codecov.io/github/UCSBarchlab/PyRTL?branch=development)
 [![Documentation Status](https://readthedocs.org/projects/pyrtl/badge/?version=latest)](http://pyrtl.readthedocs.org/en/latest/?badge=latest)
-[![Binder](https://mybinder.org/badge.svg)](https://mybinder.org/v2/gh/UCSBarchlab/PyRTL/development?filepath=%2Fipynb-examples%2F)
+[![JupyterLite](https://jupyterlite.readthedocs.io/en/latest/_static/badge.svg)](http://ucsbarchlab.github.io/PyRTL/lite/index.html)
 
 PyRTL provides a collection of classes for Pythonic [register-transfer
 level](https://en.wikipedia.org/wiki/Register-transfer_level) design,
@@ -41,8 +41,8 @@ written in PyRTL.
   page](http://ucsbarchlab.github.io/PyRTL/).
 * Try the examples in the
   [`examples`](https://github.com/UCSBarchlab/PyRTL/tree/development/examples)
-  directory. You can also [try the examples on
-  MyBinder](https://mybinder.org/v2/gh/UCSBarchlab/PyRTL/development?filepath=%2Fipynb-examples%2F).
+  directory. You can also [try the examples in your
+  browser](http://ucsbarchlab.github.io/PyRTL/lite/index.html).
 * [Full reference documentation](https://pyrtl.readthedocs.io/) is available.
 
 ### Package Contents
@@ -182,10 +182,12 @@ needed. `uv` caches installed software so future `uv` invocations will be fast.
   information into annotations instead of docstrings.
 * The Sphinx-generated documentation is published to
   https://pyrtl.readthedocs.io/ .
-* PyRTL's Sphinx build process is documented in
+* PyRTL's documentation build process is documented in
   [`docs/README.md`](https://github.com/UCSBarchlab/PyRTL/blob/development/docs/README.md).
 * PyRTL's release process is documented in
   [`docs/release/README.md`](https://github.com/UCSBarchlab/PyRTL/blob/development/docs/release/README.md).
+* PyRTL's webpage build process is documented in
+  [`www/README.md`](https://github.com/UCSBarchlab/PyRTL/blob/development/www/README.md).
 
 ### Using PyRTL
 
diff --git a/examples/Makefile b/examples/Makefile
index ae614623..3fe3b081 100644
--- a/examples/Makefile
+++ b/examples/Makefile
@@ -1,9 +1,10 @@
-PYTHON=uv run
-PY_FILES=$(wildcard example*.py) introduction-to-hardware.py
-IPYNB_FILES=$(addprefix ../ipynb-examples/, $(PY_FILES:.py=.ipynb))
+PYTHON := uv run
+TO_IPYNB := tools/to_ipynb.py
+PY_FILES := $(wildcard example*.py) introduction-to-hardware.py
+IPYNB_FILES := $(addprefix ../ipynb-examples/, $(PY_FILES:.py=.ipynb))
 
 all: $(IPYNB_FILES)
 
 # Convert a PyRTL example Python script to a Jupyter notebook.
-../ipynb-examples/%.ipynb: %.py tools/to_ipynb.py
-	$(PYTHON) tools/to_ipynb.py $< $@
+../ipynb-examples/%.ipynb: %.py $(TO_IPYNB)
+	$(PYTHON) $(TO_IPYNB) $< $@
diff --git a/examples/README.md b/examples/README.md
index de2e409f..29561675 100644
--- a/examples/README.md
+++ b/examples/README.md
@@ -1,12 +1,40 @@
 # PyRTL's Examples
 
 PyRTL's examples are Python scripts that demonstrate various PyRTL features.
-These scripts can be run with `python $SCRIPT_FILE_NAME`.
 
-Each script is converted to an equivalent Jupyter notebook in the
-`ipynb-examples` directory. These conversions are done by the `to_ipynb.py`
-script in the `examples/tools` directory.
+These scripts can be run with:
 
-If you update an example script, be sure to update its corresponding Jupyter
-notebook. These updates are handled by the `Makefile` in this directory, so all
-Jupyter notebooks can be updated by running `make`.
+```shell
+$ uv run $SCRIPT_FILE
+```
+
+or interactively with:
+
+```shell
+uv run python3 -i $SCRIPT_FILE
+```
+
+PyRTL has examples in two directories:
+[`examples`](https://github.com/UCSBarchlab/PyRTL/tree/development/examples)
+and
+[`www/examples`](https://github.com/UCSBarchlab/PyRTL/tree/development/www/examples).
+
+## Generating Jupyter Notebooks
+
+Each example script is automatically converted to a Jupyter notebook in a
+corresponding `ipynb-examples` directory,
+[`ipynb-examples`](https://github.com/UCSBarchlab/PyRTL/tree/development/ipynb-examples)
+and
+[`www/ipynb-examples`](https://github.com/UCSBarchlab/PyRTL/tree/development/www/ipynb-examples).
+[`examples/tools/to_ipynb.py`](https://github.com/UCSBarchlab/PyRTL/blob/development/examples/tools/to_ipynb.py)
+does these automatic conversions. Do not manually edit the generated Jupyter
+notebooks! Any manual changes will be lost the next time someone runs
+`to_ipynb.py`.
+
+If you update an example script, re-run `to_ipynb.py` to update its
+corresponding Jupyter notebook. This process is automated with
+[`examples/Makefile`](https://github.com/UCSBarchlab/PyRTL/blob/development/examples/Makefile)
+and
+[`www/examples/Makefile`](https://github.com/UCSBarchlab/PyRTL/blob/development/www/examples/Makefile).
+Running `make` in these directories will re-generate Jupyter notebooks for any
+modified examples in their `examples` directory.
diff --git a/examples/tools/to_ipynb.py b/examples/tools/to_ipynb.py
index 2cd2f38a..2cb1fb3e 100644
--- a/examples/tools/to_ipynb.py
+++ b/examples/tools/to_ipynb.py
@@ -2,7 +2,7 @@
 
 Usage::
 
-    python to_ipynb.py example1-combologic.py example1-combologic.ipynb
+    $ uv run to_ipynb.py example1-combologic.py example1-combologic.ipynb
 
 This converts comment blocks to Markdown cells, and code blocks to code cells, with some
 PyRTL-specific transformations:
@@ -168,24 +168,27 @@ def _emit_code():
             while current_code_source[-1].rstrip() == "":
                 current_code_source = current_code_source[:-1]
 
-                for code_line in current_code_source:
-                    if not found_imports and (
-                        code_line.startswith("import pyrtl")
-                        or code_line.startswith("from pyrtl")
-                    ):
-                        found_imports = True
-                        pip_packages = "pyrtl"
-                        if "verilog" in source_name:
-                            pip_packages = "pyrtl pyparsing"
-
-                        current_code_source = [
-                            f"%pip install {pip_packages}\n",
-                            "\n",
-                            *current_code_source,
-                            "\n",
-                            "pyrtl.reset_working_block()\n",
-                        ]
-                        break
+            for code_line in current_code_source:
+                if not found_imports and (
+                    code_line.startswith("import pyrtl")
+                    or code_line.startswith("from pyrtl")
+                ):
+                    found_imports = True
+                    pip_packages = "pyrtl"
+                    if "verilog" in source_name:
+                        pip_packages = "pyrtl[blif]"
+
+                    current_code_source = [
+                        f"%pip install {pip_packages}\n",
+                        "\n",
+                        *current_code_source,
+                        "\n",
+                        "pyrtl.reset_working_block()",
+                    ]
+                    break
+
+            # Remove any trailing whitespace from the code block's last line.
+            current_code_source[-1] = current_code_source[-1].rstrip()
 
             cells.append(_code_template | {"source": current_code_source})
             current_code_source = []
diff --git a/ipynb-examples/example0-minimum-viable-hardware.ipynb b/ipynb-examples/example0-minimum-viable-hardware.ipynb
index 72d94ab3..8c37da83 100644
--- a/ipynb-examples/example0-minimum-viable-hardware.ipynb
+++ b/ipynb-examples/example0-minimum-viable-hardware.ipynb
@@ -21,7 +21,7 @@
     "\n",
     "import pyrtl\n",
     "\n",
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -43,7 +43,7 @@
     "b = pyrtl.Input(bitwidth=8, name=\"b\")\n",
     "\n",
     "q = pyrtl.Output(bitwidth=8, name=\"q\")\n",
-    "gt5 = pyrtl.Output(bitwidth=1, name=\"gt5\")\n"
+    "gt5 = pyrtl.Output(bitwidth=1, name=\"gt5\")"
    ]
   },
   {
@@ -63,7 +63,7 @@
    "source": [
     "sum = a + b  # Makes an 8-bit adder.\n",
     "q <<= sum  # Connects the adder's output to the `q` output pin.\n",
-    "gt5 <<= sum > 5  # Does a comparison and connects the result to the `gt5` output pin.\n"
+    "gt5 <<= sum > 5  # Does a comparison and connects the result to the `gt5` output pin."
    ]
   },
   {
@@ -82,7 +82,7 @@
    "outputs": [],
    "source": [
     "sim = pyrtl.Simulation()\n",
-    "sim.step_multiple({\"a\": [0, 1, 2, 3, 4], \"b\": [2, 2, 3, 3, 4]})\n"
+    "sim.step_multiple({\"a\": [0, 1, 2, 3, 4], \"b\": [2, 2, 3, 3, 4]})"
    ]
   },
   {
@@ -100,7 +100,7 @@
    },
    "outputs": [],
    "source": [
-    "sim.tracer.render_trace()\n"
+    "sim.tracer.render_trace()"
    ]
   }
  ],
diff --git a/ipynb-examples/example1-combologic.ipynb b/ipynb-examples/example1-combologic.ipynb
index 93dacf3d..9567628b 100644
--- a/ipynb-examples/example1-combologic.ipynb
+++ b/ipynb-examples/example1-combologic.ipynb
@@ -27,7 +27,7 @@
     "\n",
     "import pyrtl\n",
     "\n",
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -54,7 +54,7 @@
    },
    "outputs": [],
    "source": [
-    "temp1 = pyrtl.WireVector(bitwidth=1, name=\"temp1\")\n"
+    "temp1 = pyrtl.WireVector(bitwidth=1, name=\"temp1\")"
    ]
   },
   {
@@ -73,7 +73,7 @@
    },
    "outputs": [],
    "source": [
-    "temp2 = pyrtl.WireVector()\n"
+    "temp2 = pyrtl.WireVector()"
    ]
   },
   {
@@ -97,7 +97,7 @@
     "c = pyrtl.Input(1, \"c\")\n",
     "\n",
     "sum = pyrtl.Output(1, \"sum\")\n",
-    "carry_out = pyrtl.Output(1, \"carry_out\")\n"
+    "carry_out = pyrtl.Output(1, \"carry_out\")"
    ]
   },
   {
@@ -118,7 +118,7 @@
    },
    "outputs": [],
    "source": [
-    "sum <<= a ^ b ^ c\n"
+    "sum <<= a ^ b ^ c"
    ]
   },
   {
@@ -144,7 +144,7 @@
     "temp1 <<= a & b  # connect the result of a & b to the pre-allocated WireVector\n",
     "temp2 <<= a & c\n",
     "temp3 = b & c  # temp3 IS the result of b & c (this is the first mention of temp3)\n",
-    "carry_out <<= temp1 | temp2 | temp3\n"
+    "carry_out <<= temp1 | temp2 | temp3"
    ]
   },
   {
@@ -168,7 +168,7 @@
    "outputs": [],
    "source": [
     "print(\"--- One Bit Adder Implementation ---\")\n",
-    "print(pyrtl.working_block())\n"
+    "print(pyrtl.working_block())"
    ]
   },
   {
@@ -188,7 +188,7 @@
    },
    "outputs": [],
    "source": [
-    "sim = pyrtl.Simulation()\n"
+    "sim = pyrtl.Simulation()"
    ]
   },
   {
@@ -214,7 +214,7 @@
     "for _cycle in range(15):\n",
     "    sim.step(\n",
     "        {\"a\": random.randrange(2), \"b\": random.randrange(2), \"c\": random.randrange(2)}\n",
-    "    )\n"
+    "    )"
    ]
   },
   {
@@ -237,7 +237,7 @@
     "sim.tracer.render_trace(symbol_len=2)\n",
     "\n",
     "a_value = sim.inspect(a)\n",
-    "print(\"The latest value of 'a' was: \", a_value)\n"
+    "print(\"The latest value of 'a' was: \", a_value)"
    ]
   },
   {
@@ -277,7 +277,7 @@
     "        or python_cout != sim.tracer.trace[\"carry_out\"][cycle]\n",
     "    ):\n",
     "        msg = \"This Example is Broken!!!\"\n",
-    "        raise Exception(msg)\n"
+    "        raise Exception(msg)"
    ]
   }
  ],
diff --git a/ipynb-examples/example1.1-signed-numbers.ipynb b/ipynb-examples/example1.1-signed-numbers.ipynb
index 89206ddb..56b61315 100644
--- a/ipynb-examples/example1.1-signed-numbers.ipynb
+++ b/ipynb-examples/example1.1-signed-numbers.ipynb
@@ -26,7 +26,7 @@
     "\n",
     "import pyrtl\n",
     "\n",
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -50,7 +50,7 @@
     "b = pyrtl.Input(bitwidth=2, name=\"b\")\n",
     "\n",
     "unsigned_sum = pyrtl.Output(bitwidth=3, name=\"unsigned_sum\")\n",
-    "unsigned_sum <<= a + b\n"
+    "unsigned_sum <<= a + b"
    ]
   },
   {
@@ -74,7 +74,7 @@
     "}\n",
     "\n",
     "sim = pyrtl.Simulation()\n",
-    "sim.step_multiple(provided_inputs=unsigned_inputs)\n"
+    "sim.step_multiple(provided_inputs=unsigned_inputs)"
    ]
   },
   {
@@ -100,7 +100,7 @@
     "    \"Unsigned addition. Each cycle adds a different combination of numbers.\\n\"\n",
     "    \"unsigned_sum == a + b\"\n",
     ")\n",
-    "sim.tracer.render_trace(repr_func=int)\n"
+    "sim.tracer.render_trace(repr_func=int)"
    ]
   },
   {
@@ -136,7 +136,7 @@
     "    \"\\nsigned integers. But re-interpreting the previous trace as signed integers \\n\"\n",
     "    \"produces INCORRECT RESULTS!\"\n",
     ")\n",
-    "sim.tracer.render_trace(repr_func=pyrtl.val_to_signed_integer)\n"
+    "sim.tracer.render_trace(repr_func=pyrtl.val_to_signed_integer)"
    ]
   },
   {
@@ -164,7 +164,7 @@
     "b = pyrtl.Input(bitwidth=2, name=\"b\")\n",
     "\n",
     "signed_sum = pyrtl.Output(bitwidth=3, name=\"signed_sum\")\n",
-    "signed_sum <<= pyrtl.signed_add(a, b)\n"
+    "signed_sum <<= pyrtl.signed_add(a, b)"
    ]
   },
   {
@@ -187,7 +187,7 @@
     "    \"b\": [-2, -1, 0, 1, -2, -1, 0, 1, -2, -1, 0, 1, -2, -1, 0, 1],\n",
     "}\n",
     "sim = pyrtl.Simulation()\n",
-    "sim.step_multiple(provided_inputs=signed_inputs)\n"
+    "sim.step_multiple(provided_inputs=signed_inputs)"
    ]
   },
   {
@@ -213,7 +213,7 @@
     "    \"\\nReset the simulation and use `signed_add()` to correctly add signed integers.\\n\"\n",
     "    \"signed_sum == signed_add(a, b)\"\n",
     ")\n",
-    "sim.tracer.render_trace(repr_func=pyrtl.val_to_signed_integer)\n"
+    "sim.tracer.render_trace(repr_func=pyrtl.val_to_signed_integer)"
    ]
   },
   {
@@ -238,7 +238,7 @@
     "pyrtl.reset_working_block()\n",
     "\n",
     "a = pyrtl.Input(bitwidth=2, name=\"a\")\n",
-    "b = pyrtl.Input(bitwidth=2, name=\"b\")\n"
+    "b = pyrtl.Input(bitwidth=2, name=\"b\")"
    ]
   },
   {
@@ -267,7 +267,7 @@
     "sign_extended_sum = pyrtl.Output(bitwidth=3, name=\"sign_extended_sum\")\n",
     "extended_a = a.sign_extended(bitwidth=3)\n",
     "extended_b = b.sign_extended(bitwidth=3)\n",
-    "sign_extended_sum <<= (extended_a + extended_b).truncate(bitwidth=3)\n"
+    "sign_extended_sum <<= (extended_a + extended_b).truncate(bitwidth=3)"
    ]
   },
   {
@@ -297,7 +297,7 @@
     "    \"\\ncorrectly add signed integers with `+`.\\nsign_extended_sum == \"\n",
     "    \"(a.sign_extended(3) + b.sign_extended(3)).truncate(3)\"\n",
     ")\n",
-    "sim.tracer.render_trace(repr_func=pyrtl.val_to_signed_integer)\n"
+    "sim.tracer.render_trace(repr_func=pyrtl.val_to_signed_integer)"
    ]
   }
  ],
diff --git a/ipynb-examples/example1.2-wire-struct.ipynb b/ipynb-examples/example1.2-wire-struct.ipynb
index f1bd3e21..0ff45163 100644
--- a/ipynb-examples/example1.2-wire-struct.ipynb
+++ b/ipynb-examples/example1.2-wire-struct.ipynb
@@ -27,7 +27,7 @@
     "\n",
     "import pyrtl\n",
     "\n",
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -69,7 +69,7 @@
    },
    "outputs": [],
    "source": [
-    "pixel_in = pyrtl.Input(name=\"pixel_in\", bitwidth=24)\n"
+    "pixel_in = pyrtl.Input(name=\"pixel_in\", bitwidth=24)"
    ]
   },
   {
@@ -95,7 +95,7 @@
     "green_in = pixel_in[8:16]\n",
     "green_in.name = \"green_in\"\n",
     "blue_in = pixel_in[0:8]\n",
-    "blue_in.name = \"blue_in\"\n"
+    "blue_in.name = \"blue_in\""
    ]
   },
   {
@@ -115,7 +115,7 @@
    "source": [
     "red_out = red_in + 0x11\n",
     "green_out = green_in + 0x22\n",
-    "blue_out = blue_in + 0x33\n"
+    "blue_out = blue_in + 0x33"
    ]
   },
   {
@@ -136,7 +136,7 @@
    "source": [
     "assert red_out.bitwidth == 9\n",
     "assert green_out.bitwidth == 9\n",
-    "assert blue_out.bitwidth == 9\n"
+    "assert blue_out.bitwidth == 9"
    ]
   },
   {
@@ -160,7 +160,7 @@
     "    red_out.truncate(8), green_out.truncate(8), blue_out.truncate(8)\n",
     ")\n",
     "assert pixel_out.bitwidth == 24\n",
-    "pixel_out.name = \"pixel_out\"\n"
+    "pixel_out.name = \"pixel_out\""
    ]
   },
   {
@@ -183,7 +183,7 @@
     "sim.step_multiple(provided_inputs={\"pixel_in\": [0x112233, 0xAABBCC]})\n",
     "sim.tracer.render_trace(\n",
     "    trace_list=[\"pixel_in\", \"red_in\", \"green_in\", \"blue_in\", \"pixel_out\"]\n",
-    ")\n"
+    ")"
    ]
   },
   {
@@ -203,7 +203,7 @@
    },
    "outputs": [],
    "source": [
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -238,7 +238,7 @@
     "    # The `green` component is the 8 middle bits, indices 8..15\n",
     "    green: 8\n",
     "    # The `blue` component is the 8 least significant bits, indices 0..7\n",
-    "    blue: 8\n"
+    "    blue: 8"
    ]
   },
   {
@@ -267,7 +267,7 @@
     "assert pixel_in.bitwidth == 24\n",
     "assert pixel_in.red.bitwidth == 8\n",
     "assert pixel_in.green.bitwidth == 8\n",
-    "assert pixel_in.blue.bitwidth == 8\n"
+    "assert pixel_in.blue.bitwidth == 8"
    ]
   },
   {
@@ -289,7 +289,7 @@
    "source": [
     "red_out = pixel_in.red + 0x11\n",
     "green_out = pixel_in.green + 0x22\n",
-    "blue_out = pixel_in.blue + 0x33\n"
+    "blue_out = pixel_in.blue + 0x33"
    ]
   },
   {
@@ -312,7 +312,7 @@
    "outputs": [],
    "source": [
     "pixel_out = Pixel(name=\"pixel_out\", green=green_out, red=red_out, blue=blue_out)\n",
-    "assert pixel_out.bitwidth == 24\n"
+    "assert pixel_out.bitwidth == 24"
    ]
   },
   {
@@ -341,7 +341,7 @@
     "        \"pixel_in.blue\",\n",
     "        \"pixel_out\",\n",
     "    ]\n",
-    ")\n"
+    ")"
    ]
   },
   {
@@ -364,7 +364,7 @@
    },
    "outputs": [],
    "source": [
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -384,7 +384,7 @@
    },
    "outputs": [],
    "source": [
-    "PixelPair = pyrtl.wire_matrix(component_schema=Pixel, size=2, class_name=\"PixelPair\")\n"
+    "PixelPair = pyrtl.wire_matrix(component_schema=Pixel, size=2, class_name=\"PixelPair\")"
    ]
   },
   {
@@ -402,7 +402,7 @@
    },
    "outputs": [],
    "source": [
-    "assert inspect.isclass(PixelPair)\n"
+    "assert inspect.isclass(PixelPair)"
    ]
   },
   {
@@ -426,7 +426,7 @@
     "pixel_pair_in = PixelPair(name=\"pixel_pair_in\", concatenated_type=pyrtl.Input)\n",
     "assert pixel_pair_in.bitwidth == 48\n",
     "assert pixel_pair_in[0].bitwidth == 24\n",
-    "assert pixel_pair_in[0].red.bitwidth == 8\n"
+    "assert pixel_pair_in[0].red.bitwidth == 8"
    ]
   },
   {
@@ -452,7 +452,7 @@
     "        blue=pixel_pair_in[0].blue,\n",
     "    ),\n",
     "    pixel_pair_in[1] + 1,\n",
-    "]\n"
+    "]"
    ]
   },
   {
@@ -470,7 +470,7 @@
    },
    "outputs": [],
    "source": [
-    "pixel_pair_out = PixelPair(name=\"pixel_pair_out\", values=pixel_pair_out_values)\n"
+    "pixel_pair_out = PixelPair(name=\"pixel_pair_out\", values=pixel_pair_out_values)"
    ]
   },
   {
@@ -504,7 +504,7 @@
     "        \"pixel_pair_in[1].blue\",\n",
     "        \"pixel_pair_out\",\n",
     "    ]\n",
-    ")\n"
+    ")"
    ]
   },
   {
diff --git a/ipynb-examples/example2-counter.ipynb b/ipynb-examples/example2-counter.ipynb
index 5862a6b8..bae4263d 100644
--- a/ipynb-examples/example2-counter.ipynb
+++ b/ipynb-examples/example2-counter.ipynb
@@ -24,8 +24,7 @@
     "\n",
     "import pyrtl\n",
     "\n",
-    "\n",
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -52,7 +51,7 @@
     "    assert len(a) == len(b) == 1  # len returns the bitwidth\n",
     "    sum = a ^ b ^ carry_in\n",
     "    carry_out = a & b | a & carry_in | b & carry_in\n",
-    "    return sum, carry_out\n"
+    "    return sum, carry_out"
    ]
   },
   {
@@ -88,7 +87,7 @@
     "        return one_bit_add(a, b, carry_in)\n",
     "    lsb, ripple_carry = one_bit_add(a[0], b[0], carry_in)\n",
     "    msbits, carry_out = ripple_add(a[1:], b[1:], ripple_carry)\n",
-    "    return pyrtl.concat(msbits, lsb), carry_out\n"
+    "    return pyrtl.concat(msbits, lsb), carry_out"
    ]
   },
   {
@@ -126,7 +125,7 @@
    "source": [
     "counter = pyrtl.Register(name=\"counter\", bitwidth=3)\n",
     "sum, _carry_out = ripple_add(counter, pyrtl.Const(1))\n",
-    "counter.next <<= sum\n"
+    "counter.next <<= sum"
    ]
   },
   {
@@ -161,7 +160,7 @@
     "for cycle in range(12):\n",
     "    sim.step()\n",
     "    assert sim.inspect(\"counter\") == cycle % 8\n",
-    "sim.tracer.render_trace()\n"
+    "sim.tracer.render_trace()"
    ]
   }
  ],
diff --git a/ipynb-examples/example3-statemachine.ipynb b/ipynb-examples/example3-statemachine.ipynb
index 0dcf0c47..1b600d6d 100644
--- a/ipynb-examples/example3-statemachine.ipynb
+++ b/ipynb-examples/example3-statemachine.ipynb
@@ -25,7 +25,7 @@
     "\n",
     "import pyrtl\n",
     "\n",
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -48,7 +48,7 @@
     "req_refund = pyrtl.Input(1, \"req_refund\")\n",
     "\n",
     "dispense = pyrtl.Output(1, \"dispense\")\n",
-    "refund = pyrtl.Output(1, \"refund\")\n"
+    "refund = pyrtl.Output(1, \"refund\")"
    ]
   },
   {
@@ -72,7 +72,7 @@
     "    TOK2 = 2  # Received second token, waiting for third token.\n",
     "    TOK3 = 3  # Received third token, waiting for fourth token.\n",
     "    DISP = 4  # Received fourth token, dispense item.\n",
-    "    RFND = 5  # Issue refund.\n"
+    "    RFND = 5  # Issue refund."
    ]
   },
   {
@@ -93,7 +93,7 @@
    "outputs": [],
    "source": [
     "state = pyrtl.Register(name=\"state\", State=State)\n",
-    "assert state.bitwidth == 3\n"
+    "assert state.bitwidth == 3"
    ]
   },
   {
@@ -153,7 +153,7 @@
     "        state.next |= State.WAIT\n",
     "\n",
     "dispense <<= state == State.DISP\n",
-    "refund <<= state == State.RFND\n"
+    "refund <<= state == State.RFND"
    ]
   },
   {
@@ -206,7 +206,7 @@
    },
    "outputs": [],
    "source": [
-    "sim = pyrtl.Simulation()\n"
+    "sim = pyrtl.Simulation()"
    ]
   },
   {
@@ -227,7 +227,7 @@
    "outputs": [],
    "source": [
     "sim_inputs = {\"token_in\": \"0010100111010000\", \"req_refund\": \"1100010000000000\"}\n",
-    "sim.step_multiple(sim_inputs)\n"
+    "sim.step_multiple(sim_inputs)"
    ]
   },
   {
@@ -248,7 +248,7 @@
    "source": [
     "sim.tracer.render_trace(\n",
     "    trace_list=[\"token_in\", \"req_refund\", \"state\", \"dispense\", \"refund\"]\n",
-    ")\n"
+    ")"
    ]
   },
   {
@@ -273,7 +273,7 @@
    "source": [
     "expected_sim_outputs = {\"dispense\": \"0000000000001000\", \"refund\": \"0111001000000000\"}\n",
     "sim = pyrtl.Simulation()\n",
-    "sim.step_multiple(sim_inputs, expected_sim_outputs)\n"
+    "sim.step_multiple(sim_inputs, expected_sim_outputs)"
    ]
   }
  ],
diff --git a/ipynb-examples/example4-debuggingtools.ipynb b/ipynb-examples/example4-debuggingtools.ipynb
index 20d0b895..86d5cd16 100644
--- a/ipynb-examples/example4-debuggingtools.ipynb
+++ b/ipynb-examples/example4-debuggingtools.ipynb
@@ -28,7 +28,7 @@
     "from pyrtl.rtllib.adders import kogge_stone\n",
     "from pyrtl.rtllib.multipliers import tree_multiplier\n",
     "\n",
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -65,7 +65,7 @@
     "\n",
     "add1_out = kogge_stone(in1, in2)\n",
     "add2_out = kogge_stone(add1_out, in2)\n",
-    "out <<= add2_out\n"
+    "out <<= add2_out"
    ]
   },
   {
@@ -89,7 +89,7 @@
    "outputs": [],
    "source": [
     "debug_out = pyrtl.Output(9, \"debug_out\")\n",
-    "debug_out <<= add1_out\n"
+    "debug_out <<= add1_out"
    ]
   },
   {
@@ -113,7 +113,7 @@
     "vals3 = [random.randrange(256) for _ in range(20)]\n",
     "\n",
     "sim = pyrtl.Simulation()\n",
-    "sim.step_multiple({\"in1\": vals1, \"in2\": vals2, \"in3\": vals3})\n"
+    "sim.step_multiple({\"in1\": vals1, \"in2\": vals2, \"in3\": vals3})"
    ]
   },
   {
@@ -137,7 +137,7 @@
     "print(\"in1:       \", sim.tracer.trace[\"in1\"])\n",
     "print(\"in2:       \", sim.tracer.trace[\"in2\"])\n",
     "print(\"debug_out: \", sim.tracer.trace[\"debug_out\"])\n",
-    "print(\"\\n\")\n"
+    "print(\"\\n\")"
    ]
   },
   {
@@ -159,7 +159,7 @@
     "for cycle in range(len(vals1)):\n",
     "    actual = sim.tracer.trace[\"debug_out\"][cycle]\n",
     "    expected = sim.tracer.trace[\"in1\"][cycle] + sim.tracer.trace[\"in2\"][cycle]\n",
-    "    assert actual == expected\n"
+    "    assert actual == expected"
    ]
   },
   {
@@ -183,7 +183,7 @@
    },
    "outputs": [],
    "source": [
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -208,7 +208,7 @@
     "out1 = pyrtl.Output(8, \"out1\")\n",
     "out2 = pyrtl.Output(8, \"out2\")\n",
     "\n",
-    "multout = tree_multiplier(in1, in2)\n"
+    "multout = tree_multiplier(in1, in2)"
    ]
   },
   {
@@ -227,7 +227,7 @@
    },
    "outputs": [],
    "source": [
-    "pyrtl.probe(multout, \"std_probe\")\n"
+    "pyrtl.probe(multout, \"std_probe\")"
    ]
   },
   {
@@ -250,7 +250,7 @@
    },
    "outputs": [],
    "source": [
-    "out1 <<= pyrtl.probe(multout, \"stdout_probe\") * 2\n"
+    "out1 <<= pyrtl.probe(multout, \"stdout_probe\") * 2"
    ]
   },
   {
@@ -268,7 +268,7 @@
    },
    "outputs": [],
    "source": [
-    "pyrtl.probe(multout + 32, \"adder_probe\")\n"
+    "pyrtl.probe(multout + 32, \"adder_probe\")"
    ]
   },
   {
@@ -286,7 +286,7 @@
    },
    "outputs": [],
    "source": [
-    "pyrtl.probe(multout[2:7], \"select_probe\")\n"
+    "pyrtl.probe(multout[2:7], \"select_probe\")"
    ]
   },
   {
@@ -305,7 +305,7 @@
    },
    "outputs": [],
    "source": [
-    "out2 <<= pyrtl.probe(multout)[2:16]  # notice probe names are not absolutely necessary\n"
+    "out2 <<= pyrtl.probe(multout)[2:16]  # notice probe names are not absolutely necessary"
    ]
   },
   {
@@ -330,7 +330,7 @@
     "vals2 = [random.randrange(10) for _ in range(10)]\n",
     "\n",
     "sim = pyrtl.Simulation()\n",
-    "sim.step_multiple({\"in1\": vals1, \"in2\": vals2})\n"
+    "sim.step_multiple({\"in1\": vals1, \"in2\": vals2})"
    ]
   },
   {
@@ -351,7 +351,7 @@
    "source": [
     "print(\"---- Using Probes ----\")\n",
     "sim.tracer.render_trace(repr_func=str)\n",
-    "sim.tracer.print_trace()\n"
+    "sim.tracer.print_trace()"
    ]
   },
   {
@@ -373,7 +373,7 @@
     "print(\"\\n--- Probe w/ debugging: ---\")\n",
     "pyrtl.set_debug_mode()\n",
     "pyrtl.probe(multout - 16, \"debugsubtr_probe\")\n",
-    "pyrtl.set_debug_mode(False)\n"
+    "pyrtl.set_debug_mode(False)"
    ]
   },
   {
@@ -403,7 +403,7 @@
     "pyrtl.set_debug_mode()\n",
     "\n",
     "test_out = pyrtl.Output(9, \"test_out\")\n",
-    "test_out <<= kogge_stone(in1, in2)\n"
+    "test_out <<= kogge_stone(in1, in2)"
    ]
   },
   {
@@ -421,7 +421,7 @@
    },
    "outputs": [],
    "source": [
-    "wire_trace = test_out.init_call_stack\n"
+    "wire_trace = test_out.init_call_stack"
    ]
   },
   {
@@ -444,7 +444,7 @@
    "source": [
     "print(\"---- Stack Trace ----\")\n",
     "for frame in wire_trace:\n",
-    "    print(frame)\n"
+    "    print(frame)"
    ]
   },
   {
@@ -475,7 +475,7 @@
    },
    "outputs": [],
    "source": [
-    "dummy_wv = pyrtl.WireVector(1, name=\"blah\")\n"
+    "dummy_wv = pyrtl.WireVector(1, name=\"blah\")"
    ]
   },
   {
@@ -493,7 +493,7 @@
    },
    "outputs": [],
    "source": [
-    "dummy_wv.name = \"argh\"\n"
+    "dummy_wv.name = \"argh\""
    ]
   },
   {
@@ -513,7 +513,7 @@
    "outputs": [],
    "source": [
     "dummy_wv.my_custom_property_name = \"John Clow is great\"\n",
-    "dummy_wv.custom_value_028493 = 13\n"
+    "dummy_wv.custom_value_028493 = 13"
    ]
   },
   {
@@ -543,7 +543,7 @@
     "\n",
     "for line in graphviz_string.split(\"\\n\")[:10]:\n",
     "    print(line)\n",
-    "print(\"...\")\n"
+    "print(\"...\")"
    ]
   }
  ],
diff --git a/ipynb-examples/example5-introspection.ipynb b/ipynb-examples/example5-introspection.ipynb
index a86c0de8..a58f72bc 100644
--- a/ipynb-examples/example5-introspection.ipynb
+++ b/ipynb-examples/example5-introspection.ipynb
@@ -19,8 +19,7 @@
     "\n",
     "import pyrtl\n",
     "\n",
-    "\n",
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -76,7 +75,7 @@
     "            if next_stage not in self._pipeline_register_map:\n",
     "                self._pipeline_register_map[next_stage] = {}\n",
     "            self._pipeline_register_map[next_stage][name] = new_pipereg\n",
-    "            new_pipereg.next <<= value\n"
+    "            new_pipereg.next <<= value"
    ]
   },
   {
@@ -116,7 +115,7 @@
     "\n",
     "\n",
     "simplepipeline = SimplePipelineExample()\n",
-    "print(pyrtl.working_block())\n"
+    "print(pyrtl.working_block())"
    ]
   },
   {
@@ -136,7 +135,7 @@
    "source": [
     "sim = pyrtl.Simulation()\n",
     "sim.step_multiple({}, nsteps=15)\n",
-    "sim.tracer.render_trace()\n"
+    "sim.tracer.render_trace()"
    ]
   }
  ],
diff --git a/ipynb-examples/example6-memory.ipynb b/ipynb-examples/example6-memory.ipynb
index 0f57dc29..9a2fc8a1 100644
--- a/ipynb-examples/example6-memory.ipynb
+++ b/ipynb-examples/example6-memory.ipynb
@@ -26,7 +26,7 @@
     "\n",
     "import pyrtl\n",
     "\n",
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -49,7 +49,7 @@
    "outputs": [],
    "source": [
     "mem1 = pyrtl.MemBlock(bitwidth=32, addrwidth=3, name=\"mem1\")\n",
-    "mem2 = pyrtl.MemBlock(32, 3, \"mem2\")\n"
+    "mem2 = pyrtl.MemBlock(32, 3, \"mem2\")"
    ]
   },
   {
@@ -68,7 +68,7 @@
    "outputs": [],
    "source": [
     "waddr = pyrtl.Input(3, \"waddr\")\n",
-    "count = pyrtl.Register(3, \"count\")\n"
+    "count = pyrtl.Register(3, \"count\")"
    ]
   },
   {
@@ -89,7 +89,7 @@
    "source": [
     "wdata = pyrtl.Input(32, \"wdata\")\n",
     "we = pyrtl.Input(1, \"we\")\n",
-    "raddr = pyrtl.Input(3, \"raddr\")\n"
+    "raddr = pyrtl.Input(3, \"raddr\")"
    ]
   },
   {
@@ -109,7 +109,7 @@
    "outputs": [],
    "source": [
     "rdata1 = pyrtl.Output(32, \"rdata1\")\n",
-    "rdata2 = pyrtl.Output(32, \"rdata2\")\n"
+    "rdata2 = pyrtl.Output(32, \"rdata2\")"
    ]
   },
   {
@@ -133,7 +133,7 @@
    "outputs": [],
    "source": [
     "rdata1 <<= mem1[raddr]\n",
-    "rdata2 <<= mem2[raddr]\n"
+    "rdata2 <<= mem2[raddr]"
    ]
   },
   {
@@ -157,7 +157,7 @@
    "outputs": [],
    "source": [
     "mem1[waddr] <<= pyrtl.MemBlock.EnabledWrite(wdata, we)  # Uses input wire\n",
-    "mem2[count] <<= pyrtl.MemBlock.EnabledWrite(wdata, we)  # Uses count register\n"
+    "mem2[count] <<= pyrtl.MemBlock.EnabledWrite(wdata, we)  # Uses count register"
    ]
   },
   {
@@ -176,7 +176,7 @@
    },
    "outputs": [],
    "source": [
-    "count.next <<= pyrtl.select(we, truecase=count + 1, falsecase=count)\n"
+    "count.next <<= pyrtl.select(we, truecase=count + 1, falsecase=count)"
    ]
   },
   {
@@ -195,7 +195,7 @@
    "outputs": [],
    "source": [
     "validate = pyrtl.Output(1, \"validate\")\n",
-    "validate <<= waddr == count\n"
+    "validate <<= waddr == count"
    ]
   },
   {
@@ -220,7 +220,7 @@
     "    \"waddr\": \"00012345670000000000000000\",\n",
     "    \"wdata\": \"00123456789990000000000000\",\n",
     "    \"raddr\": \"00000000000000000123456777\",\n",
-    "}\n"
+    "}"
    ]
   },
   {
@@ -242,7 +242,7 @@
    "source": [
     "mem1_init = dict.fromkeys(range(8), 9)\n",
     "mem2_init = dict.fromkeys(range(8), 9)\n",
-    "memvals = {mem1: mem1_init, mem2: mem2_init}\n"
+    "memvals = {mem1: mem1_init, mem2: mem2_init}"
    ]
   },
   {
@@ -264,7 +264,7 @@
     "print(pyrtl.working_block())\n",
     "sim = pyrtl.Simulation(memory_value_map=memvals)\n",
     "sim.step_multiple(simvals)\n",
-    "sim.tracer.render_trace()\n"
+    "sim.tracer.render_trace()"
    ]
   },
   {
@@ -282,7 +282,7 @@
    },
    "outputs": [],
    "source": [
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -310,7 +310,7 @@
     "    return 31 - 2 * address\n",
     "\n",
     "\n",
-    "rom_data_array = [rom_data_func(a) for a in range(16)]\n"
+    "rom_data_array = [rom_data_func(a) for a in range(16)]"
    ]
   },
   {
@@ -335,7 +335,7 @@
     "rom_add_1, rom_add_2 = pyrtl.Input(4, \"rom_in\"), pyrtl.Input(4, \"rom_in_2\")\n",
     "\n",
     "rom_out_1, rom_out_2 = pyrtl.Output(5, \"rom_out_1\"), pyrtl.Output(5, \"rom_out_2\")\n",
-    "rom_out_3, cmp_out = pyrtl.Output(5, \"rom_out_3\"), pyrtl.Output(1, \"cmp_out\")\n"
+    "rom_out_3, cmp_out = pyrtl.Output(5, \"rom_out_3\"), pyrtl.Output(1, \"cmp_out\")"
    ]
   },
   {
@@ -358,7 +358,7 @@
     "temp1 = rom1[rom_add_1]\n",
     "temp2 = rom2[rom_add_1]\n",
     "\n",
-    "rom_out_3 <<= rom2[rom_add_2]\n"
+    "rom_out_3 <<= rom2[rom_add_2]"
    ]
   },
   {
@@ -379,7 +379,7 @@
     "rom_out_1 <<= temp1\n",
     "rom_out_2 <<= temp2\n",
     "\n",
-    "cmp_out <<= temp1 == temp2\n"
+    "cmp_out <<= temp1 == temp2"
    ]
   },
   {
@@ -400,7 +400,7 @@
    "source": [
     "print(\"\\n---------RomBlocks----------\")\n",
     "print(pyrtl.working_block())\n",
-    "random.seed(4839483)\n"
+    "random.seed(4839483)"
    ]
   },
   {
@@ -423,7 +423,7 @@
     "simvals = {\n",
     "    \"rom_in\": [1, 11, 4, 2, 7, 8, 2, 4, 5, 13, 15, 3, 4, 4, 4, 8, 12, 13, 2, 1],\n",
     "    \"rom_in_2\": [random.randrange(16) for i in range(20)],\n",
-    "}\n"
+    "}"
    ]
   },
   {
@@ -445,7 +445,7 @@
    "source": [
     "sim = pyrtl.Simulation()\n",
     "sim.step_multiple(simvals)\n",
-    "sim.tracer.render_trace()\n"
+    "sim.tracer.render_trace()"
    ]
   }
  ],
diff --git a/ipynb-examples/example7-synth-timing.ipynb b/ipynb-examples/example7-synth-timing.ipynb
index af2ade16..93c94197 100644
--- a/ipynb-examples/example7-synth-timing.ipynb
+++ b/ipynb-examples/example7-synth-timing.ipynb
@@ -22,7 +22,7 @@
     "\n",
     "import pyrtl\n",
     "\n",
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -49,7 +49,7 @@
     "const_wire = pyrtl.Const(6, bitwidth=4)\n",
     "in_wire2 = pyrtl.Input(bitwidth=4, name=\"input2\")\n",
     "out_wire = pyrtl.Output(bitwidth=5, name=\"output\")\n",
-    "out_wire <<= const_wire + in_wire2\n"
+    "out_wire <<= const_wire + in_wire2"
    ]
   },
   {
@@ -71,7 +71,7 @@
    "source": [
     "print(\"Pre Synthesis:\")\n",
     "timing = pyrtl.TimingAnalysis()\n",
-    "timing.print_max_length()\n"
+    "timing.print_max_length()"
    ]
   },
   {
@@ -89,7 +89,7 @@
    },
    "outputs": [],
    "source": [
-    "critical_path_info = timing.critical_path()\n"
+    "critical_path_info = timing.critical_path()"
    ]
   },
   {
@@ -112,7 +112,7 @@
    "source": [
     "logic_area, mem_area = pyrtl.area_estimation(tech_in_nm=65)\n",
     "est_area = logic_area + mem_area\n",
-    "print(\"Estimated Area of block\", est_area, \"sq mm\")\n"
+    "print(\"Estimated Area of block\", est_area, \"sq mm\")"
    ]
   },
   {
@@ -144,7 +144,7 @@
     "timing = pyrtl.TimingAnalysis()\n",
     "timing.print_max_length()\n",
     "for net in pyrtl.working_block().logic:\n",
-    "    print(str(net))\n"
+    "    print(str(net))"
    ]
   },
   {
@@ -165,7 +165,7 @@
    },
    "outputs": [],
    "source": [
-    "_ = pyrtl.optimize()\n"
+    "_ = pyrtl.optimize()"
    ]
   },
   {
@@ -188,7 +188,7 @@
     "timing.print_max_length()\n",
     "\n",
     "for net in pyrtl.working_block().logic:\n",
-    "    print(str(net))\n"
+    "    print(str(net))"
    ]
   },
   {
diff --git a/ipynb-examples/example8-verilog.ipynb b/ipynb-examples/example8-verilog.ipynb
index 3e566613..c0c08bac 100644
--- a/ipynb-examples/example8-verilog.ipynb
+++ b/ipynb-examples/example8-verilog.ipynb
@@ -18,14 +18,14 @@
    },
    "outputs": [],
    "source": [
-    "%pip install pyrtl pyparsing\n",
+    "%pip install pyrtl[blif]\n",
     "\n",
     "import io\n",
     "import random\n",
     "\n",
     "import pyrtl\n",
     "\n",
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -91,7 +91,7 @@
     ".end\n",
     "\"\"\"\n",
     "\n",
-    "pyrtl.input_from_blif(full_adder_blif)\n"
+    "pyrtl.input_from_blif(full_adder_blif)"
    ]
   },
   {
@@ -109,7 +109,7 @@
    },
    "outputs": [],
    "source": [
-    "x, y, cin = [pyrtl.working_block().get_wirevector_by_name(s) for s in [\"x\", \"y\", \"cin\"]]\n"
+    "x, y, cin = [pyrtl.working_block().get_wirevector_by_name(s) for s in [\"x\", \"y\", \"cin\"]]"
    ]
   },
   {
@@ -131,7 +131,7 @@
     "for _cycle in range(15):\n",
     "    sim.step(\n",
     "        {\"x\": random.randrange(2), \"y\": random.randrange(2), \"cin\": random.randrange(2)}\n",
-    "    )\n"
+    "    )"
    ]
   },
   {
@@ -149,7 +149,7 @@
    },
    "outputs": [],
    "source": [
-    "sim.tracer.render_trace(trace_list=[\"x\", \"y\", \"cin\", \"sum\", \"cout\"], symbol_len=2)\n"
+    "sim.tracer.render_trace(trace_list=[\"x\", \"y\", \"cin\", \"sum\", \"cout\"], symbol_len=2)"
    ]
   },
   {
@@ -176,7 +176,7 @@
     "counter_output = pyrtl.Output(3, \"counter_output\")\n",
     "counter = pyrtl.Register(3, \"counter\")\n",
     "counter.next <<= pyrtl.select(zero, 0, counter + 1)\n",
-    "counter_output <<= counter\n"
+    "counter_output <<= counter"
    ]
   },
   {
@@ -212,7 +212,7 @@
     "sim = pyrtl.Simulation(tracer=pyrtl.SimulationTrace([counter_output, zero]))\n",
     "for _cycle in range(15):\n",
     "    sim.step({\"zero\": random.choice([0, 0, 0, 1])})\n",
-    "sim.tracer.render_trace()\n"
+    "sim.tracer.render_trace()"
    ]
   },
   {
@@ -242,7 +242,7 @@
     "        if i == 10:\n",
     "            break\n",
     "        print(line)\n",
-    "    print(\"...\")\n"
+    "    print(\"...\")"
    ]
   },
   {
@@ -275,7 +275,7 @@
     "\n",
     "with io.StringIO() as verilog_file:\n",
     "    pyrtl.output_to_verilog(verilog_file)\n",
-    "    print(verilog_file.getvalue())\n"
+    "    print(verilog_file.getvalue())"
    ]
   }
  ],
diff --git a/ipynb-examples/introduction-to-hardware.ipynb b/ipynb-examples/introduction-to-hardware.ipynb
index 3b538dbd..732e2f5d 100644
--- a/ipynb-examples/introduction-to-hardware.ipynb
+++ b/ipynb-examples/introduction-to-hardware.ipynb
@@ -28,8 +28,7 @@
     "\n",
     "import pyrtl\n",
     "\n",
-    "\n",
-    "pyrtl.reset_working_block()\n"
+    "pyrtl.reset_working_block()"
    ]
   },
   {
@@ -53,7 +52,7 @@
     "    b = 1\n",
     "    for _ in range(n):\n",
     "        a, b = b, a + b\n",
-    "    return a\n"
+    "    return a"
    ]
   },
   {
@@ -75,7 +74,7 @@
     "print(\"n   software_fibonacci(n)\")\n",
     "print(\"-------------------------\")\n",
     "for n in range(10):\n",
-    "    print(n, \" \", software_fibonacci(n))\n"
+    "    print(n, \" \", software_fibonacci(n))"
    ]
   },
   {
@@ -101,7 +100,7 @@
     "    b = pyrtl.Const(1)\n",
     "    for _ in range(n):\n",
     "        a, b = b, a + b\n",
-    "    return a\n"
+    "    return a"
    ]
   },
   {
@@ -171,7 +170,7 @@
     "    a.next <<= b\n",
     "    b.next <<= a + b\n",
     "\n",
-    "    return a\n"
+    "    return a"
    ]
   },
   {
@@ -236,7 +235,7 @@
     "    a.next <<= b\n",
     "    b.next <<= a + b\n",
     "\n",
-    "    return a, counter == n\n"
+    "    return a, counter == n"
    ]
   },
   {
@@ -288,7 +287,7 @@
     "            a.next |= b\n",
     "            b.next |= a + b\n",
     "    local_done <<= counter == local_n\n",
-    "    return a, local_done\n"
+    "    return a, local_done"
    ]
   },
   {
@@ -336,7 +335,7 @@
     "    trace_list=[\"n\", \"start\", \"counter\", \"fib\", \"done\"], repr_func=int\n",
     ")\n",
     "\n",
-    "assert sim.inspect(\"fib\") == software_fibonacci(7)\n"
+    "assert sim.inspect(\"fib\") == software_fibonacci(7)"
    ]
   }
  ],
diff --git a/justfile b/justfile
index 589d844c..dbb85d0e 100644
--- a/justfile
+++ b/justfile
@@ -41,7 +41,7 @@ docs:
         uv run sphinx-build -M html docs/ docs/_build
 
 www:
-        # Run `sphinx-build` to generate github.io webpage.
+        # Run `sphinx-build` to generate PyRTL's webpage.
         #
         # Output: www/_build/html/index.html
         uv run sphinx-build -M html www/ www/_build
diff --git a/pyproject.toml b/pyproject.toml
index 8127d23c..8eb5b98e 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -55,7 +55,7 @@ Changelog = "https://github.com/UCSBarchlab/PyRTL/blob/development/CHANGELOG.md"
 source = "vcs"
 
 [tool.ruff]
-exclude = ["ipynb-examples"]
+exclude = ["ipynb-examples", "docs/_build", "www/_build", "www/ipynb-examples"]
 
 [tool.ruff.lint]
 # See https://docs.astral.sh/ruff/rules/
@@ -118,6 +118,8 @@ ignore = [
 dev = [
     "furo>=2025.9.25",
     "graphviz>=0.21",
+    "jupyterlite-pyodide-kernel<0.8",
+    "jupyterlite-sphinx>=0.9.3",
     "pyparsing>=3.2.5",
     "pytest>=8.4.2",
     "pytest-cov>=7.0.0",
diff --git a/uv.lock b/uv.lock
index b5094515..123fb96d 100644
--- a/uv.lock
+++ b/uv.lock
@@ -2,7 +2,8 @@ version = 1
 revision = 3
 requires-python = ">=3.10"
 resolution-markers = [
-    "python_full_version >= '3.12'",
+    "python_full_version >= '3.14'",
+    "python_full_version >= '3.12' and python_full_version < '3.14'",
     "python_full_version == '3.11.*'",
     "python_full_version < '3.11'",
 ]
@@ -28,6 +29,90 @@ wheels = [
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 ]
 
+[[package]]
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+version = "4.14.2"
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 source = { registry = "https://pypi.org/simple" }
 resolution-markers = [
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+    "python_full_version >= '3.12' and python_full_version < '3.14'",
 ]
 dependencies = [
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@@ -811,7 +1991,8 @@ name = "sphinx-autodoc-typehints"
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 source = { registry = "https://pypi.org/simple" }
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 name = "urllib3"
 version = "2.7.0"
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diff --git a/www/README.md b/www/README.md
index 39eef71c..52407b96 100644
--- a/www/README.md
+++ b/www/README.md
@@ -32,6 +32,18 @@ $ uv run just www
 This builds a local copy of PyRTL's webpage in `www/_build/html`.
 `www/_build/html/index.html` is the home page.
 
+## Running JupyterLite Examples
+
+The generated page in `www/_build/html/index.html` can be viewed in any web
+browser, but the JupyterLite examples won't work unless you run a web server:
+
+```shell
+$ cd www/_build/html/
+$ uv run python3 -m http.server
+```
+
+Then open the URL displayed in your terminal.
+
 ## GitHub Actions Workflow
 
 When a commit is pushed that changes `www/`, the
diff --git a/www/_static/custom.css b/www/_static/custom.css
index 99111e82..cacb219c 100644
--- a/www/_static/custom.css
+++ b/www/_static/custom.css
@@ -64,6 +64,22 @@ a code {
     --sd-color-secondary-highlight: #7a8e9c;
     --sd-color-tabs-underline: rgba(222, 222, 222, 0);
 }
+/* "Try this example in your browser" buttons. */
+.try_examples_button {
+    font-family: "Open Sans", "Helvetica Neue", Helvetica, Arial, sans-serif;
+    font-size: 1rem;
+    color: white;
+    background-color: #6a7e8c;
+    border: none;
+    padding: 6px 12px;
+    border-radius: 5px;
+    margin-bottom: 5px;
+    box-shadow: 0 2px 5px rgba(108,108,108,0.2);
+}
+.try_examples_button:hover {
+    background-color: #7a8e9c;
+    box-shadow: 0 2px 5px rgba(0, 0, 0, 0.2);
+}
 
 /* Hero banner. */
 div.document {
diff --git a/www/conf.py b/www/conf.py
index 330b3661..a43fb3db 100644
--- a/www/conf.py
+++ b/www/conf.py
@@ -15,7 +15,12 @@
 # Add any Sphinx extension module names here, as strings. They can be
 # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
 # ones.
-extensions = ["sphinx.ext.intersphinx", "sphinx_copybutton", "sphinx_design"]
+extensions = [
+    "jupyterlite_sphinx",
+    "sphinx.ext.intersphinx",
+    "sphinx_copybutton",
+    "sphinx_design",
+]
 
 # Add any paths that contain templates here, relative to this directory.
 templates_path = ["_templates"]
@@ -23,7 +28,7 @@
 # List of patterns, relative to source directory, that match files and
 # directories to ignore when looking for source files.
 # This pattern also affects html_static_path and html_extra_path.
-exclude_patterns = ["_build", "Thumbs.db", ".DS_Store"]
+exclude_patterns = ["examples", "ipynb-examples", "_build", "Thumbs.db", ".DS_Store"]
 
 # Enable links to Python standard library classes (str, list, dict, etc).
 intersphinx_mapping = {
@@ -31,6 +36,8 @@
     "pyrtl": ("https://pyrtl.readthedocs.io/en/latest/", None),
 }
 
+jupyterlite_contents = "../ipynb-examples"
+
 # -- Options for HTML output -------------------------------------------------
 
 # The theme to use for HTML and HTML Help pages.  See the documentation for
@@ -49,3 +56,4 @@
 html_show_copyright = False
 html_show_sourcelink = False
 html_static_path = ["_static"]
+html_css_files = ["custom.css"]
diff --git a/www/examples/Makefile b/www/examples/Makefile
new file mode 100644
index 00000000..2ae421ce
--- /dev/null
+++ b/www/examples/Makefile
@@ -0,0 +1,10 @@
+PYTHON := uv run
+TO_IPYNB := ../../examples/tools/to_ipynb.py
+PY_FILES := $(wildcard example*.py)
+IPYNB_FILES := $(addprefix ../ipynb-examples/, $(PY_FILES:.py=.ipynb))
+
+all: $(IPYNB_FILES)
+
+# Convert a PyRTL example Python script to a Jupyter notebook.
+../ipynb-examples/%.ipynb: %.py $(TO_IPYNB)
+	$(PYTHON) $(TO_IPYNB) $< $@
diff --git a/www/examples/README.md b/www/examples/README.md
new file mode 100644
index 00000000..393b8019
--- /dev/null
+++ b/www/examples/README.md
@@ -0,0 +1,6 @@
+# PyRTL's Webpage Examples
+
+See the main
+[`examples`](https://github.com/UCSBarchlab/PyRTL/tree/development/examples)
+documentation in
+[`examples/README.md`](https://github.com/UCSBarchlab/PyRTL/blob/development/examples/README.md).
diff --git a/www/examples/example-adder.py b/www/examples/example-adder.py
index 4b17638a..cf072006 100644
--- a/www/examples/example-adder.py
+++ b/www/examples/example-adder.py
@@ -1,5 +1,7 @@
 import pyrtl
 
+# # Ripple-carry adder example.
+
 
 def fa(
     x: pyrtl.WireVector, y: pyrtl.WireVector, cin: pyrtl.WireVector
@@ -32,6 +34,7 @@ def adder(
 sum_, cout_ = adder(a, b, pyrtl.Const(0))
 sum <<= sum_
 
+# Simulate the design.
 sim = pyrtl.Simulation()
 sim.step_multiple({"a": [1, 2, 3], "b": [2, 3, 4]})
 sim.tracer.render_trace()
diff --git a/www/examples/example-fir.py b/www/examples/example-fir.py
index 81d72e02..bf708882 100644
--- a/www/examples/example-fir.py
+++ b/www/examples/example-fir.py
@@ -1,5 +1,7 @@
 import pyrtl
 
+# # Finite impulse filter example.
+
 
 def fir(x: pyrtl.WireVector, bs: list[int]):
     rwidth = x.bitwidth  # Bitwidth of the registers.
@@ -17,6 +19,7 @@ def fir(x: pyrtl.WireVector, bs: list[int]):
 y = pyrtl.Output(name="y", bitwidth=8)
 y <<= fir(x, bs=[0, 1])
 
+# Simulate the design.
 sim = pyrtl.Simulation()
 sim.step_multiple({"x": [0, 9, 18, 8, 17, 7, 16, 6, 15, 5]})
 sim.tracer.render_trace()
diff --git a/www/examples/example-gcd.py b/www/examples/example-gcd.py
index 5a78cad9..7be6a141 100644
--- a/www/examples/example-gcd.py
+++ b/www/examples/example-gcd.py
@@ -1,5 +1,7 @@
 import pyrtl
 
+# # Greatest common denominator example.
+
 
 def gcd(
     a: pyrtl.WireVector, b: pyrtl.WireVector, begin: pyrtl.WireVector
@@ -32,6 +34,7 @@ def gcd(
 x <<= x_
 done <<= done_
 
+# Simulate the design.
 sim = pyrtl.Simulation()
 sim.step({"a": 12, "b": 9, "begin": True})
 while not sim.inspect("done"):
diff --git a/www/examples/example-maxn.py b/www/examples/example-maxn.py
index cec198ac..6c17b3d3 100644
--- a/www/examples/example-maxn.py
+++ b/www/examples/example-maxn.py
@@ -2,6 +2,8 @@
 
 import pyrtl
 
+# # N-way max example.
+
 
 def max_n(*inputs):
     def max_2(x, y):
@@ -17,6 +19,7 @@ def max_2(x, y):
 
 max <<= max_n(a, b, c)
 
+# Simulate the design.
 sim = pyrtl.Simulation()
 sim.step_multiple({"a": [1, 5, 9], "b": [2, 6, 7], "c": [3, 4, 8]})
 sim.tracer.render_trace()
diff --git a/www/examples/example-mul.py b/www/examples/example-mul.py
index c65b8695..c3f5cacc 100644
--- a/www/examples/example-mul.py
+++ b/www/examples/example-mul.py
@@ -1,5 +1,7 @@
 import pyrtl
 
+# # ROM-based multiplier example.
+
 
 def mul(x: pyrtl.WireVector, y: pyrtl.WireVector) -> pyrtl.WireVector:
     assert x.bitwidth == 4
@@ -18,6 +20,7 @@ def romdata(addr: int) -> int:
 
 product <<= mul(a, b)
 
+# Simulate the design.
 sim = pyrtl.Simulation()
 sim.step_multiple({"a": [1, 2, 3], "b": [2, 3, 4]})
 sim.tracer.render_trace()
diff --git a/www/examples/example-ripple-carry.py b/www/examples/example-ripple-carry.py
index a81443f5..dd770fee 100644
--- a/www/examples/example-ripple-carry.py
+++ b/www/examples/example-ripple-carry.py
@@ -1,5 +1,7 @@
 import pyrtl
 
+# # Ripple-carry adder example.
+
 
 def one_bit_add(
     a: pyrtl.WireVector, b: pyrtl.WireVector, carry_in: pyrtl.WireVector | int
diff --git a/www/index.rst b/www/index.rst
index 91b60032..d766b9f3 100644
--- a/www/index.rst
+++ b/www/index.rst
@@ -43,7 +43,7 @@
 
       .. grid-item::
 
-         .. button-link:: https://mybinder.org/v2/gh/UCSBarchlab/PyRTL/development?filepath=%2Fipynb-examples%2F
+         .. button-link:: lite/index.html
             :color: secondary
             :expand:
             :shadow:
@@ -60,6 +60,8 @@ simulation. Get started with:
 
     $ pip install pyrtl
 
+or `try our examples in your browser <lite/index.html>`_.
+
 Features
 ========
 
@@ -113,6 +115,10 @@ differences between the approaches.
             The code below provides everything needed to instantiate, simulate, and
             visualize the resulting design.
 
+            .. jupyterlite:: ipynb-examples/example-gcd.ipynb
+               :new_tab: True
+               :new_tab_button_text: Try this example in your browser
+
             .. literalinclude:: examples/example-gcd.py
 
             .. image:: ../docs/screenshots/gcd.png
@@ -128,6 +134,10 @@ differences between the approaches.
             an output ``y`` which is the resulting sum of products and is valid every
             cycle (since the design is naturally fully pipelined).
 
+            .. jupyterlite:: ipynb-examples/example-fir.ipynb
+               :new_tab: True
+               :new_tab_button_text: Try this example in your browser
+
             .. literalinclude:: examples/example-fir.py
 
             .. image:: ../docs/screenshots/fir.png
@@ -144,6 +154,10 @@ differences between the approaches.
             like :func:`~functools.reduce`, which is used to chain together multiple
             ``max_2`` elements into a bigger ``max_n``.
 
+            .. jupyterlite:: ipynb-examples/example-maxn.ipynb
+               :new_tab: True
+               :new_tab_button_text: Try this example in your browser
+
             .. literalinclude:: examples/example-maxn.py
 
             .. image:: ../docs/screenshots/maxn.png
@@ -151,6 +165,7 @@ differences between the approaches.
 
          .. tab-item:: Mul
 
+
             ``mul`` generates a small 4 x 4 multiplier with a simple `ROM
             <https://en.wikipedia.org/wiki/Read-only_memory>`_ lookup. The first two
             lines simply check that the inputs are each 4-bits wide. ``romdata`` is a
@@ -161,6 +176,10 @@ differences between the approaches.
             an 8-bit ROM address and returns the value stored in the ROM at that
             address.
 
+            .. jupyterlite:: ipynb-examples/example-mul.ipynb
+               :new_tab: True
+               :new_tab_button_text: Try this example in your browser
+
             .. literalinclude:: examples/example-mul.py
 
             .. image:: ../docs/screenshots/mul.png
@@ -178,6 +197,10 @@ differences between the approaches.
             final ``full_sum`` is produced by concatenating the wires in ``sum`` with
             :func:`~pyrtl.concat_list`.
 
+            .. jupyterlite:: ipynb-examples/example-adder.ipynb
+               :new_tab: True
+               :new_tab_button_text: Try this example in your browser
+
             .. literalinclude:: examples/example-adder.py
 
             .. image:: ../docs/screenshots/adder.png
@@ -218,9 +241,8 @@ by 2 and sum them into a :class:`~pyrtl.WireVector` ``y``::
     y = sum([elem * 2 for elem in x])
 
 Hardware comprehensions are surprisingly useful. We'll cover an example in more
-detail below, but if you just want to play around with PyRTL `try Jupyter
-Notebooks on any of our examples on MyBinder
-<https://mybinder.org/v2/gh/UCSBarchlab/PyRTL/development?filepath=%2Fipynb-examples%2F>`_.
+detail below, but if you just want to play around with PyRTL, `try our examples
+in your browser <lite/index.html>`_.
 
 Hello N-bit Ripple-Carry Adder!
 ===============================
@@ -233,6 +255,10 @@ introduction to fixed 4-bit adders
 <https://www.youtube.com/watch?v=bL3ihMA8_Gs>`_, let's go ahead and build an
 `arbitrary` bitwidth adder.
 
+.. jupyterlite:: ipynb-examples/example-ripple-carry.ipynb
+   :new_tab: True
+   :new_tab_button_text: Try this example in your browser
+
 .. literalinclude:: examples/example-ripple-carry.py
 
 The code above includes ``ripple_add``, an adder generator with Python-style
@@ -245,4 +271,3 @@ running from 0 to 7 and repeating:
 
 .. image:: ../docs/screenshots/ripple-carry.png
    :width: 34em
-
diff --git a/www/ipynb-examples/example-adder.ipynb b/www/ipynb-examples/example-adder.ipynb
new file mode 100644
index 00000000..df16bd3f
--- /dev/null
+++ b/www/ipynb-examples/example-adder.ipynb
@@ -0,0 +1,107 @@
+{
+ "cells": [
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "%pip install pyrtl\n",
+    "\n",
+    "import pyrtl\n",
+    "\n",
+    "pyrtl.reset_working_block()"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    " # Ripple-carry adder example.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "def fa(\n",
+    "    x: pyrtl.WireVector, y: pyrtl.WireVector, cin: pyrtl.WireVector\n",
+    ") -> tuple[pyrtl.WireVector, pyrtl.WireVector]:\n",
+    "    \"\"\"Full adder.\"\"\"\n",
+    "    sum = x ^ y ^ cin\n",
+    "    cout = x & y | y & cin | x & cin\n",
+    "    return sum, cout\n",
+    "\n",
+    "\n",
+    "def adder(\n",
+    "    a: pyrtl.WireVector, b: pyrtl.WireVector, cin: pyrtl.WireVector\n",
+    ") -> tuple[pyrtl.WireVector, pyrtl.WireVector]:\n",
+    "    \"\"\"n-bit ripple carry adder with carry in and carry out.\"\"\"\n",
+    "    a, b = pyrtl.match_bitwidth(a, b)\n",
+    "\n",
+    "    sum = [None] * a.bitwidth\n",
+    "    for i in range(a.bitwidth):\n",
+    "        sum[i], cout = fa(a[i], b[i], cin)\n",
+    "        cin = cout\n",
+    "\n",
+    "    full_sum = pyrtl.concat_list(sum)\n",
+    "    return full_sum, cout\n",
+    "\n",
+    "\n",
+    "a = pyrtl.Input(name=\"a\", bitwidth=4)\n",
+    "b = pyrtl.Input(name=\"b\", bitwidth=4)\n",
+    "sum = pyrtl.Output(name=\"sum\", bitwidth=8)\n",
+    "\n",
+    "sum_, cout_ = adder(a, b, pyrtl.Const(0))\n",
+    "sum <<= sum_"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    " Simulate the design.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "sim = pyrtl.Simulation()\n",
+    "sim.step_multiple({\"a\": [1, 2, 3], \"b\": [2, 3, 4]})\n",
+    "sim.tracer.render_trace()"
+   ]
+  }
+ ],
+ "metadata": {
+  "kernelspec": {
+   "display_name": "Python 3",
+   "language": "python",
+   "name": "python3"
+  },
+  "language_info": {
+   "codemirror_mode": {
+    "name": "ipython",
+    "version": 3
+   },
+   "file_extension": ".py",
+   "mimetype": "text/x-python",
+   "name": "python",
+   "nbconvert_exporter": "python",
+   "pygments_lexer": "ipython3",
+   "version": "3.6.4"
+  }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 2
+}
\ No newline at end of file
diff --git a/www/ipynb-examples/example-fir.ipynb b/www/ipynb-examples/example-fir.ipynb
new file mode 100644
index 00000000..c17c6ae3
--- /dev/null
+++ b/www/ipynb-examples/example-fir.ipynb
@@ -0,0 +1,92 @@
+{
+ "cells": [
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "%pip install pyrtl\n",
+    "\n",
+    "import pyrtl\n",
+    "\n",
+    "pyrtl.reset_working_block()"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    " # Finite impulse filter example.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "def fir(x: pyrtl.WireVector, bs: list[int]):\n",
+    "    rwidth = x.bitwidth  # Bitwidth of the registers.\n",
+    "    ntaps = len(bs)  # Number of coefficients.\n",
+    "\n",
+    "    zs = [x] + [pyrtl.Register(rwidth) for _ in range(ntaps - 1)]\n",
+    "    for i in range(1, ntaps):\n",
+    "        zs[i].next <<= zs[i - 1]\n",
+    "\n",
+    "    # Produce the final sum of products.\n",
+    "    return sum(z * b for z, b in zip(zs, bs, strict=True))\n",
+    "\n",
+    "\n",
+    "x = pyrtl.Input(name=\"x\", bitwidth=8)\n",
+    "y = pyrtl.Output(name=\"y\", bitwidth=8)\n",
+    "y <<= fir(x, bs=[0, 1])"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    " Simulate the design.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "sim = pyrtl.Simulation()\n",
+    "sim.step_multiple({\"x\": [0, 9, 18, 8, 17, 7, 16, 6, 15, 5]})\n",
+    "sim.tracer.render_trace()"
+   ]
+  }
+ ],
+ "metadata": {
+  "kernelspec": {
+   "display_name": "Python 3",
+   "language": "python",
+   "name": "python3"
+  },
+  "language_info": {
+   "codemirror_mode": {
+    "name": "ipython",
+    "version": 3
+   },
+   "file_extension": ".py",
+   "mimetype": "text/x-python",
+   "name": "python",
+   "nbconvert_exporter": "python",
+   "pygments_lexer": "ipython3",
+   "version": "3.6.4"
+  }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 2
+}
\ No newline at end of file
diff --git a/www/ipynb-examples/example-gcd.ipynb b/www/ipynb-examples/example-gcd.ipynb
new file mode 100644
index 00000000..f48f9d06
--- /dev/null
+++ b/www/ipynb-examples/example-gcd.ipynb
@@ -0,0 +1,109 @@
+{
+ "cells": [
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "%pip install pyrtl\n",
+    "\n",
+    "import pyrtl\n",
+    "\n",
+    "pyrtl.reset_working_block()"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    " # Greatest common denominator example.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "def gcd(\n",
+    "    a: pyrtl.WireVector, b: pyrtl.WireVector, begin: pyrtl.WireVector\n",
+    ") -> tuple[pyrtl.WireVector, pyrtl.WireVector]:\n",
+    "    x = pyrtl.Register(bitwidth=a.bitwidth)\n",
+    "    y = pyrtl.Register(bitwidth=b.bitwidth)\n",
+    "    done = pyrtl.WireVector(bitwidth=1)\n",
+    "\n",
+    "    with pyrtl.conditional_assignment:\n",
+    "        with begin:\n",
+    "            x.next |= a\n",
+    "            y.next |= b\n",
+    "        with x > y:\n",
+    "            x.next |= x - y\n",
+    "        with y > x:\n",
+    "            y.next |= y - x\n",
+    "        with pyrtl.otherwise:\n",
+    "            done |= True\n",
+    "    return x, done\n",
+    "\n",
+    "\n",
+    "a = pyrtl.Input(name=\"a\", bitwidth=8)\n",
+    "b = pyrtl.Input(name=\"b\", bitwidth=8)\n",
+    "begin = pyrtl.Input(name=\"begin\", bitwidth=1)\n",
+    "\n",
+    "x = pyrtl.Output(name=\"x\", bitwidth=8)\n",
+    "done = pyrtl.Output(name=\"done\", bitwidth=1)\n",
+    "\n",
+    "x_, done_ = gcd(a, b, begin)\n",
+    "x <<= x_\n",
+    "done <<= done_"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    " Simulate the design.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "sim = pyrtl.Simulation()\n",
+    "sim.step({\"a\": 12, \"b\": 9, \"begin\": True})\n",
+    "while not sim.inspect(\"done\"):\n",
+    "    sim.step({\"a\": 0, \"b\": 0, \"begin\": False})\n",
+    "sim.tracer.render_trace()"
+   ]
+  }
+ ],
+ "metadata": {
+  "kernelspec": {
+   "display_name": "Python 3",
+   "language": "python",
+   "name": "python3"
+  },
+  "language_info": {
+   "codemirror_mode": {
+    "name": "ipython",
+    "version": 3
+   },
+   "file_extension": ".py",
+   "mimetype": "text/x-python",
+   "name": "python",
+   "nbconvert_exporter": "python",
+   "pygments_lexer": "ipython3",
+   "version": "3.6.4"
+  }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 2
+}
\ No newline at end of file
diff --git a/www/ipynb-examples/example-maxn.ipynb b/www/ipynb-examples/example-maxn.ipynb
new file mode 100644
index 00000000..2841fd0b
--- /dev/null
+++ b/www/ipynb-examples/example-maxn.ipynb
@@ -0,0 +1,92 @@
+{
+ "cells": [
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "%pip install pyrtl\n",
+    "\n",
+    "from functools import reduce\n",
+    "\n",
+    "import pyrtl\n",
+    "\n",
+    "pyrtl.reset_working_block()"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    " # N-way max example.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "def max_n(*inputs):\n",
+    "    def max_2(x, y):\n",
+    "        return pyrtl.select(x > y, x, y)\n",
+    "\n",
+    "    return reduce(max_2, inputs)\n",
+    "\n",
+    "\n",
+    "a = pyrtl.Input(name=\"a\", bitwidth=8)\n",
+    "b = pyrtl.Input(name=\"b\", bitwidth=8)\n",
+    "c = pyrtl.Input(name=\"c\", bitwidth=8)\n",
+    "max = pyrtl.Output(name=\"max\", bitwidth=8)\n",
+    "\n",
+    "max <<= max_n(a, b, c)"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    " Simulate the design.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "sim = pyrtl.Simulation()\n",
+    "sim.step_multiple({\"a\": [1, 5, 9], \"b\": [2, 6, 7], \"c\": [3, 4, 8]})\n",
+    "sim.tracer.render_trace()"
+   ]
+  }
+ ],
+ "metadata": {
+  "kernelspec": {
+   "display_name": "Python 3",
+   "language": "python",
+   "name": "python3"
+  },
+  "language_info": {
+   "codemirror_mode": {
+    "name": "ipython",
+    "version": 3
+   },
+   "file_extension": ".py",
+   "mimetype": "text/x-python",
+   "name": "python",
+   "nbconvert_exporter": "python",
+   "pygments_lexer": "ipython3",
+   "version": "3.6.4"
+  }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 2
+}
\ No newline at end of file
diff --git a/www/ipynb-examples/example-mul.ipynb b/www/ipynb-examples/example-mul.ipynb
new file mode 100644
index 00000000..cfb73739
--- /dev/null
+++ b/www/ipynb-examples/example-mul.ipynb
@@ -0,0 +1,93 @@
+{
+ "cells": [
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "%pip install pyrtl\n",
+    "\n",
+    "import pyrtl\n",
+    "\n",
+    "pyrtl.reset_working_block()"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    " # ROM-based multiplier example.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "def mul(x: pyrtl.WireVector, y: pyrtl.WireVector) -> pyrtl.WireVector:\n",
+    "    assert x.bitwidth == 4\n",
+    "    assert y.bitwidth == 4\n",
+    "\n",
+    "    def romdata(addr: int) -> int:\n",
+    "        return (addr >> 4) * (addr & 0xF)\n",
+    "\n",
+    "    tbl = pyrtl.RomBlock(bitwidth=8, addrwidth=8, romdata=romdata)\n",
+    "    return tbl[pyrtl.concat(x, y)]\n",
+    "\n",
+    "\n",
+    "a = pyrtl.Input(name=\"a\", bitwidth=4)\n",
+    "b = pyrtl.Input(name=\"b\", bitwidth=4)\n",
+    "product = pyrtl.Output(name=\"product\", bitwidth=8)\n",
+    "\n",
+    "product <<= mul(a, b)"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    " Simulate the design.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "sim = pyrtl.Simulation()\n",
+    "sim.step_multiple({\"a\": [1, 2, 3], \"b\": [2, 3, 4]})\n",
+    "sim.tracer.render_trace()"
+   ]
+  }
+ ],
+ "metadata": {
+  "kernelspec": {
+   "display_name": "Python 3",
+   "language": "python",
+   "name": "python3"
+  },
+  "language_info": {
+   "codemirror_mode": {
+    "name": "ipython",
+    "version": 3
+   },
+   "file_extension": ".py",
+   "mimetype": "text/x-python",
+   "name": "python",
+   "nbconvert_exporter": "python",
+   "pygments_lexer": "ipython3",
+   "version": "3.6.4"
+  }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 2
+}
\ No newline at end of file
diff --git a/www/ipynb-examples/example-ripple-carry.ipynb b/www/ipynb-examples/example-ripple-carry.ipynb
new file mode 100644
index 00000000..f37890f8
--- /dev/null
+++ b/www/ipynb-examples/example-ripple-carry.ipynb
@@ -0,0 +1,117 @@
+{
+ "cells": [
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "%pip install pyrtl\n",
+    "\n",
+    "import pyrtl\n",
+    "\n",
+    "pyrtl.reset_working_block()"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    " # Ripple-carry adder example.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "def one_bit_add(\n",
+    "    a: pyrtl.WireVector, b: pyrtl.WireVector, carry_in: pyrtl.WireVector | int\n",
+    ") -> tuple[pyrtl.WireVector, pyrtl.WireVector]:\n",
+    "    assert len(a) == len(b) == 1  # `len` returns the bitwidth.\n",
+    "    sum = a ^ b ^ carry_in  # WireVector operators build the hardware.\n",
+    "    carry_out = a & b | a & carry_in | b & carry_in\n",
+    "    return sum, carry_out\n",
+    "\n",
+    "\n",
+    "def ripple_add(\n",
+    "    a: pyrtl.WireVector, b: pyrtl.WireVector, carry_in: pyrtl.WireVector | int = 0\n",
+    ") -> tuple[pyrtl.WireVector, pyrtl.WireVector]:\n",
+    "    a, b = pyrtl.match_bitwidth(a, b)\n",
+    "    if len(a) == 1:\n",
+    "        sumbits, carry_out = one_bit_add(a, b, carry_in)\n",
+    "    else:\n",
+    "        lsbit, ripplecarry = one_bit_add(a[0], b[0], carry_in)\n",
+    "        msbits, carry_out = ripple_add(a[1:], b[1:], ripplecarry)\n",
+    "        sumbits = pyrtl.concat(msbits, lsbit)\n",
+    "    return sumbits, carry_out"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    " Use the adder in a 3-bit counter.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "counter = pyrtl.Register(bitwidth=3, name=\"counter\")\n",
+    "sum, _carry_out = ripple_add(counter, pyrtl.Const(1))\n",
+    "counter.next <<= sum"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    " Simulate the instantiated design for 12 cycles.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "sim = pyrtl.Simulation()\n",
+    "sim.step_multiple(nsteps=12)\n",
+    "sim.tracer.render_trace()"
+   ]
+  }
+ ],
+ "metadata": {
+  "kernelspec": {
+   "display_name": "Python 3",
+   "language": "python",
+   "name": "python3"
+  },
+  "language_info": {
+   "codemirror_mode": {
+    "name": "ipython",
+    "version": 3
+   },
+   "file_extension": ".py",
+   "mimetype": "text/x-python",
+   "name": "python",
+   "nbconvert_exporter": "python",
+   "pygments_lexer": "ipython3",
+   "version": "3.6.4"
+  }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 2
+}
\ No newline at end of file