Skip to content

Question regarding Clocking Wizard IP reset type in “SDSoC Platform Creation Labs > Lab 1” #23

Description

@peter2chang

In lab1 step2 (create an IP Integrator Design), Clocking Wizard IP’s reset type is set to active low. Is it because the Zynq7 SoC is used? Should I need to set reset type to Low for all my projects that use Zynq7 in the future? Thanks in advance!

Activity

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Metadata

Metadata

Assignees

No one assigned

    Labels

    No labels
    No labels

    Type

    No type

    Projects

    No projects

      Milestone

      No milestone

      Relationships

      None yet

      Development

      No branches or pull requests

      Issue actions