Issues

• Bad coding

  Bug
  edaa-org/pyEDAA.ProjectModel#67 · Filter by author Paebbels opened on Jan 12, 2024
  

• VHDLLibraries in FileSet?

  edaa-org/pyEDAA.ProjectModel#66 · Filter by author RasmusGOlsen opened on Nov 30, 2023

• ExternalVHDLLibrary incomplete type hint

  edaa-org/pyEDAA.ProjectModel#65 · Filter by author RasmusGOlsen opened on Nov 30, 2023

• Missing method to add ExternalVHDLLibrary

  Enhancement
  edaa-org/pyEDAA.ProjectModel#64 · Filter by author RasmusGOlsen opened on Nov 30, 2023
  2

• Verilog needs library, and include file information

  edaa-org/pyEDAA.ProjectModel#63 · Filter by author RasmusGOlsen opened on Oct 17, 2023
  1

• Create a design without the default fileset

  Question
  edaa-org/pyEDAA.ProjectModel#62 · Filter by author RasmusGOlsen opened on Oct 8, 2023
  1

• How to get files from Project, Design and Fileset

  EnhancementQuestion
  edaa-org/pyEDAA.ProjectModel#61 · Filter by author RasmusGOlsen opened on Oct 6, 2023
  1

• How to get top levels of a project?

  Enhancement
  edaa-org/pyEDAA.ProjectModel#60 · Filter by author RasmusGOlsen opened on Oct 5, 2023
  3

• Exception when Setting default fileset in design

  BugQuestion
  edaa-org/pyEDAA.ProjectModel#59 · Filter by author RasmusGOlsen opened on Oct 4, 2023
  3

• The Design class' function AddVHDLLibrary doesn't add anything

  Bug
  edaa-org/pyEDAA.ProjectModel#58 · Filter by author RasmusGOlsen opened on Oct 4, 2023
  1

• pySVModel 0.4 compatibility issue

  edaa-org/pyEDAA.ProjectModel#57 · Filter by author RasmusGOlsen opened on Aug 21, 2023
  1

• Files are duplicated in file set

  Bug
  edaa-org/pyEDAA.ProjectModel#56 · Filter by author RasmusGOlsen opened on Aug 9, 2023
  1

• Attribute Error in FileSet class

  Question
  edaa-org/pyEDAA.ProjectModel#55 · Filter by author RasmusGOlsen opened on Aug 7, 2023
  6

• How can I specify File attributes?

  EnhancementQuestion
  edaa-org/pyEDAA.ProjectModel#53 · Filter by author RasmusGOlsen opened on Jul 28, 2023
  2

• Why Should Verilog and SystemVerilog source file be split in two classes?

  edaa-org/pyEDAA.ProjectModel#51 · Filter by author RasmusGOlsen opened on Jun 19, 2023
  5

• Verilog include file is missing

  Bug
  edaa-org/pyEDAA.ProjectModel#50 · Filter by author RasmusGOlsen opened on Jun 19, 2023
  4

• Questions about the design and fileset in the project module

  Question
  edaa-org/pyEDAA.ProjectModel#49 · Filter by author RasmusGOlsen opened on Jun 18, 2023
  14

• Add support for SystemRDL source files

  EnhancementQuestion
  edaa-org/pyEDAA.ProjectModel#47 · Filter by author RasmusGOlsen opened on Jun 18, 2023
  7

• Error parsing an XPR file

  Bug
  edaa-org/pyEDAA.ProjectModel#46 · Filter by author Paebbels opened on Mar 10, 2022
  

• Merging/combining multiple projects

  Enhancement
  edaa-org/pyEDAA.ProjectModel#26 · Filter by author umarcor opened on Nov 1, 2021

• [CI] Create a script to use the pull-request text as release text

  Enhancement
  edaa-org/pyEDAA.ProjectModel#20 · Filter by author umarcor opened on Oct 17, 2021

• [External Tracking] Sphinx doesn't generate documentation for classes derived from metaclasses with type hints

  BugDocumentation
  edaa-org/pyEDAA.ProjectModel#10 · Filter by author Paebbels opened on Oct 3, 2021

• [File Type] Add more file types

  Enhancement
  edaa-org/pyEDAA.ProjectModel#8 · Filter by author Paebbels opened on Oct 2, 2021

• [Feature] File Attributes

  Enhancement
  edaa-org/pyEDAA.ProjectModel#7 · Filter by author Paebbels opened on Oct 2, 2021

• [Feature] Related files to files

  Enhancement
  edaa-org/pyEDAA.ProjectModel#6 · Filter by author Paebbels opened on Oct 2, 2021