diff --git a/.trinity/seals/policy_PolicyL2Generation.json b/.trinity/seals/policy_PolicyL2Generation.json
index d7c9319a34..4270274414 100644
--- a/.trinity/seals/policy_PolicyL2Generation.json
+++ b/.trinity/seals/policy_PolicyL2Generation.json
@@ -1,5 +1,5 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+cc19d1fcd",
+  "built_by": "t27c-bootstrap@0.5.2+eb3bf9bd6",
   "closure": [
     {
       "spec": "specs/policy/own_language.t27",
@@ -11,16 +11,16 @@
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
-  "gen_hash_c": "sha256:c6c9cdb35543dd68b4679feebe5d7aaeb7732866a307f1bb9896e54a4c3886ce",
-  "gen_hash_rust": "sha256:cc5b1f1c144fe6387d314da77c1b3ffc220aa0d759ef65d91a51e537445de3db",
-  "gen_hash_verilog": "sha256:fea377aa39ab65e5ee45befa9d0ef0fdf20f4c3734406a64535d15153e15831c",
-  "gen_hash_zig": "sha256:b392ec7549bce6f50e67fc8f6793abad5b49dd769b06273fbdf0770050476abf",
+  "gen_hash_c": "sha256:9bde97a57af2cca964c0688dc28b90251ed6c1bd9c140dde60a13282feab7e1c",
+  "gen_hash_rust": "sha256:1381dab7e4826ccd8ff5f3ba8662475b7bc80d6249302e5ab586c4e0f6311ffc",
+  "gen_hash_verilog": "sha256:c8b31e83fab3f8fad72903aa33af543ca294920d11235e6028535b44a28e3f35",
+  "gen_hash_zig": "sha256:1b937eda25f0f54b399c5328b054a9c3288d4bccf36910172c05a1d86424ca56",
   "module": "PolicyL2Generation",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-11T10:43:23Z",
+  "sealed_at": "2026-10-17T18:56:27Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
-  "spec_hash": "sha256:b7560ca9172ce352001ab6b833a436d15ff005d916405423f6f40f34dd9f78ac",
+  "spec_hash": "sha256:bc3a2e8f4c939ade9d951c77e0736775efe57500746bcc4cc2496ca48985a64d",
   "spec_path": "specs/policy/l2_generation.t27",
   "tests": {
     "failed": 0,
diff --git a/gen/c/policy/l2_generation.c b/gen/c/policy/l2_generation.c
index cd419e5bb3..8b60a8fe05 100644
--- a/gen/c/policy/l2_generation.c
+++ b/gen/c/policy/l2_generation.c
@@ -31,8 +31,8 @@
 #define K_ADDED 4
 #define BY_USE 0
 #define BY_STEM 1
-#define BACKENDS "c,verilog,rust,zig,$"
-#define SUBCOMMANDS "gen-c,gen-verilog,gen-rust,gen,$"
+#define BACKENDS "c,verilog,rust,zig,json,$"
+#define SUBCOMMANDS "gen-c,gen-verilog,gen-rust,gen,gen-json,$"
 #define NOT_FOUND 65535
 #define GEN_ROOT "gen/$"
 #define GEN_ROOT_LEN 4
@@ -799,12 +799,13 @@ size_t text_end(uint8_t* buf, size_t s, size_t e) {
    ------------------------------------------------------- */
 
 /* invariant: the_backend_table_is_pinned */
-/* invariant the_backend_table_is_pinned is not a C constant expression: (list_len(BACKENDS) == 4) */
-/* invariant the_backend_table_is_pinned is not a C constant expression: (list_len(SUBCOMMANDS) == 4) */
+/* invariant the_backend_table_is_pinned is not a C constant expression: (list_len(BACKENDS) == 5) */
+/* invariant the_backend_table_is_pinned is not a C constant expression: (list_len(SUBCOMMANDS) == 5) */
 /* invariant the_backend_table_is_pinned is not a C constant expression: (list_index(BACKENDS, "c", 0, 1) == list_index(SUBCOMMANDS, "gen-c", 0, 5)) */
 /* invariant the_backend_table_is_pinned is not a C constant expression: (list_index(BACKENDS, "verilog", 0, 7) == list_index(SUBCOMMANDS, "gen-verilog", 0, 11)) */
 /* invariant the_backend_table_is_pinned is not a C constant expression: (list_index(BACKENDS, "rust", 0, 4) == list_index(SUBCOMMANDS, "gen-rust", 0, 8)) */
 /* invariant the_backend_table_is_pinned is not a C constant expression: (list_index(BACKENDS, "zig", 0, 3) == list_index(SUBCOMMANDS, "gen", 0, 3)) */
+/* invariant the_backend_table_is_pinned is not a C constant expression: (list_index(BACKENDS, "json", 0, 4) == list_index(SUBCOMMANDS, "gen-json", 0, 8)) */
 /* invariant the_backend_table_is_pinned is not a C constant expression: (list_index(SUBCOMMANDS, "gen-zig", 0, 7) == NOT_FOUND) */
 
 /* invariant: the_fixed_lengths_are_the_pieces_lengths */
@@ -822,6 +823,8 @@ void test_a_copy_maps_to_its_backend_and_stem(void) {
     assert((copy_reason("gen/c/queen/priority.c", 0, 22) == R_MAPPED));
     assert((copy_reason("gen/verilog/numeric/gf16.v", 0, 26) == R_MAPPED));
     assert((copy_reason("gen/zig/a.zig", 0, 13) == R_MAPPED));
+    assert((copy_reason("gen/json/igla/own_model_board.json", 0, 34) == R_MAPPED));
+    assert((copy_reason("gen/jsonl/a.json", 0, 16) == R_UNKNOWN_BACKEND));
     assert((copy_reason("gen/README.md", 0, 13) == R_NO_BACKEND));
     assert((copy_reason("gen/c", 0, 5) == R_NO_BACKEND));
     assert((copy_reason("specs/a.t27", 0, 11) == R_NO_BACKEND));
diff --git a/specs/policy/l2_generation.t27 b/specs/policy/l2_generation.t27
index 0326b42f60..7deb772c5a 100644
--- a/specs/policy/l2_generation.t27
+++ b/specs/policy/l2_generation.t27
@@ -29,7 +29,8 @@
 ; - "--all" checks every tracked copy, whatever changed.
 ; - gen/<backend>/<stem>.<ext> is the copy of specs/<stem>.t27, written by the subcommand that the table
 ;   below pairs with the backend. zig is `t27c gen`: t27c has no `gen-zig`, which the Python this replaces
-;   named, so a correct zig copy would have failed there.
+;   named, so a correct zig copy would have failed there. json is `t27c gen-json`, the IGLA board event a
+;   spec states (#10050).
 ; - A `use` path is read as use_resolve.rs reads it: `::` and `.` both separate segments, an empty segment
 ;   vanishes, a trailing comment and every trailing ';' are cut, and a path with a space but no `::` is not
 ;   an import.
@@ -69,8 +70,8 @@ pub const BY_USE : u8 = 0;
 pub const BY_STEM : u8 = 1;
 
 /// gen/<backend>/ and the t27c subcommand that writes it, entry for entry.
-pub const BACKENDS : str = "c,verilog,rust,zig,$";
-pub const SUBCOMMANDS : str = "gen-c,gen-verilog,gen-rust,gen,$";
+pub const BACKENDS : str = "c,verilog,rust,zig,json,$";
+pub const SUBCOMMANDS : str = "gen-c,gen-verilog,gen-rust,gen,gen-json,$";
 
 pub const NOT_FOUND : usize = 65535;
 
@@ -635,6 +636,8 @@ test a_copy_maps_to_its_backend_and_stem {
     assert copy_reason("gen/c/queen/priority.c", 0, 22) == R_MAPPED;
     assert copy_reason("gen/verilog/numeric/gf16.v", 0, 26) == R_MAPPED;
     assert copy_reason("gen/zig/a.zig", 0, 13) == R_MAPPED;
+    assert copy_reason("gen/json/igla/own_model_board.json", 0, 34) == R_MAPPED;
+    assert copy_reason("gen/jsonl/a.json", 0, 16) == R_UNKNOWN_BACKEND;
     assert copy_reason("gen/README.md", 0, 13) == R_NO_BACKEND;
     assert copy_reason("gen/c", 0, 5) == R_NO_BACKEND;
     assert copy_reason("specs/a.t27", 0, 11) == R_NO_BACKEND;
@@ -905,12 +908,13 @@ test the_line_helpers_stay_inside_their_ranges {
 }
 
 invariant the_backend_table_is_pinned {
-    assert list_len(BACKENDS) == 4;
-    assert list_len(SUBCOMMANDS) == 4;
+    assert list_len(BACKENDS) == 5;
+    assert list_len(SUBCOMMANDS) == 5;
     assert list_index(BACKENDS, "c", 0, 1) == list_index(SUBCOMMANDS, "gen-c", 0, 5);
     assert list_index(BACKENDS, "verilog", 0, 7) == list_index(SUBCOMMANDS, "gen-verilog", 0, 11);
     assert list_index(BACKENDS, "rust", 0, 4) == list_index(SUBCOMMANDS, "gen-rust", 0, 8);
     assert list_index(BACKENDS, "zig", 0, 3) == list_index(SUBCOMMANDS, "gen", 0, 3);
+    assert list_index(BACKENDS, "json", 0, 4) == list_index(SUBCOMMANDS, "gen-json", 0, 8);
     assert list_index(SUBCOMMANDS, "gen-zig", 0, 7) == NOT_FOUND;
 }