From 6b749d96612b5b41d31f16a7962c2d0ec12b7cf4 Mon Sep 17 00:00:00 2001 From: Dmitrii Vasilev Date: Sun, 18 Oct 2026 15:26:26 +0700 Subject: [PATCH] fpga(ax7203): rc_filter PLL params back to f64 so t27b passes the spec again (Closes #10313) master's t27b-native-ratchet reads `specs/fpga/rc_filter_ax7203.t27: ledger pass, now blocked: type comptime_float`. #10278 ledgered the spec as t27b pass; #10296 then typed PLLE2_ADV's CLKIN1_PERIOD and REF_JITTER1 as comptime_float so t27c gen-verilog would not emit `input real`, and t27b rejects a comptime_float parameter. #10302 made gen-verilog skip t27b bitstream specs, so that reason is gone: the two parameters go back to f64 and the doc comment says why. Measured on the Railway lab at master 9da2c5f, t27b and t27c built there: - t27b on master's spec: "unsupported construct type comptime_float at line 247"; on this spec: accepted, and `t27b build --elf` writes the object (the x86 lab has no t27b JIT; CI's arm64 runs the tests). - `t27b verilog`: same 608 lines as master's; only the five `// ... (line N)` comments move by 2. The PLL instance still reads CLKIN1_PERIOD(5.0), REF_JITTER1(0.01), so the board RTL does not change. - reference (t27c test-report, zig 0.16.0): 10 of 10 pass, 0 vacuous. - seal regenerated with `t27c seal --save`: spec_hash 8fba8a41. Co-Authored-By: Claude Opus 5.5 --- .trinity/seals/fpga_FpgaRcFilter.json | 14 +++++++------- specs/fpga/rc_filter_ax7203.t27 | 4 +++- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/.trinity/seals/fpga_FpgaRcFilter.json b/.trinity/seals/fpga_FpgaRcFilter.json index 471a0e661d..5547c56073 100644 --- a/.trinity/seals/fpga_FpgaRcFilter.json +++ b/.trinity/seals/fpga_FpgaRcFilter.json @@ -1,17 +1,17 @@ { - "built_by": "t27c-bootstrap@0.5.2+a86b691b1", + "built_by": "t27c-bootstrap@0.5.2+9da2c5f", "closure": [], "config": "gen=c,rust,verilog,zig;tests=zig", - "gen_hash_c": "sha256:0d8d5fc925210336cd05292836dcc30da5e845d60285427c76658a303d56be96", - "gen_hash_rust": "sha256:156ba364b202e548825093b2ddb417ea72d7d6ed9f69ead68bc54b41f396b85b", - "gen_hash_verilog": "sha256:90bddb94a07f0f42bd10ae74e9c011101f39c2dc325baac08e041e1d2df7e91b", - "gen_hash_zig": "sha256:acb0b5b1fabeb7c69bbdc1b34adaaaedd1288c23474fa2fe05dc81568afa5850", + "gen_hash_c": "sha256:345d70ff4a42876b9a38808fb16183e3026e436fe989ae8421da9e346bc07096", + "gen_hash_rust": "sha256:6321804010ff1127f915e0004f936d9a7002c01a525de42c539fe9e2595fd9be", + "gen_hash_verilog": "sha256:f8a97da90c082ad1ab84c132487152da1fe021c7f7be0537d970d6a6483c36de", + "gen_hash_zig": "sha256:5da6f0a60ae03e0ac806727e04bf0d2ae19e3d3589271de9b090bc4f91590fb8", "module": "FpgaRcFilter", "ring": 12, "seal_schema": 2, - "sealed_at": "2026-10-18T07:41:41Z", + "sealed_at": "2026-10-18T08:25:46Z", "sealed_by": "t27c-bootstrap@0.5.2", - "spec_hash": "sha256:3728871b26cf0504c6e76306f7633547787c034d04da93493229cbd229d8e36a", + "spec_hash": "sha256:8fba8a419217ffe5dc6454759dd438d2236fb2cd829f9d64a3c2e15e3f44e51d", "spec_path": "specs/fpga/rc_filter_ax7203.t27", "tests": { "failed": 0, diff --git a/specs/fpga/rc_filter_ax7203.t27 b/specs/fpga/rc_filter_ax7203.t27 index 62e8600276..d7301506ea 100644 --- a/specs/fpga/rc_filter_ax7203.t27 +++ b/specs/fpga/rc_filter_ax7203.t27 @@ -244,7 +244,9 @@ pub fn BUFG(I: bool) -> BufgOut {} /// A PLL: 200 MHz in, VCO = 200 * 8 = 1600 MHz, CLKOUT0 = 1600 / 16 = 100 MHz; CLKFBOUT feeds CLKFBIN. /// The settings are the ones LiteDRAM's S7PLL used on this board for the DDR3 cell, which locked. pub struct PllOut { CLKOUT0: bool, CLKFBOUT: bool, LOCKED: bool } -pub fn PLLE2_ADV(CLKIN1: bool, CLKFBIN: bool, RST: bool, PWRDWN: bool, CLKIN1_PERIOD: comptime_float, REF_JITTER1: comptime_float, CLKFBOUT_MULT: comptime_int, DIVCLK_DIVIDE: comptime_int, CLKOUT0_DIVIDE: comptime_int, CLKOUT0_PHASE: comptime_int, STARTUP_WAIT: str) -> PllOut {} +/// CLKIN1_PERIOD and REF_JITTER1 are f64, not comptime_float: t27b, which runs these tests and lowers this file to the +/// board RTL, rejects a comptime_float parameter (#10313); gen-verilog no longer reads t27b bitstream specs (#10302). +pub fn PLLE2_ADV(CLKIN1: bool, CLKFBIN: bool, RST: bool, PWRDWN: bool, CLKIN1_PERIOD: f64, REF_JITTER1: f64, CLKFBOUT_MULT: comptime_int, DIVCLK_DIVIDE: comptime_int, CLKOUT0_DIVIDE: comptime_int, CLKOUT0_PHASE: comptime_int, STARTUP_WAIT: str) -> PllOut {} /// An input buffer, so the button reaches on_clock as an instance output (btn_O). pub struct IbufOut { O: bool }