From 0f14403f4a14318d75c5d31ea928d0a41282abee Mon Sep 17 00:00:00 2001 From: Dmitrii Vasilev Date: Sun, 18 Oct 2026 18:38:39 +0700 Subject: [PATCH] master red: three inherited checks fixed at their cause -- token_floor widths ledgered, rem arity text, former_name spelling (Closes #10439, Closes #10440, Closes #10441) - Verilog widths: token_floor.t27 emits [8388607:0] (rsp, the row index, 524288*16 bits) and [49766399:0] (bgq, the empty 1080x1920x3 frame). Both are exact working buffers of a host-side renderer; ledgered with the arithmetic like big_frame and suggest_feed. - t27b tail: the @rem arity case expects "`@rem` and `@mod` two", the text #10410 gave the refusal. - count-invariant: the nine tnf rows carry former_name="GF-TN (historical)" since #6953 (deliberate: it removed a name=/former_name= alias); the invariant, its planted tree and its negative control now expect that. Co-Authored-By: Claude Sonnet 5.5 --- cli/t27b/tests/tail.rs | 2 +- tools/check_catalog_integrity.py | 10 +++++----- tools/verilog_width_baseline.txt | 16 ++++++++++++++++ 3 files changed, 22 insertions(+), 6 deletions(-) diff --git a/cli/t27b/tests/tail.rs b/cli/t27b/tests/tail.rs index 056f2a92fa..4a8b0406ff 100644 --- a/cli/t27b/tests/tail.rs +++ b/cli/t27b/tests/tail.rs @@ -349,7 +349,7 @@ fn a_comptime_int_rounds_in_float_from_int() { fn f32_rounding_and_rem_call_their_ports() { let src = "module a;\n\nfn f(x: f32) -> f32 {\n return @round(x) + @floor(x) + @ceil(x) + @trunc(x) + @rem(x, 2.0);\n}\n\ntest t {\n assert(f(-2.5) == -10.5);\n}\n"; assert_eq!(names_ok(&run(src)), vec![("t", false, true)]); - for (from, to, what, why) in [("x: f32) -> f32", "x: f64) -> f64", "@trunc", "no f64 routine"), ("@rem(x, 2.0)", "@rem(x)", "@rem", "`@rem` two")] { + for (from, to, what, why) in [("x: f32) -> f32", "x: f64) -> f64", "@trunc", "no f64 routine"), ("@rem(x, 2.0)", "@rem(x)", "@rem", "`@rem` and `@mod` two")] { let m = rejected(&src.replace(from, to)); assert!(m.contains(&format!("construct ExprCall({}) at line 4", what)) && m.contains(why), "{}", m); } diff --git a/tools/check_catalog_integrity.py b/tools/check_catalog_integrity.py index 5ac9c5108a..0481e79660 100644 --- a/tools/check_catalog_integrity.py +++ b/tools/check_catalog_integrity.py @@ -108,7 +108,7 @@ def check(root): for m in re.finditer(r"id=(tnf\d+)\b", text): rung = m.group(1) row = text[m.start():text.find("\n", m.start())] - want = 'former_name="GF-T%s"' % rung[3:] + want = 'former_name="GF-T%s (historical)"' % rung[3:] if want not in row: problems.append(f"LOST {rung} no longer carries {want}") @@ -137,7 +137,7 @@ def check(root): 'id=gf16 name="GF16" bits=16 source="specs/numeric/gf16.t27"', 'id=gft16 name="GF-T16" bits=16 source="specs/numeric/gft16.t27"', 'id=bnf16 name="BNF16" bits=16 source="specs/numeric/bnf16.t27"', - 'id=tnf16 name="TNF16" former_name="GF-T16" bits=16 source="specs/numeric/tnf16.t27"', + 'id=tnf16 name="TNF16" former_name="GF-T16 (historical)" bits=16 source="specs/numeric/tnf16.t27"', 'id=gfternary name="GFTernary" bits=2 source="specs/numeric/gfternary.t27"', ] _RULE = " // Closed-form normative rule: e = round((N-1)/phi^2); m = N-1-e;" @@ -147,7 +147,7 @@ def check(root): # somewhere else in the file a `row`->`text` slip stops the check from ever # firing. Without this line the two spellings are indistinguishable and that # mutant survives. Must contain no `id=`, or it would join `ids`. -_PROSE = ' // T82: every tnf rung carries former_name="GF-T16" and its siblings.' +_PROSE = ' // T82: every tnf rung carries former_name="GF-T16 (historical)" and its siblings.' def _plant(td, rows=None, specs=None, rule=True): @@ -253,9 +253,9 @@ def drop(sub): # the thing that must be absent -- the exit code alone cannot tell them # apart, and neither can the first word. case("5 former_name stripped", - ['LOST tnf16 no longer carries former_name="GF-T16"'], + ['LOST tnf16 no longer carries former_name="GF-T16 (historical)"'], absent=("DANGLING", "MISSING", "COLLAPSED", "ALIAS", "golden-section"), - rows=[r.replace(' former_name="GF-T16"', '') for r in _ROWS]) + rows=[r.replace(' former_name="GF-T16 (historical)"', '') for r in _ROWS]) # 6. The golden-section rule string gone from the file. case("6 golden-section rule gone", diff --git a/tools/verilog_width_baseline.txt b/tools/verilog_width_baseline.txt index f9a87cfcfc..03728a37ae 100644 --- a/tools/verilog_width_baseline.txt +++ b/tools/verilog_width_baseline.txt @@ -58,3 +58,19 @@ specs/tri/t27b/conformance/big_frame.t27 # fo [524289]u8, arena [262144]u8), which the emitter prints as [2097151:0] # and [4194311:0]. Host-side text plumbing with no hardware form (#10365). specs/claw/suggest_feed.t27 +# +# specs/t27f/token_floor.t27 -- not a bus: the frame renderer's working +# memory. Two locals of the frame function, and both widths are exact: +# +# rsp : [524288]u16 = 524288*16 = 8,388,608 bits -> [8388607:0] +# the per-frame row index (#10391): each raster row visits only the +# splats that touch it; INDEX_CAP entries, sized by index_bound() +# bgq : [6220800]u8 = 6220800*8 = 49,766,400 bits -> [49766399:0] +# the empty scene, 1080*1920*3 bytes, computed once and copied into +# every pixel no splat visits (#10407) +# +# Neither can shrink without removing what the spec does: the index is what +# makes a frame cost its splats rather than its pixels, and bgq is one whole +# video frame. The spec renders a 1080x1920 video on a host; it has no +# hardware form. Same class as big_frame.t27 and suggest_feed.t27. +specs/t27f/token_floor.t27