From 21e7e697c576df96bce7830724a09ce7bce53f4b Mon Sep 17 00:00:00 2001 From: Dmitrii Vasilev Date: Mon, 19 Oct 2026 12:41:05 +0700 Subject: [PATCH 1/6] analog: rename sar_adc's Range to SarErrRange, a second type named Range broke the types ratchet (Closes #10887) Co-Authored-By: Claude Opus 5.5 --- .trinity/seals/analog_AnalogSarAdc.json | 14 +++++++------- specs/analog/sar_adc.t27 | 10 +++++----- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/.trinity/seals/analog_AnalogSarAdc.json b/.trinity/seals/analog_AnalogSarAdc.json index 59ca136c6f..85133da4ea 100644 --- a/.trinity/seals/analog_AnalogSarAdc.json +++ b/.trinity/seals/analog_AnalogSarAdc.json @@ -1,5 +1,5 @@ { - "built_by": "t27c-bootstrap@0.5.2+ea35d9b72", + "built_by": "t27c-bootstrap@0.5.2+d01578dd2", "closure": [ { "spec": "specs/analog/linear.t27", @@ -11,16 +11,16 @@ } ], "config": "gen=c,rust,verilog,zig;tests=zig", - "gen_hash_c": "sha256:190cf9c7a9bbc52e2ff243a068d5a52cef270186bb973987eccac07f356766a3", - "gen_hash_rust": "sha256:c022f3879d7688e5ab333d9a2aa777d397f1abc693347dd7d8a53aa44d77d051", - "gen_hash_verilog": "sha256:099481e4176136e97c8f372988dbd2fb9cb69cdfaaf4a3fd6b33a96bc3457a65", - "gen_hash_zig": "sha256:2e98efa78c53a211ce004f0b1480314821d694a39abc8b3091232e4394c1e616", + "gen_hash_c": "sha256:b0eb2581b1c9f1731babb89727e2e5047d82ce38a19f29d02794843811f1ec47", + "gen_hash_rust": "sha256:258a5f52785ad36cbb6fe27b08a3a270e2a79fb5905c0196add329cc280bcb57", + "gen_hash_verilog": "sha256:9de284e5fb8c5873672a597ae0489da971b346d0818d4932b16209a1444c0eb9", + "gen_hash_zig": "sha256:2d7c14ee09193405dc773b749442f1268ec6f38bf07b189c023d19f6266b4266", "module": "AnalogSarAdc", "ring": 12, "seal_schema": 2, - "sealed_at": "2026-10-19T04:48:15Z", + "sealed_at": "2026-10-19T05:40:23Z", "sealed_by": "t27c-bootstrap@0.5.2", - "spec_hash": "sha256:cedecad9b8f1a481da765debb6c64cc4c9c2a4567953dba05367fe6d7ff76094", + "spec_hash": "sha256:ec9bb693e1533ef4de9a62e2afec2d788e6e347de76329a1a7774e8485b5c76c", "spec_path": "specs/analog/sar_adc.t27", "tests": { "failed": 0, diff --git a/specs/analog/sar_adc.t27 b/specs/analog/sar_adc.t27 index 3cb3cd5001..ee7b291176 100644 --- a/specs/analog/sar_adc.t27 +++ b/specs/analog/sar_adc.t27 @@ -357,10 +357,10 @@ pub fn miss_margins(k: []const u32, off: u32, vp: []const f64, vn: []const f64, return Margins { sum: sum, worst: worst }; } -pub struct Range { lo: f64, hi: f64 } +pub struct SarErrRange { lo: f64, hi: f64 } /// The smallest and the largest signed code error (model - ngspice) over the 31 conversions. -pub fn err_range(k: []const u32, off: u32, vp: []const f64, vn: []const f64) -> Range { +pub fn err_range(k: []const u32, off: u32, vp: []const f64, vn: []const f64) -> SarErrRange { var lo : f64 = 0.0; var hi : f64 = 0.0; var i : usize = 0; @@ -371,7 +371,7 @@ pub fn err_range(k: []const u32, off: u32, vp: []const f64, vn: []const f64) -> if (e > hi) { hi = e; } i = i + 1; } - return Range { lo: lo, hi: hi }; + return SarErrRange { lo: lo, hi: hi }; } ; --- the fit: two numbers the merged blocks do not have --------------------------------------------------------------------- @@ -534,7 +534,7 @@ test the_merged_blocks_as_they_are_match_none_of_the_conversions_and_the_error_h i = i + 1; } // model - ngspice: the model is 12 codes above ngspice at the low end of the sine and 21 codes below it at the high end - const r : Range = err_range(&k0, 0, &S_VP, &S_VN); + const r : SarErrRange = err_range(&k0, 0, &S_VP, &S_VN); assert_eq(r.lo, 0.0 - 21.0); assert_eq(r.hi, 12.0); // the error is a straight line, a gain and an offset: ngspice's code about the middle (1023.5) is a times the model's plus b, by @@ -613,7 +613,7 @@ test with_the_top_plate_parasitic_and_the_comparator_offset_30_of_31_conversions const mm : Margins = miss_margins(&kf, off, &S_VP, &S_VN, 2); assert(mm.worst < 0.0003); assert(mm.worst > 0.0001); - const r : Range = err_range(&kf, off, &S_VP, &S_VN); + const r : SarErrRange = err_range(&kf, off, &S_VP, &S_VN); assert_eq(r.lo, 0.0 - 1.0); assert_eq(r.hi, 0.0); // one LSB of the 11-bit code is VDD / 1023 = 1.466 mV: the misses are within 0.15 of it From d66dd28e83d51f659328175a38e6f740bc4ac0c2 Mon Sep 17 00:00:00 2001 From: Dmitrii Vasilev Date: Mon, 19 Oct 2026 12:53:29 +0700 Subject: [PATCH 2/6] t27b ledger: rows for sar_adc, tri/worktrees/reap and ml/ngram_hslm, not-pass 129 at cap 129 (Refs #10887) #10862 auto-merged at 330dd0aef, one push before its sar_adc and reap rows, so master's native ratchet reports them UNLISTED. ngram_hslm takes the last free slot. Co-Authored-By: Claude Opus 5.5 --- docs/reports/t27b_expectations.json | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/docs/reports/t27b_expectations.json b/docs/reports/t27b_expectations.json index 48026f85f1..c5e6343035 100644 --- a/docs/reports/t27b_expectations.json +++ b/docs/reports/t27b_expectations.json @@ -49,6 +49,7 @@ {"path": "specs/analog/mos_psp103.t27", "t27b": "pass"}, {"path": "specs/analog/mos_psp103_data.t27", "t27b": "pass"}, {"path": "specs/analog/mos_table.t27", "t27b": "pass"}, + {"path": "specs/analog/sar_adc.t27", "t27b": "pass"}, {"path": "specs/analog/sar_cdac.t27", "t27b": "pass"}, {"path": "specs/analog/sar_comparator.t27", "t27b": "pass"}, {"path": "specs/analog/sar_logic.t27", "t27b": "pass"}, @@ -568,6 +569,7 @@ {"path": "specs/ml/loss/huber_loss.t27", "t27b": "pass"}, {"path": "specs/ml/loss/kl_divergence.t27", "t27b": "pass"}, {"path": "specs/ml/loss/mse_loss.t27", "t27b": "pass"}, + {"path": "specs/ml/ngram_hslm.t27", "t27b": "blocked", "blocker": "ExprCall(undeclared fn)", "reason": "unimplemented"}, {"path": "specs/ml/optimizer/adagrad.t27", "t27b": "pass"}, {"path": "specs/ml/optimizer/adam.t27", "t27b": "pass"}, {"path": "specs/ml/optimizer/adamw.t27", "t27b": "pass"}, @@ -1968,10 +1970,12 @@ {"path": "specs/tri/t27b/tuple_local_plan.t27", "t27b": "pass"}, {"path": "specs/tri/t27b/type_text.t27", "t27b": "pass"}, {"path": "specs/tri/t27b/undefined_arg_plan.t27", "t27b": "pass"}, + {"path": "specs/tri/t27b/usage.t27", "t27b": "pass"}, {"path": "specs/tri/t27b/verdict_key.t27", "t27b": "pass"}, {"path": "specs/tri/t27b/verilog_emit.t27", "t27b": "pass"}, {"path": "specs/tri/t27b/verilog_plan.t27", "t27b": "pass"}, {"path": "specs/tri/t27b/void_bind_plan.t27", "t27b": "pass"}, + {"path": "specs/tri/t27b/watch_build.t27", "t27b": "pass"}, {"path": "specs/tri/t27b/wide_plan.t27", "t27b": "pass"}, {"path": "specs/tri/test/report.t27", "t27b": "pass"}, {"path": "specs/tri/trees/avl_tree.t27", "t27b": "pass"}, @@ -1994,6 +1998,7 @@ {"path": "specs/tri/utils/time.t27", "t27b": "blocked", "blocker": "ExprCall(@divFloor)", "reason": "unimplemented"}, {"path": "specs/tri/utils/utf8.t27", "t27b": "pass"}, {"path": "specs/tri/utils/version.t27", "t27b": "pass"}, + {"path": "specs/tri/worktrees/reap.t27", "t27b": "pass"}, {"path": "specs/trinet/eth_top_ax7203.t27", "t27b": "pass"}, {"path": "specs/trinet/etx.t27", "t27b": "pass"}, {"path": "specs/trinet/ledger.t27", "t27b": "pass"}, From a4053e57bbef6d6afee4028f1254b302d1f3dfff Mon Sep 17 00:00:00 2001 From: Dmitrii Vasilev Date: Mon, 19 Oct 2026 13:16:11 +0700 Subject: [PATCH 3/6] analog: take master's ErrRange rename from #10892, keep only the missing ledger rows (Refs #10887) #10892 renamed sar_adc's Range to ErrRange on master, so this branch's SarErrRange rename now conflicts. The spec and its seal are set to master's. The ledger is master's (d0959ff17) plus the three rows master still lacks: sar_adc and worktrees/reap pass, ngram_hslm blocked. Not-pass is 129, which equals the cap, so loop-tools-tracked's "cap equals reality" holds again. Co-Authored-By: Claude Opus 5.5 --- .trinity/seals/analog_AnalogSarAdc.json | 14 +++++++------- docs/reports/t27b_expectations.json | 5 +++++ specs/analog/sar_adc.t27 | 10 +++++----- 3 files changed, 17 insertions(+), 12 deletions(-) diff --git a/.trinity/seals/analog_AnalogSarAdc.json b/.trinity/seals/analog_AnalogSarAdc.json index 85133da4ea..f385d47e2f 100644 --- a/.trinity/seals/analog_AnalogSarAdc.json +++ b/.trinity/seals/analog_AnalogSarAdc.json @@ -1,5 +1,5 @@ { - "built_by": "t27c-bootstrap@0.5.2+d01578dd2", + "built_by": "t27c-bootstrap@0.5.2+ea35d9b72", "closure": [ { "spec": "specs/analog/linear.t27", @@ -11,16 +11,16 @@ } ], "config": "gen=c,rust,verilog,zig;tests=zig", - "gen_hash_c": "sha256:b0eb2581b1c9f1731babb89727e2e5047d82ce38a19f29d02794843811f1ec47", - "gen_hash_rust": "sha256:258a5f52785ad36cbb6fe27b08a3a270e2a79fb5905c0196add329cc280bcb57", - "gen_hash_verilog": "sha256:9de284e5fb8c5873672a597ae0489da971b346d0818d4932b16209a1444c0eb9", - "gen_hash_zig": "sha256:2d7c14ee09193405dc773b749442f1268ec6f38bf07b189c023d19f6266b4266", + "gen_hash_c": "sha256:c8621c9cb85a4f0990075a906c901964df0b4c48d37206057ec1d4265ccdea30", + "gen_hash_rust": "sha256:f63529e07003b67b4d34a5a999c0095daae6732a8c3e56093dcb17fcf9573947", + "gen_hash_verilog": "sha256:3281bec146dd8f240de65ffc8a867647645c8a6af1c56303eba2e7fe35289005", + "gen_hash_zig": "sha256:9fa3aa4789bcb6d02177add93c6613f6720c4f7c59b2e6b3e65b3accf66b7048", "module": "AnalogSarAdc", "ring": 12, "seal_schema": 2, - "sealed_at": "2026-10-19T05:40:23Z", + "sealed_at": "2026-10-19T05:44:03Z", "sealed_by": "t27c-bootstrap@0.5.2", - "spec_hash": "sha256:ec9bb693e1533ef4de9a62e2afec2d788e6e347de76329a1a7774e8485b5c76c", + "spec_hash": "sha256:48e8825a4a6a7fc24ce23472bcba5499dcafbd399ac45a14fb153a0a020018e2", "spec_path": "specs/analog/sar_adc.t27", "tests": { "failed": 0, diff --git a/docs/reports/t27b_expectations.json b/docs/reports/t27b_expectations.json index c5e6343035..3ecc55bcff 100644 --- a/docs/reports/t27b_expectations.json +++ b/docs/reports/t27b_expectations.json @@ -202,14 +202,18 @@ {"path": "specs/claw/gates.t27", "t27b": "pass"}, {"path": "specs/claw/gates_pins.t27", "t27b": "pass"}, {"path": "specs/claw/github_surface.t27", "t27b": "pass"}, + {"path": "specs/claw/lab_disk.t27", "t27b": "pass"}, + {"path": "specs/claw/lab_receipt.t27", "t27b": "pass"}, {"path": "specs/claw/ledger_union.t27", "t27b": "pass"}, {"path": "specs/claw/merge_lane.t27", "t27b": "pass"}, {"path": "specs/claw/model_route.t27", "t27b": "pass"}, {"path": "specs/claw/move_gate.t27", "t27b": "pass"}, + {"path": "specs/claw/mut_known.t27", "t27b": "pass"}, {"path": "specs/claw/preview.t27", "t27b": "pass"}, {"path": "specs/claw/push_gate.t27", "t27b": "pass"}, {"path": "specs/claw/queue_cost.t27", "t27b": "pass"}, {"path": "specs/claw/recipes.t27", "t27b": "pass"}, + {"path": "specs/claw/red_origin.t27", "t27b": "pass"}, {"path": "specs/claw/reel_still.t27", "t27b": "pass"}, {"path": "specs/claw/refresh.t27", "t27b": "pass"}, {"path": "specs/claw/required_red.t27", "t27b": "pass"}, @@ -1515,6 +1519,7 @@ {"path": "specs/t27f/frame_cache.t27", "t27b": "pass"}, {"path": "specs/t27f/frame_shard.t27", "t27b": "blocked", "blocker": "type [N]T", "reason": "unimplemented"}, {"path": "specs/t27f/frontend.t27", "t27b": "pass"}, + {"path": "specs/t27f/glyph57.t27", "t27b": "pass"}, {"path": "specs/t27f/hot.t27", "t27b": "pass"}, {"path": "specs/t27f/idea_factory.t27", "t27b": "pass"}, {"path": "specs/t27f/lesson_reel.t27", "t27b": "blocked", "blocker": "type [N]T", "reason": "unimplemented"}, diff --git a/specs/analog/sar_adc.t27 b/specs/analog/sar_adc.t27 index ee7b291176..99962815dc 100644 --- a/specs/analog/sar_adc.t27 +++ b/specs/analog/sar_adc.t27 @@ -357,10 +357,10 @@ pub fn miss_margins(k: []const u32, off: u32, vp: []const f64, vn: []const f64, return Margins { sum: sum, worst: worst }; } -pub struct SarErrRange { lo: f64, hi: f64 } +pub struct ErrRange { lo: f64, hi: f64 } /// The smallest and the largest signed code error (model - ngspice) over the 31 conversions. -pub fn err_range(k: []const u32, off: u32, vp: []const f64, vn: []const f64) -> SarErrRange { +pub fn err_range(k: []const u32, off: u32, vp: []const f64, vn: []const f64) -> ErrRange { var lo : f64 = 0.0; var hi : f64 = 0.0; var i : usize = 0; @@ -371,7 +371,7 @@ pub fn err_range(k: []const u32, off: u32, vp: []const f64, vn: []const f64) -> if (e > hi) { hi = e; } i = i + 1; } - return SarErrRange { lo: lo, hi: hi }; + return ErrRange { lo: lo, hi: hi }; } ; --- the fit: two numbers the merged blocks do not have --------------------------------------------------------------------- @@ -534,7 +534,7 @@ test the_merged_blocks_as_they_are_match_none_of_the_conversions_and_the_error_h i = i + 1; } // model - ngspice: the model is 12 codes above ngspice at the low end of the sine and 21 codes below it at the high end - const r : SarErrRange = err_range(&k0, 0, &S_VP, &S_VN); + const r : ErrRange = err_range(&k0, 0, &S_VP, &S_VN); assert_eq(r.lo, 0.0 - 21.0); assert_eq(r.hi, 12.0); // the error is a straight line, a gain and an offset: ngspice's code about the middle (1023.5) is a times the model's plus b, by @@ -613,7 +613,7 @@ test with_the_top_plate_parasitic_and_the_comparator_offset_30_of_31_conversions const mm : Margins = miss_margins(&kf, off, &S_VP, &S_VN, 2); assert(mm.worst < 0.0003); assert(mm.worst > 0.0001); - const r : SarErrRange = err_range(&kf, off, &S_VP, &S_VN); + const r : ErrRange = err_range(&kf, off, &S_VP, &S_VN); assert_eq(r.lo, 0.0 - 1.0); assert_eq(r.hi, 0.0); // one LSB of the 11-bit code is VDD / 1023 = 1.466 mV: the misses are within 0.15 of it From 1c0d8c34a048abfb9dad7fc497c94e3db2f41947 Mon Sep 17 00:00:00 2001 From: Dmitrii Vasilev Date: Mon, 19 Oct 2026 13:24:22 +0700 Subject: [PATCH 4/6] tri/worktrees/reap: a neutral home path in the plain() test, so the devhome guard passes (Refs #10887) The scan check's check_devhome_paths.py fails on master for this line: it named a developer's home directory. The test only needs a plain path, so it now uses /Users/dev/. The seal is re-saved in the next commit. Co-Authored-By: Claude Opus 5.5 --- specs/tri/worktrees/reap.t27 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/specs/tri/worktrees/reap.t27 b/specs/tri/worktrees/reap.t27 index 93c7d1c64f..f328d96d66 100644 --- a/specs/tri/worktrees/reap.t27 +++ b/specs/tri/worktrees/reap.t27 @@ -250,7 +250,7 @@ test a_lock_is_held_by_nobody_a_live_pid_a_dead_one_or_an_unknown { test a_branch_and_a_path_are_plain_or_not { assert plain("claude/tri-worktrees-reap-10805") == true; assert plain("worktree-agent-a5476fea5f7b1db56") == true; - assert plain("/Users/playom/t27/.claude/worktrees/agent-a1a8e2b61031e3d98") == true; + assert plain("/Users/dev/t27/.claude/worktrees/agent-a1a8e2b61031e3d98") == true; assert plain("/private/tmp/claude-501/-Users-playom/04183dc5-60f9/scratchpad/epic/wt_4a") == true; assert plain("") == false; assert plain("/Users/play om/t27") == false; From a0bf414ecc3a765b6540bae92ff331df75ead3fb Mon Sep 17 00:00:00 2001 From: Dmitrii Vasilev Date: Mon, 19 Oct 2026 13:24:44 +0700 Subject: [PATCH 5/6] tri/worktrees/reap: re-save the seal after the test path change (Refs #10887) Railway lab, t27c built from master: 13 tests, 0 FAIL, 0 vacuous; seal --verify all hashes MATCH. Co-Authored-By: Claude Opus 5.5 --- .trinity/seals/worktrees_TriWorktreeReap.json | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.trinity/seals/worktrees_TriWorktreeReap.json b/.trinity/seals/worktrees_TriWorktreeReap.json index d5560e48d7..2bd4fa8590 100644 --- a/.trinity/seals/worktrees_TriWorktreeReap.json +++ b/.trinity/seals/worktrees_TriWorktreeReap.json @@ -1,5 +1,5 @@ { - "built_by": "t27c-bootstrap@0.5.2+ea35d9b72", + "built_by": "t27c-bootstrap@0.5.2+ae19b93cd", "closure": [ { "spec": "specs/tri/lab/receipt.t27", @@ -11,16 +11,16 @@ } ], "config": "gen=c,rust,verilog,zig;tests=zig", - "gen_hash_c": "sha256:8d09198aa53a8bdc23093d3cffb3512bc8380d7489f2246d662f60e96ab45a1d", + "gen_hash_c": "sha256:ef394961ea6804088b9a81da13baebb8f1cbfe6e1187e62e3f7122b17c234c4c", "gen_hash_rust": "sha256:a2b4fae679bfa41d9985a8c72810452a1748b7a490f224082d1d07b617ba9bd5", "gen_hash_verilog": "sha256:716b12e948192e930b1e51c9f46cf0a674355d58e9e87d00137b27cbdadab708", - "gen_hash_zig": "sha256:624311ddde0ac3622b5eeb5ef74a1e74b6ec59bd944d2ff8157f828947de373e", + "gen_hash_zig": "sha256:8096bea0fc9750a5617560324c12c28001d6204e2371f65177005bb33612153d", "module": "TriWorktreeReap", "ring": 12, "seal_schema": 2, - "sealed_at": "2026-10-19T03:51:32Z", + "sealed_at": "2026-10-19T06:24:35Z", "sealed_by": "t27c-bootstrap@0.5.2", - "spec_hash": "sha256:b01a0e09684d6e3c6c055a8a6f9efb69215f2f0ac4ffeff1a5df33fa403748fd", + "spec_hash": "sha256:e6181a331c212c15d5bd38a26ab84a2d0f8f5885e7fcf2ae686063d219311016", "spec_path": "specs/tri/worktrees/reap.t27", "tests": { "failed": 0, From a2e564e9952cb5095168a686579d603ef41f6f72 Mon Sep 17 00:00:00 2001 From: Dmitrii Vasilev Date: Mon, 19 Oct 2026 13:31:18 +0700 Subject: [PATCH 6/6] ledger: name mos_psp103_50c_data and sar_comparator_psp, both pass on master (Refs #10887) Master merged both specs without ledger rows, so t27b-native-ratchet reports them UNLISTED on every open PR. Both pass the reference and t27b; not-pass stays 129 = cap. Co-Authored-By: Claude Opus 5.5 --- docs/reports/t27b_expectations.json | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/reports/t27b_expectations.json b/docs/reports/t27b_expectations.json index 3ecc55bcff..6ca382f91b 100644 --- a/docs/reports/t27b_expectations.json +++ b/docs/reports/t27b_expectations.json @@ -47,11 +47,13 @@ {"path": "specs/analog/linear.t27", "t27b": "pass"}, {"path": "specs/analog/linear_zoh.t27", "t27b": "blocked", "blocker": "ExprCall(@sin)", "reason": "unimplemented"}, {"path": "specs/analog/mos_psp103.t27", "t27b": "pass"}, + {"path": "specs/analog/mos_psp103_50c_data.t27", "t27b": "pass"}, {"path": "specs/analog/mos_psp103_data.t27", "t27b": "pass"}, {"path": "specs/analog/mos_table.t27", "t27b": "pass"}, {"path": "specs/analog/sar_adc.t27", "t27b": "pass"}, {"path": "specs/analog/sar_cdac.t27", "t27b": "pass"}, {"path": "specs/analog/sar_comparator.t27", "t27b": "pass"}, + {"path": "specs/analog/sar_comparator_psp.t27", "t27b": "pass"}, {"path": "specs/analog/sar_logic.t27", "t27b": "pass"}, {"path": "specs/analog/sar_switch.t27", "t27b": "pass"}, {"path": "specs/api/c_abi.t27", "t27b": "pass"},