diff --git a/docs/analog/competitors.md b/docs/analog/competitors.md index 241b94a872..f53d2a30ae 100644 --- a/docs/analog/competitors.md +++ b/docs/analog/competitors.md @@ -1,6 +1,7 @@ # t27 analog emulation v0.1 - competitors, prior art, weaknesses Date of research: 2026-10-18. Method: web search plus page/PDF reads. English, ASCII only. +Section 11 (added 2026-10-19) revisits the weaknesses of section 7 against the measurements of M0 to M5 and adds a competitor delta; sections 0 to 8 are left as written on 2026-10-18. ## 0. How to read this file @@ -409,6 +410,34 @@ AI-native analog - analogdb - https://arxiv.org/abs/2609.01286 - cadence-virtuoso - https://www.eejournal.com/industry_news/cadence-unleashes-the-future-of-analog-custom-and-rfic-design-with-pioneering-ai-powered-virtuoso-studio/ +Repository evidence for section 11 (spec: is specs/analog/.t27, spec:sar_adc_ax7203 is specs/fpga/sar_adc_ax7203.t27, spec:spice_convert is specs/tools/t27o/spice_convert.t27, all at origin/master c33aec9c1) +- epic - https://github.com/gHashTag/t27/issues/10486 +- ledger - https://github.com/gHashTag/t27/issues/10486#issuecomment-6251580882 +- pr-N - https://github.com/gHashTag/t27/pull/N for N = 8844, 10517, 10528, 10530, 10578, 10604, 10779, 10781, 10845, 10854, 10884, 10893, 10898, 10919, 10940, 10953, 11055 +- issues cited by number only - https://github.com/gHashTag/t27/issues/N for N = 10503, 10516, 10749, 10777, 10785, 10848, 10881, 10882, 10888, 10909, 10910, 10911, 10920, 10941, 10942, 11020, 11040 + +Competitor delta of section 11 (fetched 2026-10-19) +- ngspice-news - https://ngspice.sourceforge.io/news.html +- vacask-releases - https://codeberg.org/arpadbuermen/VACASK/releases +- vacask-nlnet - https://nlnet.nl/project/VACASK/ +- vacask-pypi - https://pypi.org/project/vacask-bin/0.3.4.dev0/ (search result only, the page did not load) +- openvaf-gh-commits - https://api.github.com/repos/arpadbuermen/OpenVAF/commits?per_page=3 +- openvaf-gh-releases - https://api.github.com/repos/arpadbuermen/OpenVAF/releases?per_page=3 +- xyce-gh-releases - https://api.github.com/repos/Xyce/Xyce/releases?per_page=3 +- cpphdl-gh-commits - https://api.github.com/repos/mirekez/cpphdl/commits?per_page=5 +- anasymod-gh-commits - https://api.github.com/repos/sgherbst/anasymod/commits?per_page=3 +- msdsl-gh-commits - https://api.github.com/repos/sgherbst/msdsl/commits?per_page=3 +- ihp-gh-commits - https://api.github.com/repos/IHP-GmbH/IHP-Open-PDK/commits?per_page=5 +- ihp-pin-commit - https://api.github.com/repos/IHP-GmbH/IHP-Open-PDK/commits/21133f219b1a6da10d803e345761e77415ceff40 +- typhoon-blog - https://www.typhoon-hil.com/blog/ +- opalrt-ehs-page - https://www.opal-rt.com/software/software-toolboxes/ehs/ +- mdpi-emt - https://doi.org/10.3390/electronics15030606 and https://api.crossref.org/works/10.3390/electronics15030606 +- e4ds-ni-its - https://www.e4ds.com/sub_view.asp?idx=23859&lang=en +- arxiv-sipm - https://arxiv.org/abs/2607.00841 +- cadence-palladium-page - https://www.cadence.com/en_US/home/tools/system-design-and-verification/emulation-and-prototyping/palladium.html (search result only) +- synopsys-darpa - https://www.design-reuse.com/news/news44966.html (search result only) +- siemens-veloce-cs - https://www.design-reuse.com/news/55733/siemens-veloce-cs.html (search result only) + ## 10. Gaps (what I could not establish) - Number format inside Typhoon, Plexim, dSPACE FPGA solvers: not published in pages read [U]. @@ -418,3 +447,148 @@ AI-native analog - ngspice official manual text on integration defaults: not read [U]. - The partner's self-checking analog evaluator: nothing public found [U]. - High-voltage MOS and HBT (VBIC) corner structure in IHP PDK: not read [U]. +- Added 2026-10-19: wall time of one bitstream build (yosys, nextpnr, bitstream) and the break-even run count: in no receipt, so no speed claim is allowed [U]. +- Added 2026-10-19: the ngspice options (klu, threads) of the 18 minute remote run of the golden deck: not recorded [U]. +- Added 2026-10-19: full text of the 2026 FPGA electromagnetic-transient solver paper (publisher page returned 403; only the Crossref record and an abstract excerpt were read) and of the NI ITS item (excerpt only) [U]. +- Added 2026-10-19: Synopsys and Siemens analog emulation in 2026: again no source found [U]. Vendor pages for Typhoon, Plexim and OPAL-RT carry no dates on their spec tables, so "new" cannot be decided from them [U]. +- Added 2026-10-19: VACASK, Xyce and ngspice on the golden SAR deck side by side (issue #10911): not run [U]. +- Added 2026-10-19: where the pinned IHP-Open-PDK commit 21133f21 lives: it resolves through the IHP-GmbH repository API to a merge dated 2026-09-08 of a pull request from a fork's upstream-sync branch, while the newest commit on the IHP-GmbH default branch list read the same day is dated 2026-09-01; whether the model files differ from upstream is not checked [U]. + +--- + +## 11. Status after M1-M5 + +Written 2026-10-19 against origin/master at c33aec9c1. Scope: the ten weaknesses of section 7, re-read against what this repository measured in M0 to M5 (epic gHashTag/t27#10486: M0, M1, M1b, M1c, the ngspice bench, M2a, M2b, M3a, M3b, M3c, M4a to M4d, M4e with its offset experiments and its board run, M5 first slice). It is the honest basis for the v0.1 release notes: it says what the work did not close. + +### Tags and sources in this section + +- Every number is copied from the source named next to it and is tagged [V] by default: I read it in the header or a test of a spec (written spec:, see section 9), in a PR body (PR #N), in the epic (the body of gHashTag/t27#10486 as fetched on 2026-10-19) or in its ledger comment (ledger, comment 6251580882). +- [I] is arithmetic or a reading by me on top of those numbers. [U] is a number or a check I looked for in the repository and did not find; nothing is estimated. [S] appears only in the competitor delta at the end. +- CLOSED means the acceptance check of section 7 passes on the circuits that matter (the SAR blocks). REDUCED means some clauses of it are measured and pass and others fail or are not measured. OPEN means the measurements do not change what section 7 says. No weakness is CLOSED: each has at least one clause that is measured as failing or not measured. +- Tally: 0 CLOSED, 8 REDUCED, 2 OPEN (W2 and W7). W11 to W19 are weak points found while building. + +### Status of W1 to W10 + +- W1: REDUCED. Exact zero-order-hold constants exist for the linear cell and are measured; the nonlinear path and the netlist path are still backward Euler. + - Measured: spec:linear_zoh (M1c, #10503, PR #10528) puts the exact constants into the same fabric step, no hardware change. LC tank Q = 200, amplitude after 100 periods against the analytic one: exact scheme 1.0003 in Q.24 (1.00000000000006 in f64), backward Euler 1.78e-7. Backward Euler order measured at dt, dt/2, dt/4: 0.985 and 0.993 (RC), 0.975 and 0.988 (RLC Q 1), 0.915 and 0.957 (RLC Q 20); the exact scheme is within 3e-14 of the analytic solution at every grid point. For the RLC the backward Euler discretization error is 1.89e-2 V against an arithmetic error of 5.0e-7 V, some 37000 times larger: the number section 7 said a bit-exact comparison with float64 cannot show. + - Not closed: the nonlinear path is backward Euler. spec:mos_psp103 (PR #10778): the inverter at dt = 2 ns differs from ngspice converged by 14.4 mV (242041 units) and its delays are 0.51 % and 0.66 % longer. spec:sar_switch (PR #10779): backward Euler at 250 ps against a grid five times finer moves the switch overdrive by 2.96 mV, the tracking error by 0.27 % and the injection by 4.5 %. The netlist path folds backward Euler only: spec:spice_convert refuses a deck without method=gear maxord=1 (PR #10781). No second-order option was added ("none is added here", spec:linear_zoh). A compile-time report of steps per period of the fastest pole: not found [U]. + - Next step: t27o emits the exact-ZOH constants for the linear part of a deck; the comparator's discretization at 0.1 ps is measured against a finer grid (spec:sar_comparator calls it "shared with ngspice by construction", that is, unmeasured). + +- W2: OPEN. The step is chosen by hand per block, its effect is measured once, and no stiffness report or multirate coupling exists. + - Evidence: a stiffness analysis, a steps-per-fastest-pole report or a multirate partition: not found in any spec [U] (the word "stiff" appears in specs/analog only in prose about the switch step and the DAC plates). Steps in use: comparator 0.1 ps, 140 steps (spec:sar_comparator); switch 250 ps, 416 steps, because 0.1 ps "would take 5 million steps for one 500 ns period" (spec:sar_switch); inverter 2 ns at 10 pF and 100 ps at 500 fF (spec:mos_psp103); gate logic as an event simulation with a 1 ps quantum (spec:sar_logic). The golden run is 16 us and ngspice's adaptive step needs 161633 time points for it (spec:sar_adc); one fixed 0.1 ps grid would need 1.6e8 steps, about 990 times as many [I]. The step matters: see the 2.96 mV overdrive shift under W1. The switch's damped Newton needs up to 120 iterations on the clock-fall step and 1.1 on average, so the work per step is data dependent exactly at the edges (spec:sar_switch). + - Next step: a per-block step table with a steps-per-fastest-pole check in t27o for linear blocks; decide how a 0.1 ps block and a 250 ps block are coupled in M4e at device level (today the converter takes the held plates from the ngspice run, spec:sar_adc). + +- W3: REDUCED. Drain and gate charge tables bring the 500 fF inverter within 0.02 % of ngspice; they exist for tt and ss only, and the comparator and the switch still carry no charge. + - Measured: M3c (PR #10893, sub-issue #10880 of #10777) tabulates drain and gate charge for tt and ss from the terminal current of one backward Euler step (PSP103 reports no terminal charge). The 500 fF inverter at dt = 100 ps against ngspice backward Euler on the same grid: delays within 0.020 % (tpLH) and 0.0041 % (tpHL), where current-only tables were 3.09 % and 3.63 % fast; worst waveform sample 6693 units (0.40 mV, 0.027 % of Vdd) against 438317 (26 mV) without charge; table slopes within 0.16 %, 0.29 % and 0.19 % of the capacitances ngspice itself reports; Newton residual at most 2 units at every step; the ss charge used in a tt run is refused by 2.5 to 3.6 times (spec:mos_psp103). + - Not closed: charge is tabulated for tt and ss only (ff, fs, sf: #10882, open), drain and gate only, for a 500 fF node and a 100 ps step; no circuit reads the gate charge; no source or bulk charge. The comparator is still current-only on PSP103: its decision at +2 mV is 5.35 ps in the model against 523.0 ps in ngspice with its own charge, 96 to 98 times too fast (resolution 155 to 183 times) (spec:sar_comparator_psp, PR #10884). The switch is square law with no gate capacitance, so no charge injection is modelled (spec:sar_switch). The transient is checked for tt only. Non-quasi-static behaviour, and the cyclic gate-sweep charge-conservation check of section 7: not found [U]. + - Next step: #10882; put the charge tables into the comparator and the switch and re-measure the 96 to 98 times. + +- W4: REDUCED. Five corners are tabulated for two device sizes within 0.56 % where Id >= 100 uA; weak inversion, body effect, a table per temperature and the run-time load on a board remain. + - Measured: spec:mos_psp103_data (M3b, #10516, PR #10778): sg13_lv_nmos W 1.0 um and sg13_lv_pmos W 3.0 um, L 0.45 um, five corners, 25 x 25 nodes of 62.5 mV (625 words each, under 2^21), IHP-Open-PDK commit 21133f21, 27 C. Against ngspice at held-out points (tt): absolute 6.51e-7 A (NMOS) and 4.39e-7 A (PMOS); relative 0.56 % and 0.41 % where Id >= 100 uA, 4.3 % and 3.2 % for Id >= 10 uA, 21 % and 17 % for Id >= 1 uA. The section 7 bound of 1 % with a 1e-9 A floor is NOT met (measured 0.55 to 0.73): in weak inversion Id grows 6.5 to 7 times per cell and a chord is more than 41 % above the exponential (follow-up #10881, open). Temperature is another table set: spec:mos_psp103_50c_data has the saturation current 5.8 % lower (NMOS) and 4.2 % lower (PMOS) at 50 C, and the 27 C tables in a 50 C comparator run decide 5.0 % early (resolution 6.0 %) (spec:sar_comparator_psp). The slopes gm and gds are those of the interpolant, constant per cell, so the 0.35 V threshold inside cell 5 gives a soft knee: 0.25 mV in the switch gate and 39.0 mV on one node (spec:sar_switch). The 2-D tables have no body effect: the golden comparator decides 6.2 to 6.5 % later than the bulk-tied one (spec:sar_comparator_psp). A multiplier m needs no table change (PSP103 multiplies the current by m). + - Not closed: board_step takes the two tables as slices a board would load (spec:mos_psp103), but no board top reads a table, and both board tops use 0 BRAM (PR #10578, PR #10919): "one bitstream per topology, not per corner" is a design, not a receipt. Tables for another W, L, mismatch or the high-voltage devices: not made [U]. + - Next step: #10881 and #10882; a Vsb dimension or a threshold-shift term; a table-load top on the AX7203. + +- W5: REDUCED. The arithmetic error is measured per circuit and every board receipt is bit-exact with its spec; there is no overflow flag and no range table. + - Measured: arithmetic error against float64 of the same scheme, in LSB of 2^-24 V, asserted from both sides: M1 RC 2.65, RLC 8.44, ladder-3 9.45, ladder-5 40.03 (bounds 3, 9, 10, 41), growing with 1 / (1 - rho) of the slowest pole (spec:linear); exact scheme 4.84, 9.61, 34.71 and 120.50 for the tank (spec:linear_zoh); inverter 0.61 unit (spec:mos_table) and 4.78 units (spec:mos_psp103); DAC 1.74 units (spec:sar_cdac); comparator 68.05 units (4.1 uV) at 2 mV and 250.8 units (15 uV) at 0.5 mV, amplified by the regeneration (spec:sar_comparator); switch 237 units (14 uV) (spec:sar_switch). Board receipts are bit-exact with the spec: M1b 572 of 572 lines PASS and each control prints FAIL (286 lines) on its own circuit only (PR #10578); the SAR converter 550 of 550 lines PASS and its control fails exactly the 16 predicted conversions (PR #10919). Headroom: magnitudes below 2^26 in M1 (asserted), the widest word 4.95e14 (under 2^49) in the comparator and 7.2e16 (2^56) in the switch at the clock edges, in a u64 (spec:linear, spec:sar_comparator, spec:sar_switch). An unsigned word with ground at 0 cannot hold the switch's -0.17 V, so the switch counts from an offset of 0.5 V (spec:sar_switch). + - Not closed: saturating arithmetic and a sticky overflow flag: not found in any spec or board top [U]; no table of analytic bound against used range per signal; ranges are asserted per run, not derived. The nonlinear solvers have not run in fixed point on a board (W16). + - Next step: a sticky overflow bit and a range table in the receipt of the next board top. + +- W6: REDUCED. A fixed number of Newton iterations with a bounded residual works on the inverter, the comparator and (damped) the switch; no oscillator or hold-state circuit has been run and no nonlinear step has been synthesised. + - Measured: every nonlinear cell runs a fixed K of Newton iterations per step and computes the residual after the last one at every step. Inverter K = 3, last residual at most 1 unit, K = 1 leaves 8586 (spec:mos_psp103); with charge at most 2 units, K = 1 leaves 11636. Comparator K = 3: at most 2 units on the square law (K = 1 leaves 29361 units, 1.75 mV) and at most 3 units on PSP103 tables (K = 2 leaves 155, K = 1 leaves 20750) (spec:sar_comparator, spec:sar_comparator_psp). On PSP103 tables the comparator decides the right way in all 14 runs (7 inputs down to 0.12 uV, two orientations), its decision time within 0.66 % and its resolution time within 0.72 % of the bulk-tied PSP103 reference. At 0 V of input the circuit in real arithmetic stays exactly symmetric, and in fixed point one unit of rounding at step 60 grows to 2027 units at step 100 and 2659643 (0.158 V) at step 140: reported, not hidden (spec:sar_comparator). The switch uses a damped Newton with a stop test, at most 120 iterations and 1.1 on average (spec:sar_switch). + - Not closed: the acceptance circuits of section 7 (a bistable latch held in a state, a three-stage ring oscillator within 5 % of ngspice) have no counterpart in specs/analog [U]; the SAR latch is the only regenerative circuit run. The switch's loop is a `while` with a flag that `t27b verilog` may refuse, and it has not been through it (spec:sar_switch). + - Next step: take the comparator step through t27b verilog and the open flow; report LUT, DSP, Fmax and clocks per step with the iteration bound as a counter and the residual as a status bit. + +- W7: OPEN. No speed claim is allowed: the only like-for-like row (M0) is a ratio of two fixed overheads, the build time is unmeasured, and the board runs a behavioural converter. + - Measured: spec:bench (PR #10517), ngspice-47 on the bench laptop (8 GB), median of 10 runs: wall 14228 us for the RC and 14813, 14607, 14659 and 15021 us for the RLC and the 3-, 5- and 10-node ladders; the .tran itself takes 796 us for the RC, so more than 90 % is start-up. M0 on the board: 1200 clocks at 100 MHz is 12 us of compute for 10 us of circuit time (0.83 times real time [I]), and the first full 108-character line at 115200 baud arrives after 9387 us (computed, not a stopwatch reading); the wall ratio is 1.52, a ratio of two fixed overheads, and the compute-only ratio of 66 is not a claim about a run. may_claim_speedup says no for every row because BUILD_US is 0: the bitstream build time is in no receipt. + - Since then: the golden SAR deck in ngspice-47 with PSP103 took 3894.9 s (65 minutes) of wall time, 3285.7 s of user time and 161633 time points, on the laptop while other jobs ran (load average 5 to 40) (spec:sar_adc, PR #10854); 18 minutes on a remote Docker host, 10 of 12 cores, the same 161633 points (ledger, tick 28), about 3.6 times shorter [I] but from two machines and not a controlled comparison; with option klu and 8 threads a slice of the deck took 153 s where the default took 275 s (epic, row of PR #10884). The board's SAR converter takes 75 clocks (0.75 us) per conversion and 63 characters (5.5 ms) per line (PR #10919), but it runs ROM samples and a sign comparator with two fitted numbers, so its spec calls a comparison with the 65 minutes "not a comparison of the same thing" (spec:sar_adc_ax7203). Bitstream build time and break-even run count: not measured [U]. + - Next step: put the wall time of one yosys, nextpnr and bitstream build in a receipt; until then no document states a speed claim. The only like-for-like row will be a nonlinear block solved on the fabric against ngspice on the same deck. + +- W8: REDUCED. The SPICE reader parses, flattens and refuses with the line; the device tables are not yet generated from the netlist and no 20-netlist regression set exists. + - Measured: spec:spice_convert (PR #10530, 22 tests; PR #10781, 39 tests) reads the whole golden SAR deck: 16 subcircuits, 57 MOS lines, 1265 MOS and 128 cap_cmim after flattening (epic); 113 gates for M4d: inverter 23, nor 44, nor3 1, tgate 44, delay cell 1 (spec:sar_logic). It refuses with the line and the reason: the element letters D Q J K M G F H S W T U O P Z Y, .measure, .func, .model, {expressions}, subcircuit parameters, instance parameters other than m (w l ng on PDK devices); .lib and .include are recorded and never followed, so no PDK file is read. Every table names the IHP-Open-PDK commit 21133f21 and ngspice-47 (spec:mos_psp103_data). + - Not closed: the device tables come from hand-written ngspice decks (psp103_tab_*.cir) for one NMOS and one PMOS size, not from the netlist. A regression set of at least 20 netlists classified accepted or refused: not found [U] (the set is the decks in specs/analog/decks and the golden deck). The PDK commit is in the spec headers, not in the board's receipt line. The SAR runs are one corner (mos_tt, cap_typ) at 50 C. The PDK content is a preview by its own statement (section 5.6). + - Next step: t27o emits the table deck for each distinct (model, W, L, m, temperature) of a netlist and refuses a device with no table; the PDK commit goes into the receipt. + +- W9: REDUCED. The RAW writer is byte-equal to ngspice's and read by uberWAVE's parser; the boards stream receipts, not waveforms. + - Measured: spec:raw_writer (M5, #10909, PR #10940, 18 tests): ASCII and binary files equal ngspice-47's own write byte for byte on the 15-point, 4-variable reference; %.15e equals Python's on 35 vectors; ngspice loads both files (load, print); uberWAVE's wp2-parser (commit c75a89c8f) parses both, the binary file bit-exact over 1005 values and the ASCII file within 4.4e-16 relative; `tri raw` writes the M1 RLC trace of 201 points; five writer mutants each fail. uberWAVE refuses a header of 202 points over 201 rows but accepts 200 (PR #10940). + - Not closed: bandwidth. The boards print receipt lines: 108 characters per M0 line (9375 us at 115200 baud) and 63 per SAR line (5.5 ms); both tops use 0 BRAM, so there is no capture buffer, trigger or decimation. M4e's trace as RAW and the partner's per-block checks on it are not done (epic, item 4 of what is left). That uberWAVE's viewer overlays our trace on ngspice's without conversion is shown for the parser only; no screenshot found [U]. + - Next step: M5 second half; a BRAM capture buffer with burst readout and a checksum compared with the spec's fold. + +- W10: REDUCED. Three errors are reported apart for the blocks up to M4c; M4b to M4d share the grid with ngspice by construction, and the converter is scored by code match. + - Measured: arithmetic, table and discretization are reported apart in M1c, M3a, M3b, M3c, M4b and M4c. M3a 29 nV, 0.428 mV and 27.2 mV (spec:mos_table); M3b at 10 pF 0.28 uV, 1.28 mV and 14.4 mV (spec:mos_psp103); M4b arithmetic 4.1 uV, table 15.2 mV, model against ngspice 1.44 nV (spec:sar_comparator); M4c arithmetic 14 uV, table 39.0 mV, model 0.5 nV, discretization 2.96 mV in the overdrive (spec:sar_switch). The h and h/2 check: spec:linear_zoh measures the order at dt, dt/2, dt/4 against the analytic solution and marks the Q = 20 circuit as not in the asymptotic regime at dt = 5 ns (0.84 over 400 steps). ngspice is a fixed-step reference to between 1e-15 and 9.4e-15 V with gear order 1, a B source and a pre-roll, where a plain PWL source is 1.7e-5 V off the recurrence at 5 us, and ngspice's own adaptive run is 2.4e-4 to 3.4e-4 V from the continuous circuit (spec:bench, PR #10517). + - Not closed: M4b and M4d state that the discretization is shared with ngspice by construction and is not measured (the comparator's times are the grid's); only M4c measured it, once. No error(h/2) / error(h) test exists for a nonlinear block. The converter is scored by code match, not by the three-error split, and the reference itself is not unique at the LSB (W15). + - Next step: measure the comparator at 0.1 ps and 0.05 ps against ngspice on both grids; report the converter's error as a code distance (W15). + +### Found while building (W11 onward) + +### W11. A UART defect only the board showed + +- Status: CLOSED for this defect; OPEN as a class (a behaviour that appears only at the real clock ratio). +- Evidence: the first capture of the SAR top on the AX7203 (PR #10919, spec:sar_adc_ax7203) had the right payload after K= on every line (top 551 lines, control 555), but every line after the first began with the same seven bytes 95 BA 02 9A 05 49 81 instead of "T27 SAR ". Cause: the transmitter set the restart flag at the shift that starts the LF's stop bit; the next conversion needs about 80 clocks, 0.09 of a bit time at 868 clocks a bit, so the next start bit cut the stop bit to a tenth of its time and a terminal lost frame alignment. A simulation at 8 clocks per bit did not show it (80 clocks were 10 bit times), and M1b is immune because its lines are tens of thousands of clocks apart. Fix: 8 flip-flops (a gap register, GAP_BITS = 2); 908 LUT (yosys), 538 FF, 0 DSP, 0 BRAM, 108.27 MHz after place and route (PR #10919, epic). Proof: a new test (13 in all, 28 asserts for it) runs the machine at the real divider 868 against a mid-bit receiver and counts 0 framing errors; reflashed: 550 of 550 lines PASS, 31 of 31 conversions, the control 282 FAIL and 268 PASS, exactly the 16 predicted conversions. A related instrument defect: an earlier "3252 of 3252" for M1b came from a capture split between files by stray readers and was retracted; only clean single-reader captures count (572 of 572) (epic, M1b row). +- Next step: every board top gets a test at its real bit divider with a mid-bit receiver that counts framing errors (the new test is the pattern), and a capture rule of one reader per port with the port free before each capture. + +### W12. The comparator offset needed a fitted number until its source was found + +- Status: REDUCED (the source is found and measured; it is not yet derived). +- Evidence: M4e (PR #10854) matched 30 of 31 conversions only with two fitted numbers, a top-plate load Cp of 0.63 units (77 fF) and an offset of +6.7 mV; as merged it matched 0 of 31 (model minus ngspice -21 to +12 codes, a straight line of gain 1.0199 and offset 4.60 codes) (spec:sar_adc). M4b-psp (PR #10884) showed the golden latch itself is not that offset: its flip point is 0 (model +0.12 uV, ngspice within 0.12 uV), and -0.153 mV with its loads. A first reading of the decision point (+2.5 to +3.1 mV) was taken inside the clock-edge kickback and had the wrong size; read before the edge it is 6.7 to 6.9 mV (spec:sar_adc). PR #10953 (spec:sar_kick, 10 tests) changes one thing at a time in ngspice with PSP103: base +9.42 mV at the first decision; ideal tracking switches +9.19 (moved by -0.23 +- 0.40); buffers between plates and comparator +0.03 (-9.38); both halves' bottom plates ideal +0.27 (-9.14); a resistor of one transmission gate's size (2592 ohm) added to each P plate -0.89 (-10.31). Mechanism: when the comparator clock rises, its input devices push charge into the two top plates, VDP falls by 22.7 mV and VDN by 30.2 mV, and the N half's bottom plates sit behind one more transmission gate than the P half's. Late decisions (the ones that set the codes): 6.66 mV (decision 9) and 6.90 mV (decision 10); the model takes their mean, 6.776 mV. With it, and Cp = 0.63: 29 of 31 conversions (misses: conversion 16, +1 code, and 25, -1 code); with Cp refitted alone, 30 of 31 at Cp = 0.634. Count by offset at Cp = 0.63: 6.6 mV 29, 6.7 mV 30, 6.9 mV 30, 7.0 mV 25, 7.1 mV 21. +- Next step: #10942: a circuit-level model of the plates' drive (gate and inverter resistances from the M3b tables, the DAC capacitors, the charge pulse from the M3c tables, solved by M1's step) with the six first-decision rows as targets. + +### W13. The cost and the hosts of the reference runs + +- Status: REDUCED. +- Evidence: the golden SAR deck, 16 us, 31 conversions, ngspice-47 with PSP103: 3894.9 s wall (65 minutes) on the shared laptop (spec:sar_adc); 18 minutes on a remote Docker host, 10 of 12 cores, with the same 161633 points, reproducing the pinned held plates to 0 uV from conversion 2 on (conversion 1: 7 and 12 uV; conversion 0, the start-up from .ic: 1.1 and 2.0 mV) (ledger, tick 28); on a slice, option klu with 8 threads 153 s against 275 s by default, 1.8 times [I] (epic). The toolchain cost something too: OpenVAF's bundled libraries had invalid code signatures on the laptop and the process ended with "Killed: 9" until they were re-signed (ledger, tick 8), and the laptop's disk reached 100 % with 251 MB free from other sessions' build folders, after which no build lane starts below 8 GB free (epic). `tri remote` (#11020, PR #11055) now runs a golden job on any ssh host from fixed command templates written in a spec, and #11040 plans one lab service; the host is never written in the repository. The ngspice options of the 18 minute run: not recorded [U]. +- Next step: record host class, cores, ngspice options and wall time of every reference run in its receipt; measure the build time too (W7). + +### W14. Fitted versus predicted + +- Status: REDUCED (one of two fitted numbers is now measured; none is derived). +- Evidence: row 2 of spec:sar_adc (30 of 31) was fitted on all 31 conversions and "describes this run"; the held-out checks are 14 of 15 (fit on the 16 even conversions, scored on the 15 odd) and 15 of 16 (the reverse). The optimum is narrow: Cp moved by -0.02 or +0.02 units leaves 23 or 20 of 31 matches, the offset moved by -1 or +1 mV leaves 11 or 6 (spec:sar_adc). Cp (0.63 units of 122.94 fF, 77 fF) is still a fit: the first plate step gives it from 0.58 to 0.85 units depending on how the plates are driven (spec:sar_kick). The offset is measured on the netlist (6.776 mV), not derived. The board's 30 of 31 equals its spec's fitted model: "describes this run and predicts nothing" (spec:sar_adc_ax7203). Other fitted numbers: SL_TG_IN_LOAD = 0.43 (a transmission gate's input load, set so the CK edges come out right, which makes CK11 to CK2 not an independent check), the delay cell's input loads and the 4 fF and 8 fF equivalents "fitted, not derived", SL_C2_PM fitted at one point (spec:sar_logic). The gate arcs d0 and k are measured by least squares over three loads, not fitted to the result they are judged by (spec:sar_logic). All SAR evidence is one deck, one sine, one corner (mos_tt, cap_typ) and one temperature (50 C). +- Next step: after #10942 and Cp from the M3c charge tables, re-score with nothing fitted on conversions the fit never saw (another sine amplitude or phase); every spec lists its constants as fitted, measured or derived, and a claim of "matches" names which. + +### W15. The reference is not unique at the LSB + +- Status: OPEN. +- Evidence: conversion 0 gives code 1006 in our ngspice-47 run and 1007 in the published ngspice-46 RAW of the same deck; the wrapper decks of the offset experiments also give 1007. The last decision of that conversion sits 0.006 mV from its flip (D = -6.889 mV, flip -6.895 mV): "a 0.01 mV difference between two simulations of the same circuit decides it" (spec:sar_kick). Otherwise 30 of 31 codes are identical between the two runs, the held plates agree to 0.007 mV and 0.012 mV from conversion 1 on, and the whole traces differ by at most 1.1 mV (VDP) and 1.3 mV (VDN) from 600 ns on, in edge timing (spec:sar_adc). The offset's spread by decision (6.66, 6.90, 7.10 and 6.98 mV for decisions 9, 10, 8, 7) is the size of what separates 29 from 30 matches (spec:sar_kick). The M4 acceptance of the epic, "every conversion code ... equals ngspice's", is therefore at the mercy of 0.01 mV. +- Next step: state the acceptance as "within one code, and the distance of each miss from its threshold in LSB" (the spec already gives 0.09 LSB for conversion 25), with the distances of all 31 conversions tabulated. + +### W16. The board runs the behavioural converter, not the circuit + +- Status: OPEN. +- Evidence: in the SAR top on the AX7203 the held samples, the DAC words and the pinned codes are ROMs, and the machine is a sign comparator plus the MSB-first sequence: 75 clocks per conversion, 908 LUT, 538 FF, 0 DSP, 0 BRAM; "the board holds ROMs of the samples: it does not sample anything" (spec:sar_adc_ax7203, PR #10919). The nonlinear solvers (inverter with charge, comparator, switch) are specs run by t27c test and t27b test; no board top contains one, and the switch spec says that none of it has been through t27b verilog (spec:sar_switch, spec:mos_psp103). Timing margin is thin and not stable: the SAR top placed at 124.60 MHz and, after 8 more flip-flops, at 108.27 MHz against a 100 MHz constraint on the default seed (PR #10919); M1b's controls placed at 87.84 and 99.32 MHz against 106.30 for the committed top (PR #10578). +- Next step: tables in BRAM (after #10881 and #10882), then the inverter and the comparator step on the fabric with receipts that report LUT, DSP, BRAM, Fmax and clocks per step. + +### W17. Gate-level logic is measured delays with fitted numbers + +- Status: REDUCED. +- Evidence: spec:sar_logic (M4d, PR #10845; M4d-b, PR #10898, #10848): 113 gates, CK11 to CK1 in the same order as ngspice with PSP103. The first version used settled delays and the repeated comparator-clock falls were 83 to 127 % late, because the delay cell remembers its last edge (#10848); with age tables measured in ngspice the repeated falls are within 1.8 % and the rises within 0.6 % (bound 8 %), seven held-out pulse trains within a worst case of 5.1 %. The CK edges were first 17 % early (458 ps against 548 ps); two causes were found, a drive-strength fight in the skew window (+47 ps) and a transmission gate's input load, which is one fitted number (+41 ps). Not covered: pulses with a high time under 14 ns or a low time under 16 ns (the tables are flat there and a scratch prototype was 17 % off), trim codes other than 000 (scaled from 000), any corner but tt at 50 C, and the closed loop with the comparator (spec:sar_logic). This is not a transistor-level model. +- Next step: close the loop with the comparator's own Valid at device level (M4e) and calibrate another trim code. + +### W18. No mismatch, noise or Monte Carlo + +- Status: OPEN. +- Evidence: every spec header closes with a list of what it does not say, and noise, mismatch and Monte Carlo are in it (spec:sar_comparator_psp, spec:sar_adc, spec:mos_psp103, spec:sar_logic). The comparator's imbalance is a deterministic multiplier: m of 35 or 34 instead of 36 on one input device gives flip points of +4.2665 and +8.689 mV in ngspice, so a 4.4 % imbalance would give the converter's 6.7 mV (spec:sar_comparator_psp). The IHP corner files carry mismatch and statistical sections (section 5.6) that no spec uses. One conversion of the 31 is decided 0.133 mV (0.09 LSB) from a threshold (conversion 25, spec:sar_adc), so a mismatch of that size changes codes [I]. +- Next step: a non-claim in the v0.1 release notes; later, a per-device multiplier as an input of the table solver and a distribution run on a remote host. + +### W19. Toolchain debts found on the way + +- Status: REDUCED. +- Evidence: the compiler PR #8844, "gen-verilog: an entry parameter named clk/rst_n/en is declared once; a void body's last call stays a statement", merged 2026-10-19 at 12:22 UTC; changes to the seals of analog_AnalogSar* were held until it landed, so PR #10893 and PR #10953 waited as drafts and merged at 13:43 and 13:48 UTC (ledger, ticks 21 and 27; GitHub close times). Still open: #10749 (frontier closure stale forever for specs two imports deep), #10785 (gen-rust lowers a local array passed to a mutable slice parameter to &mut &(w), which rustc refuses; one stamp in spec:spice_convert is written again because of it), #10920 (@bitCast between f64 and u64 is printed as written; spec:raw_writer builds the pair from arithmetic instead). t27b verilog refuses signed types, so every analog word is sign-magnitude (spec:linear), and array indexing, so the ROMs are if-chains (spec:sar_adc_ax7203). Two type-name collisions, Ring and Range, moved the types ratchet on master and were renamed (#10539, #10892). +- Next step: close #10749, #10785 and #10920; run the types ratchet in every review of an analog spec. + +### Competitor delta since 2026-10-18 + +Method: searches run on 2026-10-19 (WebSearch, extended mode for FPGA solvers, AMS emulation, VACASK, ngspice and FPGA circuit emulation, standard mode for the vendor lookups), then WebFetch of the primary page or of the public GitHub API for each hit, so most items are [V]. The window is one day long. The search tool is US-only and vendor spec pages carry no dates. + +Result: nothing new dated after 2026-10-18 was found for any of the items below. The positioning of sections 0 and 7 stands unchanged. What follows is the state of each tracked item on 2026-10-19, and three items the first pass missed that predate 2026-10-18. + +- FPGA circuit solvers for power electronics. Typhoon HIL: newest blog post 2026-10-14 ("De-Risking BESS Projects"), none on the solver or on new hardware [V] (src:typhoon-blog). OPAL-RT: the eHS product page, undated, lists a 32 ns minimum time step, up to 500 kHz switching, 625 ps oversampled sampling and a "250-node grid @ 500 ns", and does not state the number format [V] (src:opalrt-ehs-page); this differs from the 70 ns Gen5 figure of the documentation page cited in section 2.2, so the two vendor pages still disagree and nothing in it is new. NI: an e4ds item dated 2026-10-16 about the NI ITS inverter test system says "FPGA-based real-time simulation" with no step or solver, full text paywalled [V, excerpt] (src:e4ds-ni-its). Plexim: nothing new; the Nanostep 4 ns figure is from a search summary [S]. +- Academic FPGA solvers. Missed by the first pass, published 2026-01-29: Liang, Wu, Zhao and Huang, "A General FPGA-Based Accelerated Solver for Electromagnetic Transient Simulations", Electronics 15(3):606, an offline power-system accelerator checked against a CPU-only platform; Crossref metadata and abstract excerpt read, full text not (403) [V for metadata, U for numbers] (src:mdpi-emt). Also missed, submitted 2026-07-01: arXiv 2607.00841, an FPGA emulator of silicon-photomultiplier detector signals (one time bin per clock, one-pole recursive filters, DACs at 2.5 GS/s), not a circuit solver [V, abstract] (src:arxiv-sipm). Neither is IC-level. +- AMS emulation and real-number modelling. Cadence: no 2026 announcement for the Palladium real number modeling app; its product page still lists it [S] (src:cadence-palladium-page). Synopsys: only the 2018 to 2019 DARPA AMS emulation items on ZeBu, nothing from 2026 [S] (src:synopsys-darpa). Siemens: no Veloce analog or RNM source, only the Veloce CS launch article [S] (src:siemens-veloce-cs). Real-number modelling: no new source. +- VACASK (open Verilog-A simulator, University of Ljubljana, relevant to issue #10911). Newest release 0.3.4 on 2026-09-13, then 0.3.4.rc1 on 2026-07-02, 0.3.3 on 2026-06-10, 0.3.2 on 2026-01-21; no release after 2026-10-18 [V] (src:vacask-releases). NLnet grant started 2026-03; planned work: AC stability, S-parameters, transient noise, adjoint small-signal and noise analyses, PyOPUS integration [V] (src:vacask-nlnet). A pre-release 0.3.4.dev0 binary package on PyPI is a search result only [S] (src:vacask-pypi). 0.3.4 is the version a comparison run would pin [I]. +- ngspice. Newest release 47 on 2026-08-11 (pyplot command, VDMOS soft recovery model, .wav support), before it 46 on 2026-03-29; no item after 2026-10-18 [V] (src:ngspice-news). The runs in this repository use ngspice-47; the golden deck's published RAW was made with 46 (spec:sar_adc). +- Xyce. The homepage says "Xyce 7.10 has been released" without a date; the GitHub release Release-7.10.0 is dated 2025-07-21 and no 2026 release exists [V] (src:xyce, src:xyce-gh-releases). +- OpenVAF (Reloaded fork). One release, tagged _20260610, published 2026-06-10; newest commits 2026-10-14 ("Updated readme") and 2026-10-13 ("Treat limexp as an ordinary builtin, not an analog operator"); nothing after 2026-10-18 [V] (src:openvaf-gh-releases, src:openvaf-gh-commits). +- Stanford msdsl and anasymod. The closest open prior art is dormant: the newest commit of anasymod is 2021-07-28 and of msdsl 2024-04-02 [V] (src:anasymod-gh-commits, src:msdsl-gh-commits). +- cpphdl analog. Active: five commits on 2026-10-17 and 2026-10-18 (Verilog-A export and generated model catalog, 10GBASE-R SerDes models with dual-solver regressions, a 1G PAM5 prototype with an IHP repeater flow, a README clarification at 2026-10-18 16:07 UTC), none after that [V] (src:cpphdl-gh-commits). The Verilog-A export and the 10GBASE-R path are already in section 5.4; no FPGA claim appears in what was read. +- IHP-Open-PDK. Newest commit on the IHP-GmbH default branch list is 2026-09-01 ("Dev -> Main", changelog entries since v0.3.0) [V] (src:ihp-gh-commits). Our pinned commit 21133f21 resolves to a merge dated 2026-09-08 from a fork's upstream-sync branch [V] (src:ihp-pin-commit); whether its model files equal upstream's is not checked [U]. + +Consequence for this file: none for the claims of sections 0 to 8. For the next refresh: re-read the VACASK release list, the ngspice news page and the cpphdl commit list; read the full text of the 2026 electromagnetic-transient paper if the publisher page opens.