From 02e4fa2fc9055a6c4bc99a56548548ac9c72c55c Mon Sep 17 00:00:00 2001 From: Claude Date: Mon, 19 Oct 2026 23:57:07 +0700 Subject: [PATCH] elab baseline: add systolic 0 (Closes #11099) #11094 made specs systolic generate Verilog that iverilog elaborates with 0 errors. The ratchet reads a generated module absent from the baseline as NEW and fails, even at 0: master's fpga-conformance has been red on fcb3bc5a6 with "elaboration errors: 214 (baseline 214)" and "NEW systolic: 0 errors, not in baseline". Produced by tools/check_elab_ratchet.py --update-baseline on a t27c with master's compiler.rs digest (e34e1b174c96, == FROZEN_HASH); the verify run matched CI's numbers exactly. The calibration comment stays iverilog 12.0 (CI's version): every other count is identical under 13.0. Co-Authored-By: Claude Sonnet 5.5 --- tools/elab_baseline.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/elab_baseline.txt b/tools/elab_baseline.txt index b41d601de7..860c876111 100644 --- a/tools/elab_baseline.txt +++ b/tools/elab_baseline.txt @@ -114,6 +114,7 @@ secded 0 simulator 2 spi 0 stdlib 2 +systolic 0 tern9m_l0_k_weights 8 ternary_isa 7 ternary_link 0