From 054aa73ba8a6fda34fba2cef36d76fdb2d1ef6f3 Mon Sep 17 00:00:00 2001 From: Claude Date: Tue, 20 Oct 2026 00:52:04 +0700 Subject: [PATCH 1/2] analog M3c-3: PSP103 drain and gate charge tables for ff, fs and sf, the 500 fF inverter in all five corners within 0.025 % of ngspice backward Euler The corner half of #10882 (charge tables of #10777, epic #10486). - specs/analog/decks/psp103_q_ff.cir, _fs, _sf: psp103_q_tt.cir with the title and the .lib section changed; run on ngspice-47 + OSDI + the pinned IHP-Open-PDK, the printed current tables are FF_N/FF_P, FS_N/FS_P, SF_N/SF_P byte for byte, and a re-run of the tt deck reproduces TT_QD_N .. TT_QG_P byte for byte. - specs/analog/decks/psp103_inv_be_500f_ss.cir, _ff, _fs, _sf: psp103_inv_be_500f.cir (tt) with the .lib section changed, the reference of each corner's 500 fF run (a deck per corner, outside the issue's boundary: the issue asks for ngspice backward Euler of the same corner and only tt had one). - mos_psp103_data.t27: FF_/FS_/SF_ QD_N QG_N QD_P QG_P (4 x 625 words each), SS_/FF_/FS_/SF_INV500_BE (401 samples) with their two 0.75 V crossing times, the op-point capacitances of the three corners, pins for all of them, accessors qd_n qg_n qd_p qg_p inv500_be inv500_tplh_fs inv500_tphl_fs fold_q; the tests run over all five corners. - mos_psp103.t27: q500_run / q500_ok (the board's fixed-point run of any corner against that corner's ngspice), op_gap; ff, fs, sf: tpLH 0.0207 / 0.0191 / 0.0249 % and tpHL 0.0107 / 0.0019 / 0.0079 % of ngspice (the issue asked for 1 %); the fs charge in the sf run fails the check; of the 25 pairs of corner and charge exactly the five diagonal runs pass; the tables' slopes agree with ngspice's op-point capacitances within 0.30 % in each corner. Not in this commit: the gate charge in a circuit that has a gate node (third scenario of #10882). Updates #10882 Co-Authored-By: Claude Sonnet 5.5 --- specs/analog/decks/psp103_inv_be_500f_ff.cir | 41 + specs/analog/decks/psp103_inv_be_500f_fs.cir | 41 + specs/analog/decks/psp103_inv_be_500f_sf.cir | 41 + specs/analog/decks/psp103_inv_be_500f_ss.cir | 41 + specs/analog/decks/psp103_q_ff.cir | 140 +++ specs/analog/decks/psp103_q_fs.cir | 140 +++ specs/analog/decks/psp103_q_sf.cir | 140 +++ specs/analog/mos_psp103.t27 | 441 +++++++- specs/analog/mos_psp103_data.t27 | 993 +++++++++++++++++-- 9 files changed, 1912 insertions(+), 106 deletions(-) create mode 100644 specs/analog/decks/psp103_inv_be_500f_ff.cir create mode 100644 specs/analog/decks/psp103_inv_be_500f_fs.cir create mode 100644 specs/analog/decks/psp103_inv_be_500f_sf.cir create mode 100644 specs/analog/decks/psp103_inv_be_500f_ss.cir create mode 100644 specs/analog/decks/psp103_q_ff.cir create mode 100644 specs/analog/decks/psp103_q_fs.cir create mode 100644 specs/analog/decks/psp103_q_sf.cir diff --git a/specs/analog/decks/psp103_inv_be_500f_ff.cir b/specs/analog/decks/psp103_inv_be_500f_ff.cir new file mode 100644 index 0000000000..5b16b71b68 --- /dev/null +++ b/specs/analog/decks/psp103_inv_be_500f_ff.cir @@ -0,0 +1,41 @@ +IHP SG13G2 inverter, 500 fF, backward Euler on a fixed 100 ps grid, corner mos_ff +* specs/analog/decks/psp103_inv_be_500f_ff.cir -- reference data for specs/analog/mos_psp103.t27 (M3b, #10516, epic #10486). A netlist plus +* a .control block that prints two numbers. M3c-3 (#10882): the same deck for corner mos_ff, the reference of the ff charge-table run (psp103_inv_be_500f.cir is mos_tt; _ss, _fs and _sf are the other three). +* The circuit and the run of psp103_inv_be.cir with the load at 500 fF and dt = 100 ps (dt / C = 200 V/A again, so the table model runs the +* same 400 steps, bit for bit; only the circuit is 20 times faster). The device capacitances of PSP103 (gate-drain overlap and channel, +* drain junctions: a few fF to some ten fF at W = 1 um and 3 um), which the table model does not have, are now a few percent of the load. +* Paths are NOT in this file: ngspice reads IHP_PDK and IHP_OSDI from the environment (see psp103_tab_tt.cir). +* Run: IHP_PDK= IHP_OSDI= ngspice -b psp103_inv_be_500f_ff.cir (ngspice-47) +* Grid: tstep = 0.78125 dt makes the opening ramp end exactly at dt = 100 ps, so every internal point from then on is a multiple of dt. The +* input is a B source of nint(time / dt): Vdd up to index 1, 0 V from index 2 (150 ps) to index 201, Vdd from index 202. Step k of the spec ends +* at (k + 2) dt; step 0 starts at t = dt = 100 ps and step 200 at 201 dt = 20.1 ns. +* What it prints (ngspice .meas, 6 digits, in s): tplh and tphl, the times at which the output crosses 0.75 V rising (after step 0's edge) and +* falling (after step 200's edge); the delays are these minus 100 ps and minus 20.1 ns. +* M3c adds the waveform: between "BEGIN tran_be" and "END tran_be", 401 rows " TAB