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+# t27 analog emulation v0.1 -- release notes, DRAFT 2026-10-20
+
+Status: a draft for M6 (target 2026-11-16, epic #10486). Every number has its source next to it (a PR, a test or a receipt); a number without a source is not here. Nothing below is a speed claim.
+
+## What v0.1 is
+
+An analog circuit given as a SPICE netlist with IHP SG13G2 (PSP103) device models becomes `.t27` specs that are at once the software reference and the FPGA design. The specs live in `specs/analog/`, the netlist front end in `specs/tools/t27o/`, the checks run with `t27c test-report <spec>` and against ngspice-47 with the OSDI models.
+
+## Measured
+
+| piece | result | source |
+|---|---|---|
+| M0 RC low-pass on the AX7203 | 200 samples bit-exact on the board, 2.65 LSB or less against float64, 520 LUT, 0 DSP | #10276 |
+| M1 linear state-space cell | 14 of 14 tests; reproduces M0 bit for bit; RC 2.65, RLC 8.44, ladder3 9.45, ladder5 40.03 LSB against float64 | #10511 |
+| M1b the cell on the board | 573 of 573 receipt lines PASS in the 2026-10-19 regression (572 of 572 before), 1196 LUT, 1096 FF, 0 DSP, 0 BRAM, 116.06 MHz after routing; each mis-stamped control fails on its own circuit only | #10578, #11082 |
+| M1c exact zero-order hold | LC tank Q = 200 after 100 periods: amplitude ratio 1.0003 against 1.78e-7 for backward Euler | #10528, #10539 |
+| M2 netlist front end | the golden SAR deck parses and flattens (16 subcircuits, 1265 MOS, 128 `cap_cmim`); rc, rlc, lad3, lad5 give every cell word bit-exact | #10530, #10781 |
+| M3b PSP103 current tables | five corners, 25 x 25 grid; tt table against ngspice 0.56 % and 0.41 % where Id is at least 100 uA; CMOS inverter delay within 0.37 % and 0.51 % | #10778 |
+| M3c charge tables | tt and ss in PR #10893 (500 fF inverter delays within 0.020 % and 0.0041 % of ngspice); ff, fs and sf in PR #11123 (within 0.0249 % at worst); gate node of a MOS loaded by a MOS drain within 0.051 % of the supply | #10893, #11123 |
+| M3c weak inversion (tt) | a log-domain reader with an integer exp: 0.080 and 0.094 % at the 576 midpoints, 0.398 and 0.527 % at 1000 held-out points, 0.467 and 0.705 % at the cell centres; inverter delays within 0.025 % at 500 fF | #11146 |
+| M4a capacitive DAC | all 1024 codes of a half within 1.74 units of 2^-24 V of the closed form and ngspice; INL 0 | #10575 |
+| M4b comparator | decision time against ngspice within 0.53 % (square law); VACASK and ngspice-47 agree to 0.125 ps on the decision time at 14 inputs; the square-law comparator model is 97.7 times too fast on the decision against PSP103 (device charge not read) | #10604, #11133 |
+| M4c sampling switch | gate overdrive within 0.26 mV (square law) | #10779 |
+| M4d SAR logic and clock | 113 gates extracted from the golden deck; CK11 to CK1 order identical; delay cell trim settings within 4.3 % | #10845 |
+| M4e the whole converter | our ngspice-47 run of the golden deck reproduces 30 of 31 codes of the published RAW file; the behavioural converter got 0 of 31 as first merged and 30 of 31 with two fitted numbers; the converter offset is the comparator's clock-edge kick read through unequal top plates (base +9.42 mV, kick removed +0.03 mV); `sar_kick_net.t27` derives the kick from the plates' drive: scenarios S1 to S4 and the seven first-decision offsets met (offsets within 1 mV) | #10854, #10953, #11124 |
+| SAR top on the board | 549 of 549 receipt lines PASS, bit-exact with the spec, 908 LUT, 538 FF, 0 DSP, 0 BRAM, 108.27 MHz after routing; the control fails on exactly the 16 predicted conversions | #11082 |
+| M5 RAW files | ngspice reads the files the `.t27` writer produces; the converter trace as a RAW file is issue #11148 | #10909 |
+
+## What it does not claim
+
+- No speed claim: ngspice's wall time is mostly process start-up and no build time of the board design is measured against it.
+- The two board tops are behavioural: they do not read the PSP103 tables, so the FPGA size of a PSP103 solver is not measured.
+- M4e is not predicted end to end: scenario S5 (the late decisions of the converter) is not met, three of four late-decision offsets are within 0.2 mV and one misses by 0.29 mV (#11124).
+- Weak inversion is met for the tt corner only; the other four corners have the 25 x 25 current tables of M3b and no log tables.
+- The comparator and the switch of the whole converter are not yet at PSP103 level inside the converter loop.
+- The full demo of the external team's VACASK example does not run on the VACASK obtained; only the comparator and the DAC were compared (#11133).
+- The external team's per-block self-checking checks are not applied yet; nothing here says the converter passes them.
+- This is a SAR ADC and its blocks, not a full mixed-signal chip.
+
+## Reproduce
+
+`t27c test-report specs/analog/<spec>.t27` for a spec's tests (vacuous passes must be 0); the decks under `specs/analog/decks/` run with ngspice-47 and the IHP-Open-PDK at the commit named in each table; the board receipts are in `docs/analog/board-regression-2026-10-19.md`. The night report of 2026-10-19 (`docs/analog/night-report-2026-10-19.md`) has the sources of each number.