From 61361a1d54556fe379d5305f1d1ffecb2e994e7a Mon Sep 17 00:00:00 2001 From: Ray Morris Date: Tue, 8 Sep 2026 00:02:12 -0500 Subject: [PATCH 1/2] Remove FURYF4OSD PB10/PB11 outputs that duplicate S4_OUT/S1_OUT PB10 was declared TIM2_CH3 and PB11 TIM2_CH4, the same compare registers already driving S4_OUT (PA2) and S1_OUT (PA3). Two pins on one compare register can only emit the same waveform, so neither pad could ever be an independent output for any protocol, and at motorCount >= 5 the extra entries fight S1/S4 for their CCRs. Per the STM32F405 datasheet AF table PB10's only timer function is TIM2_CH3 and PB11's only timer function is TIM2_CH4, so there is no free channel to remap them to; both pads are also this board's UART3 TX/RX. MAX_PWM_OUTPUT_PORTS drops to the 4 outputs that remain. --- src/main/target/FURYF4OSD/target.c | 4 ++-- src/main/target/FURYF4OSD/target.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/target/FURYF4OSD/target.c b/src/main/target/FURYF4OSD/target.c index ef414db35e4..5ffb74dab73 100644 --- a/src/main/target/FURYF4OSD/target.c +++ b/src/main/target/FURYF4OSD/target.c @@ -28,8 +28,8 @@ timerHardware_t timerHardware[] = { DEF_TIM(TIM3, CH3, PB0, TIM_USE_OUTPUT_AUTO, 0, 0 ), // S2_OUT - D(1, 7, 5) DEF_TIM(TIM3, CH4, PB1, TIM_USE_OUTPUT_AUTO, 0, 0 ), // S3_OUT - D(1, 2, 5) DEF_TIM(TIM2, CH3, PA2, TIM_USE_OUTPUT_AUTO, 0, 0 ), // S4_OUT - D(1, 1, 3) - DEF_TIM(TIM2, CH3, PB10, TIM_USE_ANY, 0, 0), - DEF_TIM(TIM2, CH4, PB11, TIM_USE_ANY, 0, 0), + // PB10/PB11 (UART3) reach only TIM2_CH3/TIM2_CH4, the compare registers already + // driving S4_OUT/S1_OUT, so they cannot carry independent outputs. DEF_TIM(TIM5, CH1, PA0, TIM_USE_LED, 0, 0 ), // LED_STRIP - DMA1_ST2_CH6 }; diff --git a/src/main/target/FURYF4OSD/target.h b/src/main/target/FURYF4OSD/target.h index 71abc9a8c68..1d6b14a65e6 100644 --- a/src/main/target/FURYF4OSD/target.h +++ b/src/main/target/FURYF4OSD/target.h @@ -169,4 +169,4 @@ #define USE_DSHOT #define USE_ESC_SENSOR -#define MAX_PWM_OUTPUT_PORTS 6 +#define MAX_PWM_OUTPUT_PORTS 4 From 4d2e5e52b1947b9adcd14eb2f75e6820e7f59932 Mon Sep 17 00:00:00 2001 From: Ray Morris Date: Tue, 8 Sep 2026 00:02:37 -0500 Subject: [PATCH 2/2] Move WARPF7 S6 to TIM8_CH3 so it stops duplicating S1 S6 (PC8) was declared TIM3_CH3, the compare register already driving S1 (PB0), so S6 could only ever mirror S1 and was never usable as its own output. PC8 also reaches TIM8_CH3, which no other output on this board uses, so S6 moves there and the documented eight outputs all work. S4 (PB11) additionally moves to the second DMA option for TIM2_CH4, DMA1 Stream6. Its default, Stream7, is the only stream TIM3_CH3 can use, so S1 claimed it first and S4 went dead at four motors. --- src/main/target/WARPF7/target.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/target/WARPF7/target.c b/src/main/target/WARPF7/target.c index 0d5e35b9255..b89df68343c 100644 --- a/src/main/target/WARPF7/target.c +++ b/src/main/target/WARPF7/target.c @@ -40,13 +40,13 @@ timerHardware_t timerHardware[] = { DEF_TIM(TIM2, CH3, PB10, TIM_USE_OUTPUT_AUTO, 0, 0), // S3 - DEF_TIM(TIM2, CH4, PB11, TIM_USE_OUTPUT_AUTO, 0, 0), // S4 + DEF_TIM(TIM2, CH4, PB11, TIM_USE_OUTPUT_AUTO, 0, 1), // S4 -- dmavar 1: DMA1 Stream6, S1's TIM3_CH3 has only DMA1 Stream7 // DEF_TIM(TIM3, CH4, PC9, TIM_USE_OUTPUT_AUTO, 0, 0), // S5 DEF_TIM(TIM8, CH4, PC9, TIM_USE_OUTPUT_AUTO, 0, 0), - DEF_TIM(TIM3, CH3, PC8, TIM_USE_OUTPUT_AUTO, 0, 0), // S6 - //DEF_TIM(TIM8, CH3, PC8, TIM_USE_OUTPUT_AUTO, 0, 0), + // DEF_TIM(TIM3, CH3, PC8, TIM_USE_OUTPUT_AUTO, 0, 0), // S6 + DEF_TIM(TIM8, CH3, PC8, TIM_USE_OUTPUT_AUTO, 0, 0), // DEF_TIM(TIM3, CH2, PC7, TIM_USE_OUTPUT_AUTO, 0, 0), // S7 DEF_TIM(TIM8, CH2, PC7, TIM_USE_OUTPUT_AUTO, 0, 0),