From 31d637fd26c1210f6ee2df2ff21f89d3103c37a3 Mon Sep 17 00:00:00 2001 From: Raphael Hunziker Date: Thu, 10 Sep 2026 20:41:53 +0200 Subject: [PATCH] drivers: send the full page address on 2Gbit W25N devices w25n_performCommandWithPageAddress() sent a fixed zero byte followed by 16 bits of page address. That is correct for the 1Gbit W25N01GV, which has 1024 blocks of 64 pages and therefore 65536 pages, but not for the 2Gbit W25N02KV and MX35LF2G. Both have 2048 blocks of 64 pages, so page addresses run up to 131071 and the first address byte carries bit 16. With the upper bit dropped, page data read, program execute and block erase all addressed the lower half of the chip, so the upper half mirrored onto the lower half: erasing a block in the upper half erased the wrong block, and the data of the upper half was never reachable. Pass bits 23..16 of the page address in the first address byte. On the W25N01GV those bits are zero for every valid page address, so the instruction sequence for that device is unchanged. Found while investigating #11376 --- src/main/drivers/flash_w25n.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/main/drivers/flash_w25n.c b/src/main/drivers/flash_w25n.c index c23a1bddfbd..8d62537f005 100644 --- a/src/main/drivers/flash_w25n.c +++ b/src/main/drivers/flash_w25n.c @@ -160,7 +160,10 @@ static void w25n_performOneByteCommand(uint8_t command) static void w25n_performCommandWithPageAddress(uint8_t command, uint32_t pageAddress) { - uint8_t cmd[4] = { command, 0, (pageAddress >> 8) & 0xff, (pageAddress >> 0) & 0xff}; + // The 2Gbit devices have 2048 blocks of 64 pages, so their page address needs 17 bits. + // Its most significant bit is the lowest bit of the first address byte, which is a don't + // care on the 1Gbit W25N01GV where the page address never exceeds 16 bits. + uint8_t cmd[4] = { command, (pageAddress >> 16) & 0xff, (pageAddress >> 8) & 0xff, (pageAddress >> 0) & 0xff}; busTransfer(busDev, NULL, cmd, sizeof(cmd)); }