tWR and tRTP does not provide much of performance uplift so we could have ignored them and left them to the end, but!! lower tRTP could mean lower tRAS and here where is the performance uplift comes from that's why these timings really matters especially for micron rev E ones. Micron can do very low tRP, tRAS, tRTP, tWTRS and tWTRL compared to other types of memory chips so spending some time on lowering tWR totally worth it rather than leaving it to the end. The order should be like this:
tRP >> tWR >> tRTP >> tRAS >> tRC.
I Think the best results would be achieved with this order.
Originally posted by @IslamGhunym in #55 (comment)
tWR and tRTP does not provide much of performance uplift so we could have ignored them and left them to the end, but!! lower tRTP could mean lower tRAS and here where is the performance uplift comes from that's why these timings really matters especially for micron rev E ones. Micron can do very low tRP, tRAS, tRTP, tWTRS and tWTRL compared to other types of memory chips so spending some time on lowering tWR totally worth it rather than leaving it to the end. The order should be like this:
tRP >> tWR >> tRTP >> tRAS >> tRC.
I Think the best results would be achieved with this order.
Originally posted by @IslamGhunym in #55 (comment)