From 07d6f424dd1174e1cda984a17e4a83db64c9e4af Mon Sep 17 00:00:00 2001 From: marif-nexthop Date: Thu, 22 Oct 2026 01:44:49 +0000 Subject: [PATCH 1/6] [Nexthop][misc] Introduce the m4340nhp platform (#1828) --- .github/pr-projects.json | 1 + fboss/agent/platforms/common/tests/PlatformMappingUtilsTest.cpp | 1 + .../m4340nhp/platform_mapping/m4340nhp_platform_descriptor.csv | 2 ++ fboss/lib/if/fboss_common.thrift | 1 + 4 files changed, 5 insertions(+) create mode 100644 fboss/configs/platforms/nexthop/m4340nhp/platform_mapping/m4340nhp_platform_descriptor.csv diff --git a/.github/pr-projects.json b/.github/pr-projects.json index 2f2237419d0a8..b74ed0ad3c31f 100644 --- a/.github/pr-projects.json +++ b/.github/pr-projects.json @@ -11,6 +11,7 @@ "ladakh800bcls", "m4061nhp", "m4062nhp", + "m4340nhp", "meru800bfa", "meru800bia", "minipack", diff --git a/fboss/agent/platforms/common/tests/PlatformMappingUtilsTest.cpp b/fboss/agent/platforms/common/tests/PlatformMappingUtilsTest.cpp index 56bd1d27eb5d7..0d3e1efa7d593 100644 --- a/fboss/agent/platforms/common/tests/PlatformMappingUtilsTest.cpp +++ b/fboss/agent/platforms/common/tests/PlatformMappingUtilsTest.cpp @@ -138,6 +138,7 @@ TEST( PlatformType::PLATFORM_M4062NHP, PlatformType::PLATFORM_M4061CLSC, PlatformType::PLATFORM_M5120CSC, + PlatformType::PLATFORM_M4340NHP, futurePlatformType, }; for (const auto type : platformTypes) { diff --git a/fboss/configs/platforms/nexthop/m4340nhp/platform_mapping/m4340nhp_platform_descriptor.csv b/fboss/configs/platforms/nexthop/m4340nhp/platform_mapping/m4340nhp_platform_descriptor.csv new file mode 100644 index 0000000000000..b9ac4c549f34b --- /dev/null +++ b/fboss/configs/platforms/nexthop/m4340nhp/platform_mapping/m4340nhp_platform_descriptor.csv @@ -0,0 +1,2 @@ +System_Vendor,Platform_Type,Product_Name_Prefixes,Mode_Names,Asic_Type +nexthop,PLATFORM_M4340NHP,M4340NHP,m4340nhp,ASIC_TYPE_QUMRAN4D diff --git a/fboss/lib/if/fboss_common.thrift b/fboss/lib/if/fboss_common.thrift index a22a231072c3a..6cd8bbdfb1e00 100644 --- a/fboss/lib/if/fboss_common.thrift +++ b/fboss/lib/if/fboss_common.thrift @@ -71,6 +71,7 @@ enum PlatformType { PLATFORM_WEDGE800CNHP = 56, PLATFORM_M4061CLSC = 57, PLATFORM_M4052ACTM = 58, + PLATFORM_M4340NHP = 59, PLATFORM_UNKNOWN = 1000, # Placeholder for unknown platform type } From 3200e12079e5f54c7b6c5611d06e4350bfc8d64d Mon Sep 17 00:00:00 2001 From: Lotus Fenn Date: Sat, 24 Oct 2026 18:32:28 +0000 Subject: [PATCH 2/6] [Nexthop][m4061nhp] Introduce the m4061nhp platform (#1836) --- fboss/agent/platforms/common/tests/PlatformMappingUtilsTest.cpp | 1 + .../m4061nhp/platform_mapping/m4061nhp_platform_descriptor.csv | 2 ++ fboss/lib/if/fboss_common.thrift | 1 + 3 files changed, 4 insertions(+) create mode 100644 fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_platform_descriptor.csv diff --git a/fboss/agent/platforms/common/tests/PlatformMappingUtilsTest.cpp b/fboss/agent/platforms/common/tests/PlatformMappingUtilsTest.cpp index 0d3e1efa7d593..89022c44d5636 100644 --- a/fboss/agent/platforms/common/tests/PlatformMappingUtilsTest.cpp +++ b/fboss/agent/platforms/common/tests/PlatformMappingUtilsTest.cpp @@ -139,6 +139,7 @@ TEST( PlatformType::PLATFORM_M4061CLSC, PlatformType::PLATFORM_M5120CSC, PlatformType::PLATFORM_M4340NHP, + PlatformType::PLATFORM_M4061NHP, futurePlatformType, }; for (const auto type : platformTypes) { diff --git a/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_platform_descriptor.csv b/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_platform_descriptor.csv new file mode 100644 index 0000000000000..a18fdfa54bdfb --- /dev/null +++ b/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_platform_descriptor.csv @@ -0,0 +1,2 @@ +System_Vendor,Platform_Type,Product_Name_Prefixes,Mode_Names,Asic_Type +nexthop,PLATFORM_M4061NHP,M4061NHP,m4061nhp,ASIC_TYPE_TOMAHAWK6 diff --git a/fboss/lib/if/fboss_common.thrift b/fboss/lib/if/fboss_common.thrift index 6cd8bbdfb1e00..e4851519fb258 100644 --- a/fboss/lib/if/fboss_common.thrift +++ b/fboss/lib/if/fboss_common.thrift @@ -72,6 +72,7 @@ enum PlatformType { PLATFORM_M4061CLSC = 57, PLATFORM_M4052ACTM = 58, PLATFORM_M4340NHP = 59, + PLATFORM_M4061NHP = 60, PLATFORM_UNKNOWN = 1000, # Placeholder for unknown platform type } From e4a24b71ee857dcd2470bac80903dc5a894b4688 Mon Sep 17 00:00:00 2001 From: Lotus Fenn Date: Sun, 25 Oct 2026 05:59:42 +0000 Subject: [PATCH 3/6] [Nexthop][misc] platform_mapping_v2: Map PROFILE_1600G_8_PAM4_RS544X2N_COPPER (#1842) --- fboss/agent/Platform.cpp | 1 + fboss/agent/switch_config.thrift | 1 + fboss/agent/test/utils/PortTestUtils.cpp | 2 ++ fboss/lib/platform_mapping_v2/helpers.py | 8 +++++++- 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/fboss/agent/Platform.cpp b/fboss/agent/Platform.cpp index dd772d9f71419..6db743b820de4 100644 --- a/fboss/agent/Platform.cpp +++ b/fboss/agent/Platform.cpp @@ -275,6 +275,7 @@ int Platform::getLaneCount(cfg::PortProfileID profile) const { case cfg::PortProfileID::PROFILE_800G_8_PAM4_RS544X2N_OPTICAL: case cfg::PortProfileID::PROFILE_800G_8_PAM4_RS544X2N_COPPER: case cfg::PortProfileID::PROFILE_1600G_8_PAM4_RS544X2N_OPTICAL: + case cfg::PortProfileID::PROFILE_1600G_8_PAM4_RS544X2N_COPPER: return 8; case cfg::PortProfileID::PROFILE_DEFAULT: diff --git a/fboss/agent/switch_config.thrift b/fboss/agent/switch_config.thrift index 020774e49c8df..9c803da6c3b73 100644 --- a/fboss/agent/switch_config.thrift +++ b/fboss/agent/switch_config.thrift @@ -199,6 +199,7 @@ enum PortProfileID { PROFILE_1600G_8_PAM4_RS544X2N_OPTICAL = 63, PROFILE_212POINT5G_1_PAM4_RS544X2N_OPTICAL = 64, PROFILE_212POINT5G_1_PAM4_RS544X2N_COPPER = 65, + PROFILE_1600G_8_PAM4_RS544X2N_COPPER = 66, } enum Scope { diff --git a/fboss/agent/test/utils/PortTestUtils.cpp b/fboss/agent/test/utils/PortTestUtils.cpp index 61d9005cf8e38..405d9bb429815 100644 --- a/fboss/agent/test/utils/PortTestUtils.cpp +++ b/fboss/agent/test/utils/PortTestUtils.cpp @@ -110,6 +110,7 @@ cfg::PortSpeed getSpeed(cfg::PortProfileID profile) { return cfg::PortSpeed::EIGHTHUNDREDG; case cfg::PortProfileID::PROFILE_1600G_8_PAM4_RS544X2N_OPTICAL: + case cfg::PortProfileID::PROFILE_1600G_8_PAM4_RS544X2N_COPPER: return cfg::PortSpeed::ONEPOINTSIXT; case cfg::PortProfileID::PROFILE_DEFAULT: @@ -151,6 +152,7 @@ TransmitterTechnology getMediaType(cfg::PortProfileID profile) { case cfg::PortProfileID::PROFILE_400G_2_PAM4_RS544X2N_COPPER: case cfg::PortProfileID::PROFILE_800G_4_PAM4_RS544X2N_COPPER: case cfg::PortProfileID::PROFILE_212POINT5G_1_PAM4_RS544X2N_COPPER: + case cfg::PortProfileID::PROFILE_1600G_8_PAM4_RS544X2N_COPPER: return TransmitterTechnology::COPPER; case cfg::PortProfileID::PROFILE_10G_1_NRZ_NOFEC_OPTICAL: diff --git a/fboss/lib/platform_mapping_v2/helpers.py b/fboss/lib/platform_mapping_v2/helpers.py index c8bb9cd856207..c01399c0f1cba 100644 --- a/fboss/lib/platform_mapping_v2/helpers.py +++ b/fboss/lib/platform_mapping_v2/helpers.py @@ -90,7 +90,10 @@ def profile_to_port_speed(profile: PortProfileID) -> List[PortSpeed]: PortProfileID.PROFILE_800G_4_PAM4_RS544X2N_COPPER, ]: return [PortSpeed.EIGHTHUNDREDG] - if profile in [PortProfileID.PROFILE_1600G_8_PAM4_RS544X2N_OPTICAL]: + if profile in [ + PortProfileID.PROFILE_1600G_8_PAM4_RS544X2N_OPTICAL, + PortProfileID.PROFILE_1600G_8_PAM4_RS544X2N_COPPER, + ]: return [PortSpeed.ONEPOINTSIXT] if profile in [ PortProfileID.PROFILE_10G_1_NRZ_NOFEC_COPPER, @@ -168,6 +171,7 @@ def num_lanes_from_profile(profile: PortProfileID) -> int: PortProfileID.PROFILE_800G_8_PAM4_RS544X2N_OPTICAL, PortProfileID.PROFILE_800G_8_PAM4_RS544X2N_COPPER, PortProfileID.PROFILE_1600G_8_PAM4_RS544X2N_OPTICAL, + PortProfileID.PROFILE_1600G_8_PAM4_RS544X2N_COPPER, ]: return 8 if profile in [PortProfileID.PROFILE_DEFAULT]: @@ -1078,6 +1082,7 @@ def transmitter_tech_from_profile( PortProfileID.PROFILE_400G_8_PAM4_RS544X2N_COPPER, PortProfileID.PROFILE_100G_1_PAM4_NOFEC_COPPER, PortProfileID.PROFILE_800G_8_PAM4_RS544X2N_COPPER, + PortProfileID.PROFILE_1600G_8_PAM4_RS544X2N_COPPER, ]: return [TransmitterTechnology.COPPER] if profile in [ @@ -1177,6 +1182,7 @@ def fec_from_profile(profile: PortProfileID) -> FecMode: PortProfileID.PROFILE_800G_4_PAM4_RS544X2N_COPPER, PortProfileID.PROFILE_800G_4_PAM4_RS544X2N_OPTICAL, PortProfileID.PROFILE_1600G_8_PAM4_RS544X2N_OPTICAL, + PortProfileID.PROFILE_1600G_8_PAM4_RS544X2N_COPPER, ]: return FecMode.RS544_2N # RS545 profiles From dbad1f641a7262d3d32e08e569340a200f308a3c Mon Sep 17 00:00:00 2001 From: Lotus Fenn Date: Sat, 24 Oct 2026 21:01:43 +0000 Subject: [PATCH 4/6] [Nexthop][m4061nhp] Add the platform mapping (#1837) --- fboss/agent/hw/test/ProdConfigFactory.cpp | 2 + .../generated/platform_descriptor.json | 11 + .../generated/platform_mapping.json | 176175 +++++++++++++++ .../m4061nhp_port_profile_mapping.csv | 514 + .../m4061nhp_profile_settings.csv | 17 + .../platform_mapping/m4061nhp_si_settings.csv | 513 + .../m4061nhp_static_mapping.csv | 517 + .../m4061nhp_vendor_config.json | 20 + fboss/lib/platform_mapping_v2/gen.py | 1 + 9 files changed, 177770 insertions(+) create mode 100644 fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/generated/platform_descriptor.json create mode 100644 fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/generated/platform_mapping.json create mode 100644 fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_port_profile_mapping.csv create mode 100644 fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_profile_settings.csv create mode 100644 fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_si_settings.csv create mode 100644 fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_static_mapping.csv create mode 100644 fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_vendor_config.json diff --git a/fboss/agent/hw/test/ProdConfigFactory.cpp b/fboss/agent/hw/test/ProdConfigFactory.cpp index 489f46066c9c8..0aff35bb4ebcf 100644 --- a/fboss/agent/hw/test/ProdConfigFactory.cpp +++ b/fboss/agent/hw/test/ProdConfigFactory.cpp @@ -166,6 +166,7 @@ uint16_t uplinksCountFromSwitch(PlatformType mode) { case PM::PLATFORM_ICECUBE800BC: case PM::PLATFORM_ICETEA800BC: case PM::PLATFORM_MONTBLANC: + case PM::PLATFORM_M4061NHP: case PM::PLATFORM_M4062NHP: case PM::PLATFORM_M5120CSC: return 4; @@ -195,6 +196,7 @@ cfg::PortSpeed getPortSpeed(PlatformType platformType) { portSpeed = cfg::PortSpeed::TWOHUNDREDG; break; case PlatformType::PLATFORM_MONTBLANC: + case PlatformType::PLATFORM_M4061NHP: portSpeed = cfg::PortSpeed::FOURHUNDREDG; break; case PlatformType::PLATFORM_MINIPACK3N: diff --git a/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/generated/platform_descriptor.json b/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/generated/platform_descriptor.json new file mode 100644 index 0000000000000..a9e702eda1878 --- /dev/null +++ b/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/generated/platform_descriptor.json @@ -0,0 +1,11 @@ +{ + "platformType": 60, + "productNamePrefixes": [ + "M4061NHP" + ], + "modeNames": [ + "m4061nhp" + ], + "asicType": 18, + "numSwitchAsics": 1 +} diff --git a/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/generated/platform_mapping.json b/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/generated/platform_mapping.json new file mode 100644 index 0000000000000..794a4ed181f7a --- /dev/null +++ b/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/generated/platform_mapping.json @@ -0,0 +1,176175 @@ +{ + "ports": { + "1": { + "mapping": { + "id": 1, + "name": "eth1/4/1", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 0 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 0 + } + } + }, + { + "a": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 1 + } + } + }, + { + "a": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 2 + } + } + }, + { + "a": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 3 + } + } + }, + { + "a": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 4 + } + } + }, + { + "a": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 5 + } + } + }, + { + "a": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 6 + } + } + }, + { + "a": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "23": { + "subsumedPorts": [ + 2, + 3, + 4 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 0 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 1 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 2 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 3 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 1 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 3 + } + } + ] + } + }, + "25": { + "subsumedPorts": [ + 2, + 3, + 4 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 0 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 1 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 2 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 3 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 1 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 3 + } + } + ] + } + }, + "38": { + "subsumedPorts": [ + 2, + 3, + 4 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 0 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 1 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 2 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 3 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 1 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 3 + } + } + ] + } + }, + "39": { + "subsumedPorts": [ + 2, + 3, + 4, + 5, + 6, + 7, + 8 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 0 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 1 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 2 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 3 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 4 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 5 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 6 + } + }, + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 1 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 3 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 4 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 5 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 6 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 7 + } + } + ] + } + }, + "45": { + "subsumedPorts": [ + 2, + 3, + 4 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-TH6_NIF-slot1/chip1/core1", + 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+552,552,eth1/61/5,23-25-38-45-47-51-52-53-57-58-59,,,,0,0 +553,553,eth1/61/6,47-53-59,,,,0,0 +554,554,eth1/61/7,47-51-53-58-59,,,,0,0 +555,555,eth1/61/8,47-53-59,,,,0,0 +540,540,eth1/62/1,23-25-38-39-45-47-50-51-52-53-57-58-59-63-66,,,,0,0 +541,541,eth1/62/2,47-53-59,,,,0,0 +542,542,eth1/62/3,47-51-53-58-59,,,,0,0 +543,543,eth1/62/4,47-53-59,,,,0,0 +544,544,eth1/62/5,23-25-38-45-47-51-52-53-57-58-59,,,,0,0 +545,545,eth1/62/6,47-53-59,,,,0,0 +546,546,eth1/62/7,47-51-53-58-59,,,,0,0 +547,547,eth1/62/8,47-53-59,,,,0,0 +268,268,eth1/65/1,22-23,,,,4,0 diff --git a/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_profile_settings.csv b/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_profile_settings.csv new file mode 100644 index 0000000000000..d9d753dedcbfe --- /dev/null +++ b/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_profile_settings.csv @@ -0,0 +1,17 @@ +Port_Speed(mbps),A_CHIP_TYPE,Z_CHIP_TYPE,NUM_LANES,Modulation,A_FEC,Z_FEC,MEDIA_TYPE,A_Interface_Type,Z_Interface_Type +1600000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,,OPTICAL,KR8, +1600000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,,COPPER,CR8, +800000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,,OPTICAL,KR8, +800000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,,COPPER,CR8, +800000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,,OPTICAL,KR4, +800000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,,COPPER,CR4, +400000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,,OPTICAL,KR4, +400000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,,COPPER,CR4, +400000,NPU,TRANSCEIVER,2,PAM4,RS544_2N,,OPTICAL,KR2, +400000,NPU,TRANSCEIVER,2,PAM4,RS544_2N,,COPPER,CR2, +200000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,,OPTICAL,KR4, +200000,NPU,TRANSCEIVER,1,PAM4,RS544_2N,,OPTICAL,KR, +200000,NPU,TRANSCEIVER,1,PAM4,RS544_2N,,COPPER,CR, +100000,NPU,TRANSCEIVER,1,PAM4,RS544,,OPTICAL,SR, +100000,NPU,TRANSCEIVER,4,NRZ,RS528,,OPTICAL,SR4, +100000,NPU,TRANSCEIVER,4,NRZ,RS528,,COPPER,CR4, diff --git a/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_si_settings.csv b/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_si_settings.csv new file mode 100644 index 0000000000000..a78043acf3d3e --- /dev/null +++ b/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_si_settings.csv @@ -0,0 +1,513 @@ +SLOT_ID,CHIP_ID,CHIP_TYPE,CORE_ID,CORE_TYPE,CORE_LANE,LANE_SPEED(mbps),MEDIA_TYPE,OPTICS_VENDOR,NIC_VENDOR,CABLE_LENGTH(m),TX_PRE3,TX_PRE2,TX_PRE1,TX_MAIN,TX_POST1,TX_POST2,TX_POST3,RX_CTLE_CODE,RX_DSP_MODE,RX_AFE_TRIM,TCVR_VENDOR,TX_PRECODING,RX_PRECODING,RX_REACH +1,1,NPU,0,TH6_NIF,0,200000,OPTICAL,,,,0,0,-40,130,0,0,0,,,,,1,1,1 +1,1,NPU,0,TH6_NIF,1,200000,OPTICAL,,,,0,0,-40,130,0,0,0,,,,,1,1,1 +1,1,NPU,0,TH6_NIF,2,200000,OPTICAL,,,,0,0,-40,130,0,0,0,,,,,1,1,1 +1,1,NPU,0,TH6_NIF,3,200000,OPTICAL,,,,0,0,-40,130,0,0,0,,,,,1,1,1 +1,1,NPU,0,TH6_NIF,4,200000,OPTICAL,,,,0,0,-40,130,0,0,0,,,,,1,1,1 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a/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_vendor_config.json b/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_vendor_config.json new file mode 100644 index 0000000000000..6e9cc73cf1b0d --- /dev/null +++ b/fboss/configs/platforms/nexthop/m4061nhp/platform_mapping/m4061nhp_vendor_config.json @@ -0,0 +1,20 @@ +{ + "config" : { + "common_config" : { + + }, + "prod_config_only" : { + + }, + "hw_test_config_only" : { + }, + "link_test_config_only" : { + }, + "benchmark_config_only" : { + + }, + "port_map_config" : { + + } + } +} diff --git a/fboss/lib/platform_mapping_v2/gen.py b/fboss/lib/platform_mapping_v2/gen.py index 4042d4b0e40c3..220a57f9f036b 100644 --- a/fboss/lib/platform_mapping_v2/gen.py +++ b/fboss/lib/platform_mapping_v2/gen.py @@ -86,6 +86,7 @@ def resolve(path: str) -> str: "wedge800bact", "m4052actm", "m4062nhp", + "m4061nhp", "m4061clsc", "m5120csc", "wedge800bnhp", From 741d9e54cabcc689d7bca0afe424ebcd29163e36 Mon Sep 17 00:00:00 2001 From: marif-nexthop Date: Fri, 2 Oct 2026 18:58:12 +0000 Subject: [PATCH 5/6] [Nexthop][feature] "asic_config_v3" - Support multiple management ports (#1714) --- .../asic_config_v3/schema_field_reference.md | 6 +- .../broadcom/xgs/asics/tomahawk5.json | 16 +-- .../broadcom/xgs/asics/tomahawk6.json | 16 +-- .../asic_config/asic_config.json | 10 +- .../icecube800bc/asic_config/asic_config.json | 10 +- .../icetea800bc/asic_config/asic_config.json | 10 +- .../asic_config/asic_config.json | 10 +- .../tahansb800bc/asic_config/asic_config.json | 10 +- .../generators/broadcom_xgs_generator.py | 108 ++++++++++++------ .../broadcom_xgs_asic_config.schema.json | 60 ++++++---- .../schemas/platform_config.schema.json | 30 ++--- 11 files changed, 174 insertions(+), 112 deletions(-) diff --git a/docs/docs/developing/asic_config_v3/schema_field_reference.md b/docs/docs/developing/asic_config_v3/schema_field_reference.md index 12c6e7ece9e72..bb3df04fac69e 100644 --- a/docs/docs/developing/asic_config_v3/schema_field_reference.md +++ b/docs/docs/developing/asic_config_v3/schema_field_reference.md @@ -54,8 +54,8 @@ following fields. | `port_config` | XGS. Front-panel port settings: `default_speed` (in Mbps), `speed_to_fec` (mapping from speed to FEC mode), `enable` (the value emitted for `PC_PORT.ENABLE`), and `pc_port_overrides` (extra `PC_PORT` key/value lines emitted verbatim, for example `LINK_TRAINING`). This object is distinct from the DNX `port_config` string inside `asic_config_params`. | | `cpu_port` | XGS. CPU port settings: `speed` (in Mbps) and `num_lanes`. | | `mgmt_port` | XGS. Management port settings: `enabled` (whether the port is emitted at all), `enable` (the `PC_PORT.ENABLE` value), `in_port_block` (include the port in the `PORT` MTU range), and `speed_variants` (per-speed settings keyed by speed). | -| `mgmt_port_overrides` | XGS. Platform overrides of the ASIC-level management port defaults: `logical_id`, `physical_id`, `speed`, `num_lanes`, and `fec`. | -| `port_mapping_overrides` | XGS. Adjustments to the logical-to-physical port mapping formula: `core_range` (which cores participate, for example `"0-15,48-63"`), `num_lp_ports_on_even_core`, `num_logical_ports_per_datapath`, `lp_start_step_offset`, `lp_offset_simple`, `special_core_offset_apply_all`, and `exclude_logical_ports` (logical port IDs omitted from `PC_PORT_PHYS_MAP`, `PC_PORT`, and `PORT`, for front-panel ports that are not populated on the platform). | +| `mgmt_port_overrides` | XGS. List of platform overrides of the ASIC-level management port defaults (`logical_id`, `physical_id`, `speed`, `num_lanes`, and `fec`), overriding the port at the same index. Entries beyond the defaults list declare additional ports and must be complete. Duplicate logical or physical port identifiers are rejected. | +| `port_mapping_overrides` | XGS. Adjustments to the logical-to-physical port mapping formula: `core_range` (which cores participate, for example `"0-15,48-63"`), `num_lp_ports_on_even_core`, `num_logical_ports_per_datapath`, `lp_start_step_offset`, `lp_offset_simple`, and `exclude_logical_ports` (logical port IDs omitted from `PC_PORT_PHYS_MAP`, `PC_PORT`, and `PORT`, for front-panel ports that are not populated on the platform). | | `platform_sai_overrides` | XGS. Platform-level SAI settings. These take precedence within the layered `global` sources and override the ASIC-level SAI overrides. | | `platform_sdk_overrides` | DNX. Platform-level SOC properties applied on top of the ASIC `base_sdk_settings` and declarative tables. Keys carry their SOC suffix inline. | | `device_config_overrides` | XGS. Key/value pairs written to the `DEVICE_CONFIG` output table, for example clock frequencies. | @@ -101,7 +101,7 @@ files under `fboss/configs/asic_vendors/broadcom/xgs/asics/`. | `port_architecture` | Core, lane, and datapath layout consumed by the port mapping logic: `num_cores`, `num_lanes_per_core`, `num_logical_ports_per_datapath`, `num_physical_ports_per_datapath`, and `num_lp_ports_on_even_core_default`. | | `mmu_size` | MMU buffer size in bytes. Also used as the `MAX_FRAME_SIZE` and port MTU values. | | `table_names` | Ordered list of output YAML table names. Controls which tables appear in the output and their order. | -| `mgmt_port_defaults` | Default management port settings: `logical_id`, `physical_id`, `speed`, `num_lanes`, and `fec`. Platforms may override these per variant. | +| `mgmt_port_defaults` | List of default management port settings, one entry per port: `logical_id`, `physical_id`, `speed`, `num_lanes`, and `fec`. Platforms may override these per variant. | | `preamble_support` | Whether the ASIC supports a preamble section prepended to the output YAML. When `false`, any `preamble_file` declared by a platform is ignored. | | `global_defaults` | ASIC-specific SDK settings copied into the `global` output table. | | `sai_overrides` | ASIC-specific SAI settings layered on top of the vendor SAI common values. | diff --git a/fboss/configs/asic_vendors/broadcom/xgs/asics/tomahawk5.json b/fboss/configs/asic_vendors/broadcom/xgs/asics/tomahawk5.json index e3d9b0b332353..7cb2a4c9ba684 100644 --- a/fboss/configs/asic_vendors/broadcom/xgs/asics/tomahawk5.json +++ b/fboss/configs/asic_vendors/broadcom/xgs/asics/tomahawk5.json @@ -26,13 +26,15 @@ "PC_PMD_FIRMWARE", "DLB_ECMP_CONFIG" ], - "mgmt_port_defaults": { - "logical_id": 76, - "physical_id": 513, - "speed": 100000, - "num_lanes": 4, - "fec": "PC_FEC_RS528" - }, + "mgmt_port_defaults": [ + { + "logical_id": 76, + "physical_id": 513, + "speed": 100000, + "num_lanes": 4, + "fec": "PC_FEC_RS528" + } + ], "preamble_support": true, "global_defaults": { diff --git a/fboss/configs/asic_vendors/broadcom/xgs/asics/tomahawk6.json b/fboss/configs/asic_vendors/broadcom/xgs/asics/tomahawk6.json index 7599f3853f31c..f66b2338557cd 100644 --- a/fboss/configs/asic_vendors/broadcom/xgs/asics/tomahawk6.json +++ b/fboss/configs/asic_vendors/broadcom/xgs/asics/tomahawk6.json @@ -26,13 +26,15 @@ "DLB_ECMP_CONFIG", "PHB_CONTROL" ], - "mgmt_port_defaults": { - "logical_id": 76, - "physical_id": 513, - "speed": 100000, - "num_lanes": 4, - "fec": "PC_FEC_RS528" - }, + "mgmt_port_defaults": [ + { + "logical_id": 76, + "physical_id": 513, + "speed": 100000, + "num_lanes": 4, + "fec": "PC_FEC_RS528" + } + ], "preamble_support": false, "global_defaults": { diff --git a/fboss/configs/platforms/arista/icecube800banw/asic_config/asic_config.json b/fboss/configs/platforms/arista/icecube800banw/asic_config/asic_config.json index 7214ade0d0230..2bc346ea2fd20 100644 --- a/fboss/configs/platforms/arista/icecube800banw/asic_config/asic_config.json +++ b/fboss/configs/platforms/arista/icecube800banw/asic_config/asic_config.json @@ -28,10 +28,12 @@ "enabled": true, "enable": 1 }, - "mgmt_port_overrides": { - "logical_id": 268, - "physical_id": 514 - }, + "mgmt_port_overrides": [ + { + "logical_id": 268, + "physical_id": 514 + } + ], "port_mapping_overrides": { "num_logical_ports_per_datapath": 16, "lp_start_step_offset": 2, diff --git a/fboss/configs/platforms/celestica/icecube800bc/asic_config/asic_config.json b/fboss/configs/platforms/celestica/icecube800bc/asic_config/asic_config.json index 4bf1394322c19..1a9788bfe288a 100644 --- a/fboss/configs/platforms/celestica/icecube800bc/asic_config/asic_config.json +++ b/fboss/configs/platforms/celestica/icecube800bc/asic_config/asic_config.json @@ -34,10 +34,12 @@ } } }, - "mgmt_port_overrides": { - "logical_id": 268, - "physical_id": 514 - }, + "mgmt_port_overrides": [ + { + "logical_id": 268, + "physical_id": 514 + } + ], "port_mapping_overrides": { "num_logical_ports_per_datapath": 18, "lp_start_step_offset": 0, diff --git a/fboss/configs/platforms/celestica/icetea800bc/asic_config/asic_config.json b/fboss/configs/platforms/celestica/icetea800bc/asic_config/asic_config.json index aabd1fe101d7a..aa247b7280cff 100644 --- a/fboss/configs/platforms/celestica/icetea800bc/asic_config/asic_config.json +++ b/fboss/configs/platforms/celestica/icetea800bc/asic_config/asic_config.json @@ -28,10 +28,12 @@ "enabled": true, "enable": 1 }, - "mgmt_port_overrides": { - "logical_id": 268, - "physical_id": 514 - }, + "mgmt_port_overrides": [ + { + "logical_id": 268, + "physical_id": 514 + } + ], "port_mapping_overrides": { "num_logical_ports_per_datapath": 16, "lp_start_step_offset": 2, diff --git a/fboss/configs/platforms/celestica/ladakh800bcls/asic_config/asic_config.json b/fboss/configs/platforms/celestica/ladakh800bcls/asic_config/asic_config.json index aca62e97808ee..590775871685a 100644 --- a/fboss/configs/platforms/celestica/ladakh800bcls/asic_config/asic_config.json +++ b/fboss/configs/platforms/celestica/ladakh800bcls/asic_config/asic_config.json @@ -30,10 +30,12 @@ "enabled": true, "in_port_block": true }, - "mgmt_port_overrides": { - "logical_id": 268, - "physical_id": 514 - }, + "mgmt_port_overrides": [ + { + "logical_id": 268, + "physical_id": 514 + } + ], "port_mapping_overrides": { "num_logical_ports_per_datapath": 18, "lp_start_step_offset": 0, diff --git a/fboss/configs/platforms/celestica/tahansb800bc/asic_config/asic_config.json b/fboss/configs/platforms/celestica/tahansb800bc/asic_config/asic_config.json index 583aad159174f..bfafef416f5fa 100644 --- a/fboss/configs/platforms/celestica/tahansb800bc/asic_config/asic_config.json +++ b/fboss/configs/platforms/celestica/tahansb800bc/asic_config/asic_config.json @@ -26,10 +26,12 @@ "mgmt_port": { "enabled": true }, - "mgmt_port_overrides": { - "logical_id": 268, - "physical_id": 514 - }, + "mgmt_port_overrides": [ + { + "logical_id": 268, + "physical_id": 514 + } + ], "port_mapping_overrides": { "num_logical_ports_per_datapath": 18, "lp_start_step_offset": 0, diff --git a/fboss/lib/asic_config_v3/generators/broadcom_xgs_generator.py b/fboss/lib/asic_config_v3/generators/broadcom_xgs_generator.py index a821113610d3d..fd68330940811 100644 --- a/fboss/lib/asic_config_v3/generators/broadcom_xgs_generator.py +++ b/fboss/lib/asic_config_v3/generators/broadcom_xgs_generator.py @@ -5,6 +5,7 @@ from typing import Any import yaml + from fboss.lib.asic_config_v3.base_generator import BaseAsicConfigGenerator from fboss.lib.asic_config_v3.paths import AsicConfigPaths from fboss.lib.platform_mapping_v2.platform_mapping_v2 import PlatformMappingParser @@ -52,10 +53,14 @@ def __init__( self.num_ports_per_core: int = self.platform_config.get("num_ports_per_core", 2) self.mmu_size: int = self.asic_config.get("mmu_size", 9416) - # Compute lanes_per_port from ASIC port_architecture and platform num_ports_per_core + # lanes_per_port is derived from the ASIC port architecture unless the + # platform wires only a subset of chip lanes per port and overrides it + # explicitly via num_lanes_per_port. port_arch = self.asic_config.get("port_architecture", {}) num_lanes_per_core = port_arch.get("num_lanes_per_core", 8) - self.lanes_per_port: int = num_lanes_per_core // self.num_ports_per_core + self.lanes_per_port: int = self.platform_config.get( + "num_lanes_per_port", num_lanes_per_core // self.num_ports_per_core + ) @property def output_extension(self) -> str: @@ -280,6 +285,49 @@ def _get_logical_port_to_physical_port_mapping(self) -> list[list[int]]: return logical_to_physical_port_mapping + def _get_mgmt_ports(self) -> list[dict[str, Any]]: + """Return one merged settings dict per management port. + + ``mgmt_port_defaults`` and ``mgmt_port_overrides`` are lists with one + entry per port; overrides merge onto the defaults entry at the same + index. Entries beyond the defaults list must be complete, and ports + must not share logical or physical identifiers. + """ + defaults = self.asic_config.get("mgmt_port_defaults", []) + overrides = self.variant_config.get("mgmt_port_overrides", []) + + ports = [] + for i in range(max(len(defaults), len(overrides))): + port = { + **(defaults[i] if i < len(defaults) else {}), + **(overrides[i] if i < len(overrides) else {}), + } + if i >= len(defaults): + missing = { + "logical_id", + "physical_id", + "speed", + "num_lanes", + "fec", + } - port.keys() + if missing: + raise ValueError( + f"mgmt_port_overrides entry {i} declares an additional " + "management port with no mgmt_port_defaults entry to " + f"inherit from, so it must be complete; missing " + f"{sorted(missing)}" + ) + ports.append(port) + + for field in ("logical_id", "physical_id"): + ids = [port[field] for port in ports if field in port] + duplicates = sorted({v for v in ids if ids.count(v) > 1}) + if duplicates: + raise ValueError( + f"Management ports declare duplicate {field} values: {duplicates}" + ) + return ports + def _generate_logical_port_to_physical_port_mapping( self, mgmt_port: bool = False ) -> None: @@ -294,18 +342,12 @@ def _generate_logical_port_to_physical_port_mapping( pm_value = (f"PC_PHYS_PORT_ID: {lp_map[1]}",) self.values["PC_PORT_PHYS_MAP"][pm_key] = pm_value - if mgmt_port: - mgmt_defaults = self.asic_config.get("mgmt_port_defaults", {}) - mgmt_overrides = self.variant_config.get("mgmt_port_overrides", {}) - logical_id = mgmt_overrides.get( - "logical_id", mgmt_defaults.get("logical_id", 76) - ) - physical_id = mgmt_overrides.get( - "physical_id", mgmt_defaults.get("physical_id", 513) - ) - pm_key = (f"PORT_ID: {logical_id}",) - pm_value = (f"PC_PHYS_PORT_ID: {physical_id}",) - self.values["PC_PORT_PHYS_MAP"][pm_key] = pm_value + mgmt_port_config = self.variant_config.get("mgmt_port", {}) + if mgmt_port and mgmt_port_config.get("enabled", False): + for port in self._get_mgmt_ports(): + pm_key = (f"PORT_ID: {port['logical_id']}",) + pm_value = (f"PC_PHYS_PORT_ID: {port['physical_id']}",) + self.values["PC_PORT_PHYS_MAP"][pm_key] = pm_value def _generate_lane_map(self) -> None: """Generate lane map entries in PC_PM_CORE.""" @@ -346,8 +388,6 @@ def _generate_port_config(self, mgmt_port: bool = False) -> None: port_config = self.variant_config.get("port_config", {}) cpu_port_config = self.variant_config.get("cpu_port", {}) mgmt_port_config = self.variant_config.get("mgmt_port", {}) - mgmt_defaults = self.asic_config.get("mgmt_port_defaults", {}) - mgmt_overrides = self.variant_config.get("mgmt_port_overrides", {}) default_speed = port_config.get("default_speed", 400000) speed_to_fec = port_config.get("speed_to_fec", {}) @@ -383,31 +423,25 @@ def _generate_port_config(self, mgmt_port: bool = False) -> None: self.values["PC_PORT"][pc_key] = pc_value if mgmt_port and mgmt_port_config.get("enabled", False): - logical_id = mgmt_overrides.get( - "logical_id", mgmt_defaults.get("logical_id", 76) - ) - mgmt_speed = mgmt_overrides.get("speed", mgmt_defaults.get("speed", 100000)) - mgmt_num_lanes = mgmt_overrides.get( - "num_lanes", mgmt_defaults.get("num_lanes", 4) - ) - mgmt_fec = mgmt_overrides.get( - "fec", mgmt_defaults.get("fec", "PC_FEC_RS528") - ) mgmt_enable = mgmt_port_config.get("enable", 0) + for port in self._get_mgmt_ports(): + logical_id = port["logical_id"] + mgmt_port_key = (f"PORT_ID: {logical_id}",) + mgmt_port_value = ( + f"ENABLE: {mgmt_enable}", + f"SPEED: {port['speed']}", + f"NUM_LANES: {port['num_lanes']}", + f"FEC_MODE: {port['fec']}", + f"MAX_FRAME_SIZE: {self.mmu_size}", + ) + self.values["PC_PORT"][mgmt_port_key] = mgmt_port_value - mgmt_port_key = (f"PORT_ID: {logical_id}",) - mgmt_port_value = ( - f"ENABLE: {mgmt_enable}", - f"SPEED: {mgmt_speed}", - f"NUM_LANES: {mgmt_num_lanes}", - f"FEC_MODE: {mgmt_fec}", - f"MAX_FRAME_SIZE: {self.mmu_size}", - ) - self.values["PC_PORT"][mgmt_port_key] = mgmt_port_value + # Optionally include the mgmt ports in the PORT (MTU) range + # alongside FP. + if mgmt_port_config.get("in_port_block", False): + port_ranges.append(f"[{logical_id}, {logical_id}]") - # Optionally include the mgmt port in the PORT (MTU) range alongside FP. if mgmt_port_config.get("in_port_block", False): - port_ranges.append(f"[{logical_id}, {logical_id}]") port_ranges_str = ", ".join(port_ranges) pc_key = (f"PORT_ID: [{port_ranges_str}]",) diff --git a/fboss/lib/asic_config_v3/schemas/broadcom_xgs_asic_config.schema.json b/fboss/lib/asic_config_v3/schemas/broadcom_xgs_asic_config.schema.json index 0e8ef86e03a3e..6b536aaaad056 100644 --- a/fboss/lib/asic_config_v3/schemas/broadcom_xgs_asic_config.schema.json +++ b/fboss/lib/asic_config_v3/schemas/broadcom_xgs_asic_config.schema.json @@ -81,31 +81,11 @@ "minItems": 1 }, "mgmt_port_defaults": { - "type": "object", - "description": "Default settings for the management (out-of-band) port.", - "required": ["logical_id", "physical_id", "speed", "num_lanes", "fec"], - "additionalProperties": false, - "properties": { - "logical_id": { - "type": "integer", - "description": "Logical port identifier for the management port." - }, - "physical_id": { - "type": "integer", - "description": "Physical port identifier for the management port." - }, - "speed": { - "type": "integer", - "description": "Default port speed in Mbps (e.g. 100000 for 100 GbE)." - }, - "num_lanes": { - "type": "integer", - "description": "Number of physical lanes used by the management port." - }, - "fec": { - "type": "string", - "description": "Forward Error Correction (FEC) mode (e.g. \"PC_FEC_RS528\")." - } + "type": "array", + "description": "Default settings for the management (out-of-band) ports, one entry per port.", + "minItems": 1, + "items": { + "$ref": "#/$defs/mgmt_port_settings" } }, "preamble_support": { @@ -208,5 +188,35 @@ "$ref": "https://github.com/facebook/fboss/blob/main/fboss/lib/asic_config_v3/schemas/conditional_setting.schema.json#/$defs/conditional_setting" } } + }, + "$defs": { + "mgmt_port_settings": { + "type": "object", + "description": "Default settings for one management port.", + "required": ["logical_id", "physical_id", "speed", "num_lanes", "fec"], + "additionalProperties": false, + "properties": { + "logical_id": { + "type": "integer", + "description": "Logical port identifier for the management port." + }, + "physical_id": { + "type": "integer", + "description": "Physical port identifier for the management port." + }, + "speed": { + "type": "integer", + "description": "Default port speed in Mbps (e.g. 100000 for 100 GbE)." + }, + "num_lanes": { + "type": "integer", + "description": "Number of physical lanes used by the management port." + }, + "fec": { + "type": "string", + "description": "Forward Error Correction (FEC) mode (e.g. \"PC_FEC_RS528\")." + } + } + } } } diff --git a/fboss/lib/asic_config_v3/schemas/platform_config.schema.json b/fboss/lib/asic_config_v3/schemas/platform_config.schema.json index 58eb593cc9e3f..a56aae157e354 100644 --- a/fboss/lib/asic_config_v3/schemas/platform_config.schema.json +++ b/fboss/lib/asic_config_v3/schemas/platform_config.schema.json @@ -199,10 +199,6 @@ "type": "boolean", "description": "When true, computes the per-port logical-port offset as i * lanes_per_port on all cores rather than using the default even / odd conditional." }, - "core_offset_apply_all": { - "type": "boolean", - "description": "When true, applies the +1 core offset to every core rather than only cores 0 and 1. Required for platforms with a linear-stride port layout." - }, "exclude_logical_ports": { "type": "array", "items": { @@ -214,15 +210,11 @@ } }, "mgmt_port_overrides": { - "type": "object", - "description": "Optional. Per-platform overrides of the ASIC-level mgmt_port_defaults.", - "additionalProperties": false, - "properties": { - "logical_id": {"type": "integer"}, - "physical_id": {"type": "integer"}, - "speed": {"type": "integer"}, - "num_lanes": {"type": "integer"}, - "fec": {"type": "string"} + "type": "array", + "description": "Optional. Per-platform overrides of the ASIC-level mgmt_port_defaults, overriding the port at the same index. Entries beyond the defaults list declare additional ports and must be complete; the generator rejects incomplete additional entries and duplicate logical or physical port identifiers.", + "minItems": 1, + "items": { + "$ref": "#/$defs/mgmt_port_override" } }, "platform_sai_overrides": { @@ -296,6 +288,18 @@ } } }, + "mgmt_port_override": { + "type": "object", + "description": "Overrides for one management port. Fields not given keep the ASIC-level default for that port.", + "additionalProperties": false, + "properties": { + "logical_id": {"type": "integer"}, + "physical_id": {"type": "integer"}, + "speed": {"type": "integer"}, + "num_lanes": {"type": "integer"}, + "fec": {"type": "string"} + } + }, "mgmt_speed_config": { "type": "object", "description": "Per-speed management port configuration.", From 2b62bea3fbba92733a6b02d72ff753fd88aefadc Mon Sep 17 00:00:00 2001 From: Lotus Fenn Date: Sun, 25 Oct 2026 00:00:03 +0000 Subject: [PATCH 6/6] [Nexthop][m4061nhp] Add the asic_config_v3 config Add m4061nhp's asic_config_v3 input and the SDK yaml generated from it, plus the synced reference validate_asic_configs_contents compares it to. check-yaml skips synced references, as it already does generated outputs. Stacked on https://github.com/facebook/fboss/pull/1837 (platform mapping, which carries #1842, #1836 and #1828) and https://github.com/facebook/fboss/pull/1714 (multiple management ports). --- .pre-commit-config.yaml | 6 +- .../m4061nhp/asic_config/asic_config.json | 83 ++ .../asic_config/generated/default.yml | 1208 +++++++++++++++++ .../synced_asic_configs/m4061nhp.yml | 1208 +++++++++++++++++ 4 files changed, 2502 insertions(+), 3 deletions(-) create mode 100644 fboss/configs/platforms/nexthop/m4061nhp/asic_config/asic_config.json create mode 100644 fboss/configs/platforms/nexthop/m4061nhp/asic_config/generated/default.yml create mode 100644 fboss/lib/asic_config_v2/synced_asic_configs/m4061nhp.yml diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 78dd14d628411..510607b7372bc 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -25,9 +25,9 @@ repos: # asic_config generated outputs carry no trailing newline by design. exclude: ^fboss/configs/platforms/[^/]+/[^/]+/asic_config/generated/ - id: check-yaml - # asic_config generated outputs are multi-document YAML with complex - # mapping keys that PyYAML cannot load; they are generated artifacts. - exclude: ^fboss/configs/platforms/[^/]+/[^/]+/asic_config/generated/ + # asic_config generated outputs and their synced references are + # multi-document YAML with complex mapping keys that PyYAML cannot load. + exclude: ^fboss/(configs/platforms/[^/]+/[^/]+/asic_config/generated|lib/asic_config_v2/synced_asic_configs)/ - id: check-json - id: check-merge-conflict - repo: https://github.com/astral-sh/ruff-pre-commit diff --git a/fboss/configs/platforms/nexthop/m4061nhp/asic_config/asic_config.json b/fboss/configs/platforms/nexthop/m4061nhp/asic_config/asic_config.json new file mode 100644 index 0000000000000..ea59ce9823f9d --- /dev/null +++ b/fboss/configs/platforms/nexthop/m4061nhp/asic_config/asic_config.json @@ -0,0 +1,83 @@ +{ + "platform_name": "m4061nhp", + "vendor": "broadcom", + "asic": "tomahawk6", + "num_ports_per_core": 1, + "defaults": { + "asic_config_params": { + "config_type": "YAML_CONFIG", + "exact_match": false, + "mmu_lossless": false, + "config_gen_type": "DEFAULT" + }, + "port_config": { + "default_speed": 1600000, + "speed_to_fec": { + "400000": "PC_FEC_RS544_2XN", + "800000": "PC_FEC_RS544_2XN", + "1600000": "PC_FEC_RS544_2XN_IEEE" + } + }, + "cpu_port": { + "speed": 10000, + "num_lanes": 1 + }, + "mgmt_port": { + "enabled": true + }, + "mgmt_port_overrides": [ + { + "logical_id": 268, + "physical_id": 514, + "speed": 100000, + "num_lanes": 4, + "fec": "PC_FEC_RS528" + } + ], + "port_mapping_overrides": { + "num_logical_ports_per_datapath": 17 + }, + "platform_sai_overrides": { + "pktio_mode": 1, + "vlan_flooding_l2mc_num_reserved": 0, + "shared_block_mask_section": "uc_bc", + "skip_protocol_default_entries": 1, + "sai_feat_tail_timestamp": 0, + "sai_port_phy_time_sync_en": 1, + "l3_intf_vlan_split_egress": 1, + "sai_stats_disable_mask": "0x200", + "l3_alpm_large_vrf_mode": 1, + "sai_ip_counter_cstats": 1, + "default_cpu_tx_queue": 7 + }, + "conditional_settings": [ + { + "name": "m4061nhp_mmu_tables", + "condition": { + "source": "asic_config_params", + "param": "config_gen_type", + "equals": "DEFAULT" + }, + "apply": { + "TM_THD_CONFIG": { + "MIRROR_ON_DROP_RESERVATION": 0, + "SKIP_BUFFER_RESERVATION": 1 + } + }, + "skip_from_sai_common": [ + "sai_optimized_mmu", + "sai_mmu_qgroups_default" + ] + } + ], + "features": { + "generate_dlb_config": true, + "generate_dlb_ecmp_config": true, + "generate_low_clock_freq_settings": false, + "generate_autoload_board_settings": true + } + }, + "variants": { + "default": {} + } +} diff --git a/fboss/configs/platforms/nexthop/m4061nhp/asic_config/generated/default.yml b/fboss/configs/platforms/nexthop/m4061nhp/asic_config/generated/default.yml new file mode 100644 index 0000000000000..6e42a05674810 --- /dev/null +++ b/fboss/configs/platforms/nexthop/m4061nhp/asic_config/generated/default.yml @@ -0,0 +1,1208 @@ +--- +device: + 0: + PC_PM_CORE: + ? + PC_PM_ID: 1 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x07251634 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x5E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xD8 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 2 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x01237654 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x5E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xCA + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 3 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x07251634 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xA1 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x27 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 4 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x50724163 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xA4 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x1F + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 5 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x52614370 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x8E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xA5 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 6 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05163427 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xF2 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 7 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x03125467 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x45 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 8 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05163427 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x0D + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 9 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x15260437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB1 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xA5 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 10 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x13026754 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x35 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 11 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16053724 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xD8 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 12 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x51604372 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xE4 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 13 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x60517342 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xE1 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 14 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05163427 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xD2 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 15 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x03125467 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x65 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 16 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05163427 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x2D + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 17 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16053724 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x27 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 18 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x13026754 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x35 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 19 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16053724 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xD8 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 20 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x51604372 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xE4 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 21 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x52614370 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x8E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xA5 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 22 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05163427 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xD2 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 23 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x03125467 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x65 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 24 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05163427 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x2D + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 25 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x15260437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB1 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xA5 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 26 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x13026754 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xB5 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 27 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16053724 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x58 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 28 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x51604372 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xA4 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 29 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x72506341 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xF4 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xBB + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 30 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x25073416 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xF1 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x77 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 31 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x23015476 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x0E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xC0 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 32 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x25073416 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x0E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x8A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 33 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x07251634 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xF4 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xDD + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 34 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x01237654 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xF4 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xCF + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 35 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x07251634 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x0B + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x22 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 36 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x50724163 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x0E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x15 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 37 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x52614370 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB1 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x5A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 38 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05162437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xAD + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 39 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x02135467 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x1A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 40 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05162437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x52 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 41 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x15260437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x8E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x5A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 42 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x12036754 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x6A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 43 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16052734 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x87 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 44 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x51604273 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x4B + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 45 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x60517243 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x4E + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 46 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05162437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x8D + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 47 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x02135467 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x3A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 48 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05162437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x72 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 49 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16052734 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x78 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 50 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x12036754 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x6A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 51 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16052734 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x87 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 52 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x51604273 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x4B + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 53 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x52614370 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB1 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x5A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 54 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05162437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x8D + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 55 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x02135467 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x3A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 56 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05162437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x72 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 57 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x15260437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x8E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x5A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 58 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x12036754 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xEA + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 59 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16052734 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x07 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 60 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x51604273 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x0B + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 61 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x72506341 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x5E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xB1 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 62 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x25073416 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x5B + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x72 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 63 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x23015476 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xA4 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xC5 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 64 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x25073416 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xA4 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x8F + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 65 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x3120 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x1203 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x01 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x09 + TX_POLARITY_FLIP_AUTO: 0 +... +--- +device: + 0: + PC_PORT_PHYS_MAP: + ? + PORT_ID: 1 + : + PC_PHYS_PORT_ID: 1 + ? + PORT_ID: 9 + : + PC_PHYS_PORT_ID: 9 + ? + PORT_ID: 18 + : + PC_PHYS_PORT_ID: 17 + ? + PORT_ID: 26 + : + PC_PHYS_PORT_ID: 25 + ? + PORT_ID: 36 + : + PC_PHYS_PORT_ID: 33 + ? + PORT_ID: 44 + : + PC_PHYS_PORT_ID: 41 + ? + PORT_ID: 54 + : + PC_PHYS_PORT_ID: 49 + ? + PORT_ID: 62 + : + PC_PHYS_PORT_ID: 57 + ? + PORT_ID: 72 + : + PC_PHYS_PORT_ID: 65 + ? + PORT_ID: 80 + : + PC_PHYS_PORT_ID: 73 + ? + PORT_ID: 90 + : + PC_PHYS_PORT_ID: 81 + ? + PORT_ID: 98 + : + PC_PHYS_PORT_ID: 89 + ? + PORT_ID: 108 + : + PC_PHYS_PORT_ID: 97 + ? + PORT_ID: 116 + : + PC_PHYS_PORT_ID: 105 + ? + PORT_ID: 126 + : + PC_PHYS_PORT_ID: 113 + ? + PORT_ID: 134 + : + PC_PHYS_PORT_ID: 121 + ? + PORT_ID: 144 + : + PC_PHYS_PORT_ID: 129 + ? + PORT_ID: 152 + : + PC_PHYS_PORT_ID: 137 + ? + PORT_ID: 162 + : + PC_PHYS_PORT_ID: 145 + ? + PORT_ID: 170 + : + PC_PHYS_PORT_ID: 153 + ? + PORT_ID: 180 + : + PC_PHYS_PORT_ID: 161 + ? + PORT_ID: 188 + : + PC_PHYS_PORT_ID: 169 + ? + PORT_ID: 198 + : + PC_PHYS_PORT_ID: 177 + ? + PORT_ID: 206 + : + PC_PHYS_PORT_ID: 185 + ? + PORT_ID: 216 + : + PC_PHYS_PORT_ID: 193 + ? + PORT_ID: 224 + : + PC_PHYS_PORT_ID: 201 + ? + PORT_ID: 234 + : + PC_PHYS_PORT_ID: 209 + ? + PORT_ID: 242 + : + PC_PHYS_PORT_ID: 217 + ? + PORT_ID: 252 + : + PC_PHYS_PORT_ID: 225 + ? + PORT_ID: 260 + : + PC_PHYS_PORT_ID: 233 + ? + PORT_ID: 270 + : + PC_PHYS_PORT_ID: 241 + ? + PORT_ID: 278 + : + PC_PHYS_PORT_ID: 249 + ? + PORT_ID: 288 + : + PC_PHYS_PORT_ID: 257 + ? + PORT_ID: 296 + : + PC_PHYS_PORT_ID: 265 + ? + PORT_ID: 306 + : + PC_PHYS_PORT_ID: 273 + ? + PORT_ID: 314 + : + PC_PHYS_PORT_ID: 281 + ? + PORT_ID: 324 + : + PC_PHYS_PORT_ID: 289 + ? + PORT_ID: 332 + : + PC_PHYS_PORT_ID: 297 + ? + PORT_ID: 342 + : + PC_PHYS_PORT_ID: 305 + ? + PORT_ID: 350 + : + PC_PHYS_PORT_ID: 313 + ? + PORT_ID: 360 + : + PC_PHYS_PORT_ID: 321 + ? + PORT_ID: 368 + : + PC_PHYS_PORT_ID: 329 + ? + PORT_ID: 378 + : + PC_PHYS_PORT_ID: 337 + ? + PORT_ID: 386 + : + PC_PHYS_PORT_ID: 345 + ? + PORT_ID: 396 + : + PC_PHYS_PORT_ID: 353 + ? + PORT_ID: 404 + : + PC_PHYS_PORT_ID: 361 + ? + PORT_ID: 414 + : + PC_PHYS_PORT_ID: 369 + ? + PORT_ID: 422 + : + PC_PHYS_PORT_ID: 377 + ? + PORT_ID: 432 + : + PC_PHYS_PORT_ID: 385 + ? + PORT_ID: 440 + : + PC_PHYS_PORT_ID: 393 + ? + PORT_ID: 450 + : + PC_PHYS_PORT_ID: 401 + ? + PORT_ID: 458 + : + PC_PHYS_PORT_ID: 409 + ? + PORT_ID: 468 + : + PC_PHYS_PORT_ID: 417 + ? + PORT_ID: 476 + : + PC_PHYS_PORT_ID: 425 + ? + PORT_ID: 486 + : + PC_PHYS_PORT_ID: 433 + ? + PORT_ID: 494 + : + PC_PHYS_PORT_ID: 441 + ? + PORT_ID: 504 + : + PC_PHYS_PORT_ID: 449 + ? + PORT_ID: 512 + : + PC_PHYS_PORT_ID: 457 + ? + PORT_ID: 522 + : + PC_PHYS_PORT_ID: 465 + ? + PORT_ID: 530 + : + PC_PHYS_PORT_ID: 473 + ? + PORT_ID: 540 + : + PC_PHYS_PORT_ID: 481 + ? + PORT_ID: 548 + : + PC_PHYS_PORT_ID: 489 + ? + PORT_ID: 558 + : + PC_PHYS_PORT_ID: 497 + ? + PORT_ID: 566 + : + PC_PHYS_PORT_ID: 505 + ? + PORT_ID: 0 + : + PC_PHYS_PORT_ID: 0 + ? + PORT_ID: 268 + : + PC_PHYS_PORT_ID: 514 +... +--- +device: + 0: + PC_PORT: + ? + PORT_ID: 0 + : + ENABLE: 1 + SPEED: 10000 + NUM_LANES: 1 + ? + PORT_ID: [[1, 1], [9, 9], [18, 18], [26, 26], [36, 36], [44, 44], [54, 54], + [62, 62], [72, 72], [80, 80], [90, 90], [98, 98], [108, 108], [116, 116], + [126, 126], [134, 134], [144, 144], [152, 152], [162, 162], [170, 170], [180, + 180], [188, 188], [198, 198], [206, 206], [216, 216], [224, 224], [234, 234], + [242, 242], [252, 252], [260, 260], [270, 270], [278, 278], [288, 288], [296, + 296], [306, 306], [314, 314], [324, 324], [332, 332], [342, 342], [350, 350], + [360, 360], [368, 368], [378, 378], [386, 386], [396, 396], [404, 404], [414, + 414], [422, 422], [432, 432], [440, 440], [450, 450], [458, 458], [468, 468], + [476, 476], [486, 486], [494, 494], [504, 504], [512, 512], [522, 522], [530, + 530], [540, 540], [548, 548], [558, 558], [566, 566]] + : + ENABLE: 0 + SPEED: 1600000 + NUM_LANES: 8 + FEC_MODE: PC_FEC_RS544_2XN_IEEE + MAX_FRAME_SIZE: 9416 + ? + PORT_ID: 268 + : + ENABLE: 0 + SPEED: 100000 + NUM_LANES: 4 + FEC_MODE: PC_FEC_RS528 + MAX_FRAME_SIZE: 9416 +... +--- +device: + 0: + PORT_CONFIG: + PORT_SYSTEM_PROFILE_OPERMODE_PIPEUNIQUE: 1 +... +--- +bcm_device: + 0: + global: + l3_alpm_template: 1 + l3_alpm_hit_mode: 1 + ipv6_lpm_128b_enable: 1 + pktio_driver_type: 1 + qos_map_multi_get_mode: 1 + rx_cosq_mapping_management_mode: 0 + l3_iif_reservation_skip: 0 + pcie_host_intf_timeout_purge_enable: 0 + macro_flow_hash_shuffle_random_seed: 34345645 + bcm_linkscan_interval: 25000 + sai_common_hash_crc: 0x1 + sai_disable_srcmacqedstmac_ctrl: 0x1 + sai_acl_qset_optimization: 0x1 + sai_pkt_rx_custom_cfg: 1 + sai_pkt_rx_pkt_size: 16512 + sai_pkt_rx_cfg_ppc: 16 + sai_async_fdb_nbr_enable: 0x1 + sai_pfc_defaults_disable: 0x1 + sai_ifp_enable_on_cpu_tx: 0x1 + sai_vfp_smac_drop_filter_disable: 1 + sai_macro_flow_based_hash: 1 + sai_dis_ctr_incr_on_port_ln_dn: 0 + custom_feature_mesh_topology_sync_mode: 1 + sai_ecmp_group_members_increment: 1 + sai_field_group_auto_prioritize: 1 + bcm_tunnel_term_compatible_mode: 1 + sai_l2_cpu_fdb_event_suppress: 1 + sai_port_phy_time_sync_en: 1 + sai_stats_support_mask: 0x802 + sai_disable_internal_port_serdes: 1 + stat_custom_receive0_management_mode: 1 + sai_eapol_trap_use_bcast_mac: 1 + sai_stats_disable_mask: 0x200 + pktio_mode: 1 + vlan_flooding_l2mc_num_reserved: 0 + shared_block_mask_section: uc_bc + skip_protocol_default_entries: 1 + sai_feat_tail_timestamp: 0 + l3_intf_vlan_split_egress: 1 + l3_alpm_large_vrf_mode: 1 + sai_ip_counter_cstats: 1 + default_cpu_tx_queue: 7 + global_flexctr_ing_action_num_reserved: 20 + global_flexctr_ing_pool_num_reserved: 8 + global_flexctr_ing_op_profile_num_reserved: 20 + global_flexctr_ing_group_num_reserved: 2 + global_flexctr_egr_action_num_reserved: 8 + global_flexctr_egr_pool_num_reserved: 5 + global_flexctr_egr_op_profile_num_reserved: 10 + global_flexctr_egr_group_num_reserved: 1 + l3_ecmp_member_secondary_mem_size: 24576 + l3_ecmp_member_first_lkup_mem_size: 8192 + dlb_quality_adjustment_default_value_select: 1 +... +--- +device: + 0: + TM_THD_CONFIG: + THRESHOLD_MODE: LOSSY + MIRROR_ON_DROP_RESERVATION: 0 + SKIP_BUFFER_RESERVATION: 1 +... +--- +device: + 0: + PORT: + ? + PORT_ID: [[1, 1], [9, 9], [18, 18], [26, 26], [36, 36], [44, 44], [54, 54], + [62, 62], [72, 72], [80, 80], [90, 90], [98, 98], [108, 108], [116, 116], + [126, 126], [134, 134], [144, 144], [152, 152], [162, 162], [170, 170], [180, + 180], [188, 188], [198, 198], [206, 206], [216, 216], [224, 224], [234, 234], + [242, 242], [252, 252], [260, 260], [270, 270], [278, 278], [288, 288], [296, + 296], [306, 306], [314, 314], [324, 324], [332, 332], [342, 342], [350, 350], + [360, 360], [368, 368], [378, 378], [386, 386], [396, 396], [404, 404], [414, + 414], [422, 422], [432, 432], [440, 440], [450, 450], [458, 458], [468, 468], + [476, 476], [486, 486], [494, 494], [504, 504], [512, 512], [522, 522], [530, + 530], [540, 540], [548, 548], [558, 558], [566, 566]] + : + MTU: 9416 + MTU_CHECK: 1 +... +--- +device: + 0: + DEVICE_CONFIG: + AUTOLOAD_BOARD_SETTINGS: 0 +... +--- +device: + 0: + FP_CONFIG: + FP_ING_OPERMODE: GLOBAL_PIPE_AWARE +... +--- +device: + 0: + CTR_EFLEX_CONFIG: + CTR_ING_EFLEX_OPERMODE_PIPEUNIQUE: 1 + CTR_ING_EFLEX_OPERMODE_PIPE_INSTANCE_UNIQUE: 1 + CTR_EGR_EFLEX_OPERMODE_PIPEUNIQUE: 1 + CTR_EGR_EFLEX_OPERMODE_PIPE_INSTANCE_UNIQUE: 1 +... +--- +device: + 0: + DLB_ECMP_CONFIG: + PATH_QUALITY_PROFILE_MODE: WIDE +... diff --git a/fboss/lib/asic_config_v2/synced_asic_configs/m4061nhp.yml b/fboss/lib/asic_config_v2/synced_asic_configs/m4061nhp.yml new file mode 100644 index 0000000000000..6e42a05674810 --- /dev/null +++ b/fboss/lib/asic_config_v2/synced_asic_configs/m4061nhp.yml @@ -0,0 +1,1208 @@ +--- +device: + 0: + PC_PM_CORE: + ? + PC_PM_ID: 1 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x07251634 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x5E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xD8 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 2 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x01237654 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x5E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xCA + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 3 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x07251634 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xA1 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x27 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 4 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x50724163 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xA4 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x1F + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 5 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x52614370 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x8E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xA5 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 6 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05163427 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xF2 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 7 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x03125467 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x45 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 8 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05163427 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x0D + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 9 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x15260437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB1 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xA5 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 10 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x13026754 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x35 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 11 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16053724 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xD8 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 12 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x51604372 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xE4 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 13 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x60517342 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xE1 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 14 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05163427 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xD2 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 15 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x03125467 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x65 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 16 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05163427 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x2D + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 17 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16053724 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x27 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 18 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x13026754 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x35 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 19 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16053724 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xD8 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 20 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x51604372 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xE4 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 21 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x52614370 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x8E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xA5 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 22 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05163427 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xD2 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 23 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x03125467 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x65 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 24 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05163427 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x2D + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 25 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x15260437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB1 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xA5 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 26 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x13026754 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xB5 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 27 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16053724 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x58 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 28 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x51604372 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xA4 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 29 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x72506341 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xF4 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xBB + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 30 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x25073416 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xF1 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x77 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 31 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x23015476 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x0E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xC0 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 32 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x25073416 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x0E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x8A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 33 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x07251634 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xF4 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xDD + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 34 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x01237654 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xF4 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xCF + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 35 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x07251634 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x0B + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x22 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 36 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x50724163 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x0E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x15 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 37 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x52614370 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB1 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x5A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 38 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05162437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xAD + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 39 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x02135467 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x1A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 40 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05162437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x52 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 41 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x15260437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x8E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x5A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 42 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x12036754 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x6A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 43 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16052734 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x87 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 44 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x51604273 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x4B + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 45 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x07251634 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x60517243 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x4F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x4E + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 46 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05162437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x8D + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 47 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x02135467 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x3A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 48 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05162437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x72 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 49 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16052734 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x78 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 50 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x12036754 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x6A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 51 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16052734 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x87 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 52 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x51604273 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x4B + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 53 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x52614370 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB1 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x5A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 54 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05162437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1F + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x8D + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 55 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x02135467 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x3A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 56 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x25073416 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x05162437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x72 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 57 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x37042615 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x15260437 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x8E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x5A + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 58 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x12036754 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x1A + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xEA + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 59 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x16053724 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x16052734 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xE5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x07 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 60 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x05162437 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x51604273 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xB5 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x0B + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 61 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x14350627 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x72506341 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x5E + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xB1 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 62 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x25073416 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x5B + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x72 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 63 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x23015476 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xA4 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0xC5 + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 64 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x35142706 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x25073416 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0xA4 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x8F + TX_POLARITY_FLIP_AUTO: 0 + ? + PC_PM_ID: 65 + CORE_INDEX: 0 + : + RX_LANE_MAP: 0x3120 + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP: 0x1203 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP: 0x01 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP: 0x09 + TX_POLARITY_FLIP_AUTO: 0 +... +--- +device: + 0: + PC_PORT_PHYS_MAP: + ? + PORT_ID: 1 + : + PC_PHYS_PORT_ID: 1 + ? + PORT_ID: 9 + : + PC_PHYS_PORT_ID: 9 + ? + PORT_ID: 18 + : + PC_PHYS_PORT_ID: 17 + ? + PORT_ID: 26 + : + PC_PHYS_PORT_ID: 25 + ? + PORT_ID: 36 + : + PC_PHYS_PORT_ID: 33 + ? + PORT_ID: 44 + : + PC_PHYS_PORT_ID: 41 + ? + PORT_ID: 54 + : + PC_PHYS_PORT_ID: 49 + ? + PORT_ID: 62 + : + PC_PHYS_PORT_ID: 57 + ? + PORT_ID: 72 + : + PC_PHYS_PORT_ID: 65 + ? + PORT_ID: 80 + : + PC_PHYS_PORT_ID: 73 + ? + PORT_ID: 90 + : + PC_PHYS_PORT_ID: 81 + ? + PORT_ID: 98 + : + PC_PHYS_PORT_ID: 89 + ? + PORT_ID: 108 + : + PC_PHYS_PORT_ID: 97 + ? + PORT_ID: 116 + : + PC_PHYS_PORT_ID: 105 + ? + PORT_ID: 126 + : + PC_PHYS_PORT_ID: 113 + ? + PORT_ID: 134 + : + PC_PHYS_PORT_ID: 121 + ? + PORT_ID: 144 + : + PC_PHYS_PORT_ID: 129 + ? + PORT_ID: 152 + : + PC_PHYS_PORT_ID: 137 + ? + PORT_ID: 162 + : + PC_PHYS_PORT_ID: 145 + ? + PORT_ID: 170 + : + PC_PHYS_PORT_ID: 153 + ? + PORT_ID: 180 + : + PC_PHYS_PORT_ID: 161 + ? + PORT_ID: 188 + : + PC_PHYS_PORT_ID: 169 + ? + PORT_ID: 198 + : + PC_PHYS_PORT_ID: 177 + ? + PORT_ID: 206 + : + PC_PHYS_PORT_ID: 185 + ? + PORT_ID: 216 + : + PC_PHYS_PORT_ID: 193 + ? + PORT_ID: 224 + : + PC_PHYS_PORT_ID: 201 + ? + PORT_ID: 234 + : + PC_PHYS_PORT_ID: 209 + ? + PORT_ID: 242 + : + PC_PHYS_PORT_ID: 217 + ? + PORT_ID: 252 + : + PC_PHYS_PORT_ID: 225 + ? + PORT_ID: 260 + : + PC_PHYS_PORT_ID: 233 + ? + PORT_ID: 270 + : + PC_PHYS_PORT_ID: 241 + ? + PORT_ID: 278 + : + PC_PHYS_PORT_ID: 249 + ? + PORT_ID: 288 + : + PC_PHYS_PORT_ID: 257 + ? + PORT_ID: 296 + : + PC_PHYS_PORT_ID: 265 + ? + PORT_ID: 306 + : + PC_PHYS_PORT_ID: 273 + ? + PORT_ID: 314 + : + PC_PHYS_PORT_ID: 281 + ? + PORT_ID: 324 + : + PC_PHYS_PORT_ID: 289 + ? + PORT_ID: 332 + : + PC_PHYS_PORT_ID: 297 + ? + PORT_ID: 342 + : + PC_PHYS_PORT_ID: 305 + ? + PORT_ID: 350 + : + PC_PHYS_PORT_ID: 313 + ? + PORT_ID: 360 + : + PC_PHYS_PORT_ID: 321 + ? + PORT_ID: 368 + : + PC_PHYS_PORT_ID: 329 + ? + PORT_ID: 378 + : + PC_PHYS_PORT_ID: 337 + ? + PORT_ID: 386 + : + PC_PHYS_PORT_ID: 345 + ? + PORT_ID: 396 + : + PC_PHYS_PORT_ID: 353 + ? + PORT_ID: 404 + : + PC_PHYS_PORT_ID: 361 + ? + PORT_ID: 414 + : + PC_PHYS_PORT_ID: 369 + ? + PORT_ID: 422 + : + PC_PHYS_PORT_ID: 377 + ? + PORT_ID: 432 + : + PC_PHYS_PORT_ID: 385 + ? + PORT_ID: 440 + : + PC_PHYS_PORT_ID: 393 + ? + PORT_ID: 450 + : + PC_PHYS_PORT_ID: 401 + ? + PORT_ID: 458 + : + PC_PHYS_PORT_ID: 409 + ? + PORT_ID: 468 + : + PC_PHYS_PORT_ID: 417 + ? + PORT_ID: 476 + : + PC_PHYS_PORT_ID: 425 + ? + PORT_ID: 486 + : + PC_PHYS_PORT_ID: 433 + ? + PORT_ID: 494 + : + PC_PHYS_PORT_ID: 441 + ? + PORT_ID: 504 + : + PC_PHYS_PORT_ID: 449 + ? + PORT_ID: 512 + : + PC_PHYS_PORT_ID: 457 + ? + PORT_ID: 522 + : + PC_PHYS_PORT_ID: 465 + ? + PORT_ID: 530 + : + PC_PHYS_PORT_ID: 473 + ? + PORT_ID: 540 + : + PC_PHYS_PORT_ID: 481 + ? + PORT_ID: 548 + : + PC_PHYS_PORT_ID: 489 + ? + PORT_ID: 558 + : + PC_PHYS_PORT_ID: 497 + ? + PORT_ID: 566 + : + PC_PHYS_PORT_ID: 505 + ? + PORT_ID: 0 + : + PC_PHYS_PORT_ID: 0 + ? + PORT_ID: 268 + : + PC_PHYS_PORT_ID: 514 +... +--- +device: + 0: + PC_PORT: + ? + PORT_ID: 0 + : + ENABLE: 1 + SPEED: 10000 + NUM_LANES: 1 + ? + PORT_ID: [[1, 1], [9, 9], [18, 18], [26, 26], [36, 36], [44, 44], [54, 54], + [62, 62], [72, 72], [80, 80], [90, 90], [98, 98], [108, 108], [116, 116], + [126, 126], [134, 134], [144, 144], [152, 152], [162, 162], [170, 170], [180, + 180], [188, 188], [198, 198], [206, 206], [216, 216], [224, 224], [234, 234], + [242, 242], [252, 252], [260, 260], [270, 270], [278, 278], [288, 288], [296, + 296], [306, 306], [314, 314], [324, 324], [332, 332], [342, 342], [350, 350], + [360, 360], [368, 368], [378, 378], [386, 386], [396, 396], [404, 404], [414, + 414], [422, 422], [432, 432], [440, 440], [450, 450], [458, 458], [468, 468], + [476, 476], [486, 486], [494, 494], [504, 504], [512, 512], [522, 522], [530, + 530], [540, 540], [548, 548], [558, 558], [566, 566]] + : + ENABLE: 0 + SPEED: 1600000 + NUM_LANES: 8 + FEC_MODE: PC_FEC_RS544_2XN_IEEE + MAX_FRAME_SIZE: 9416 + ? + PORT_ID: 268 + : + ENABLE: 0 + SPEED: 100000 + NUM_LANES: 4 + FEC_MODE: PC_FEC_RS528 + MAX_FRAME_SIZE: 9416 +... +--- +device: + 0: + PORT_CONFIG: + PORT_SYSTEM_PROFILE_OPERMODE_PIPEUNIQUE: 1 +... +--- +bcm_device: + 0: + global: + l3_alpm_template: 1 + l3_alpm_hit_mode: 1 + ipv6_lpm_128b_enable: 1 + pktio_driver_type: 1 + qos_map_multi_get_mode: 1 + rx_cosq_mapping_management_mode: 0 + l3_iif_reservation_skip: 0 + pcie_host_intf_timeout_purge_enable: 0 + macro_flow_hash_shuffle_random_seed: 34345645 + bcm_linkscan_interval: 25000 + sai_common_hash_crc: 0x1 + sai_disable_srcmacqedstmac_ctrl: 0x1 + sai_acl_qset_optimization: 0x1 + sai_pkt_rx_custom_cfg: 1 + sai_pkt_rx_pkt_size: 16512 + sai_pkt_rx_cfg_ppc: 16 + sai_async_fdb_nbr_enable: 0x1 + sai_pfc_defaults_disable: 0x1 + sai_ifp_enable_on_cpu_tx: 0x1 + sai_vfp_smac_drop_filter_disable: 1 + sai_macro_flow_based_hash: 1 + sai_dis_ctr_incr_on_port_ln_dn: 0 + custom_feature_mesh_topology_sync_mode: 1 + sai_ecmp_group_members_increment: 1 + sai_field_group_auto_prioritize: 1 + bcm_tunnel_term_compatible_mode: 1 + sai_l2_cpu_fdb_event_suppress: 1 + sai_port_phy_time_sync_en: 1 + sai_stats_support_mask: 0x802 + sai_disable_internal_port_serdes: 1 + stat_custom_receive0_management_mode: 1 + sai_eapol_trap_use_bcast_mac: 1 + sai_stats_disable_mask: 0x200 + pktio_mode: 1 + vlan_flooding_l2mc_num_reserved: 0 + shared_block_mask_section: uc_bc + skip_protocol_default_entries: 1 + sai_feat_tail_timestamp: 0 + l3_intf_vlan_split_egress: 1 + l3_alpm_large_vrf_mode: 1 + sai_ip_counter_cstats: 1 + default_cpu_tx_queue: 7 + global_flexctr_ing_action_num_reserved: 20 + global_flexctr_ing_pool_num_reserved: 8 + global_flexctr_ing_op_profile_num_reserved: 20 + global_flexctr_ing_group_num_reserved: 2 + global_flexctr_egr_action_num_reserved: 8 + global_flexctr_egr_pool_num_reserved: 5 + global_flexctr_egr_op_profile_num_reserved: 10 + global_flexctr_egr_group_num_reserved: 1 + l3_ecmp_member_secondary_mem_size: 24576 + l3_ecmp_member_first_lkup_mem_size: 8192 + dlb_quality_adjustment_default_value_select: 1 +... +--- +device: + 0: + TM_THD_CONFIG: + THRESHOLD_MODE: LOSSY + MIRROR_ON_DROP_RESERVATION: 0 + SKIP_BUFFER_RESERVATION: 1 +... +--- +device: + 0: + PORT: + ? + PORT_ID: [[1, 1], [9, 9], [18, 18], [26, 26], [36, 36], [44, 44], [54, 54], + [62, 62], [72, 72], [80, 80], [90, 90], [98, 98], [108, 108], [116, 116], + [126, 126], [134, 134], [144, 144], [152, 152], [162, 162], [170, 170], [180, + 180], [188, 188], [198, 198], [206, 206], [216, 216], [224, 224], [234, 234], + [242, 242], [252, 252], [260, 260], [270, 270], [278, 278], [288, 288], [296, + 296], [306, 306], [314, 314], [324, 324], [332, 332], [342, 342], [350, 350], + [360, 360], [368, 368], [378, 378], [386, 386], [396, 396], [404, 404], [414, + 414], [422, 422], [432, 432], [440, 440], [450, 450], [458, 458], [468, 468], + [476, 476], [486, 486], [494, 494], [504, 504], [512, 512], [522, 522], [530, + 530], [540, 540], [548, 548], [558, 558], [566, 566]] + : + MTU: 9416 + MTU_CHECK: 1 +... +--- +device: + 0: + DEVICE_CONFIG: + AUTOLOAD_BOARD_SETTINGS: 0 +... +--- +device: + 0: + FP_CONFIG: + FP_ING_OPERMODE: GLOBAL_PIPE_AWARE +... +--- +device: + 0: + CTR_EFLEX_CONFIG: + CTR_ING_EFLEX_OPERMODE_PIPEUNIQUE: 1 + CTR_ING_EFLEX_OPERMODE_PIPE_INSTANCE_UNIQUE: 1 + CTR_EGR_EFLEX_OPERMODE_PIPEUNIQUE: 1 + CTR_EGR_EFLEX_OPERMODE_PIPE_INSTANCE_UNIQUE: 1 +... +--- +device: + 0: + DLB_ECMP_CONFIG: + PATH_QUALITY_PROFILE_MODE: WIDE +...