From 082d3ee030b201cee1da18ff8d34e7af365b96b6 Mon Sep 17 00:00:00 2001 From: Yazen Ghannam Date: Sat, 18 Nov 2023 13:32:32 -0600 Subject: [PATCH 1/5] x86/mce/amd, EDAC/mce_amd: Move long names to decoder module commit ff03ff328fbd0a2b3a43e8b9bbc2a1d84265e77e upstream. The long names of the SMCA banks are only used by the MCE decoder module. Move them out of the arch code and into the decoder module. [ bp: Name the long names array "smca_long_names", drop local ptr in decode_smca_error(), constify arrays. ] Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20231118193248.1296798-5-yazen.ghannam@amd.com Signed-off-by: priyanka-mani Signed-off-by: mohanasv2 --- arch/x86/include/asm/mce.h | 1 - arch/x86/kernel/cpu/mce/amd.c | 74 ++++++++++++++--------------------- drivers/edac/mce_amd.c | 46 ++++++++++++++++++++-- 3 files changed, 72 insertions(+), 49 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 0aea4e41f9b1..06442336dea0 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -382,7 +382,6 @@ enum smca_bank_types { N_SMCA_BANK_TYPES }; -extern const char *smca_get_long_name(enum smca_bank_types t); extern bool amd_mce_is_memory_error(struct mce *m); void mce_amd_feature_init(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 4b6182e111a4..888bb1557919 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -94,42 +94,37 @@ struct smca_bank { static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks); static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts); -struct smca_bank_name { - const char *name; /* Short name for sysfs */ - const char *long_name; /* Long name for pretty-printing */ -}; - -static struct smca_bank_name smca_names[] = { - [SMCA_LS ... SMCA_LS_V2] = { "load_store", "Load Store Unit" }, - [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, - [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, - [SMCA_DE] = { "decode_unit", "Decode Unit" }, - [SMCA_RESERVED] = { "reserved", "Reserved" }, - [SMCA_EX] = { "execution_unit", "Execution Unit" }, - [SMCA_FP] = { "floating_point", "Floating Point Unit" }, - [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, - [SMCA_CS ... SMCA_CS_V2] = { "coherent_slave", "Coherent Slave" }, - [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, +static const char * const smca_names[] = { + [SMCA_LS ... SMCA_LS_V2] = "load_store", + [SMCA_IF] = "insn_fetch", + [SMCA_L2_CACHE] = "l2_cache", + [SMCA_DE] = "decode_unit", + [SMCA_RESERVED] = "reserved", + [SMCA_EX] = "execution_unit", + [SMCA_FP] = "floating_point", + [SMCA_L3_CACHE] = "l3_cache", + [SMCA_CS ... SMCA_CS_V2] = "coherent_slave", + [SMCA_PIE] = "pie", /* UMC v2 is separate because both of them can exist in a single system. */ - [SMCA_UMC] = { "umc", "Unified Memory Controller" }, - [SMCA_UMC_V2] = { "umc_v2", "Unified Memory Controller v2" }, - [SMCA_PB] = { "param_block", "Parameter Block" }, - [SMCA_PSP ... SMCA_PSP_V2] = { "psp", "Platform Security Processor" }, - [SMCA_SMU ... SMCA_SMU_V2] = { "smu", "System Management Unit" }, - [SMCA_MP5] = { "mp5", "Microprocessor 5 Unit" }, - [SMCA_MPDMA] = { "mpdma", "MPDMA Unit" }, - [SMCA_NBIO] = { "nbio", "Northbridge IO Unit" }, - [SMCA_PCIE ... SMCA_PCIE_V2] = { "pcie", "PCI Express Unit" }, - [SMCA_XGMI_PCS] = { "xgmi_pcs", "Ext Global Memory Interconnect PCS Unit" }, - [SMCA_NBIF] = { "nbif", "NBIF Unit" }, - [SMCA_SHUB] = { "shub", "System Hub Unit" }, - [SMCA_SATA] = { "sata", "SATA Unit" }, - [SMCA_USB] = { "usb", "USB Unit" }, - [SMCA_GMI_PCS] = { "gmi_pcs", "Global Memory Interconnect PCS Unit" }, - [SMCA_XGMI_PHY] = { "xgmi_phy", "Ext Global Memory Interconnect PHY Unit" }, - [SMCA_WAFL_PHY] = { "wafl_phy", "WAFL PHY Unit" }, - [SMCA_GMI_PHY] = { "gmi_phy", "Global Memory Interconnect PHY Unit" }, + [SMCA_UMC] = "umc", + [SMCA_UMC_V2] = "umc_v2", + [SMCA_PB] = "param_block", + [SMCA_PSP ... SMCA_PSP_V2] = "psp", + [SMCA_SMU ... SMCA_SMU_V2] = "smu", + [SMCA_MP5] = "mp5", + [SMCA_MPDMA] = "mpdma", + [SMCA_NBIO] = "nbio", + [SMCA_PCIE ... SMCA_PCIE_V2] = "pcie", + [SMCA_XGMI_PCS] = "xgmi_pcs", + [SMCA_NBIF] = "nbif", + [SMCA_SHUB] = "shub", + [SMCA_SATA] = "sata", + [SMCA_USB] = "usb", + [SMCA_GMI_PCS] = "gmi_pcs", + [SMCA_XGMI_PHY] = "xgmi_phy", + [SMCA_WAFL_PHY] = "wafl_phy", + [SMCA_GMI_PHY] = "gmi_phy", }; static const char *smca_get_name(enum smca_bank_types t) @@ -137,17 +132,8 @@ static const char *smca_get_name(enum smca_bank_types t) if (t >= N_SMCA_BANK_TYPES) return NULL; - return smca_names[t].name; -} - -const char *smca_get_long_name(enum smca_bank_types t) -{ - if (t >= N_SMCA_BANK_TYPES) - return NULL; - - return smca_names[t].long_name; + return smca_names[t]; } -EXPORT_SYMBOL_GPL(smca_get_long_name); enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) { diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index c20b2d127c28..e6867b1bc9c5 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1163,11 +1163,51 @@ static void decode_mc6_mce(struct mce *m) pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n"); } +static const char * const smca_long_names[] = { + [SMCA_LS ... SMCA_LS_V2] = "Load Store Unit", + [SMCA_IF] = "Instruction Fetch Unit", + [SMCA_L2_CACHE] = "L2 Cache", + [SMCA_DE] = "Decode Unit", + [SMCA_RESERVED] = "Reserved", + [SMCA_EX] = "Execution Unit", + [SMCA_FP] = "Floating Point Unit", + [SMCA_L3_CACHE] = "L3 Cache", + [SMCA_CS ... SMCA_CS_V2] = "Coherent Slave", + [SMCA_PIE] = "Power, Interrupts, etc.", + + /* UMC v2 is separate because both of them can exist in a single system. */ + [SMCA_UMC] = "Unified Memory Controller", + [SMCA_UMC_V2] = "Unified Memory Controller v2", + [SMCA_PB] = "Parameter Block", + [SMCA_PSP ... SMCA_PSP_V2] = "Platform Security Processor", + [SMCA_SMU ... SMCA_SMU_V2] = "System Management Unit", + [SMCA_MP5] = "Microprocessor 5 Unit", + [SMCA_MPDMA] = "MPDMA Unit", + [SMCA_NBIO] = "Northbridge IO Unit", + [SMCA_PCIE ... SMCA_PCIE_V2] = "PCI Express Unit", + [SMCA_XGMI_PCS] = "Ext Global Memory Interconnect PCS Unit", + [SMCA_NBIF] = "NBIF Unit", + [SMCA_SHUB] = "System Hub Unit", + [SMCA_SATA] = "SATA Unit", + [SMCA_USB] = "USB Unit", + [SMCA_GMI_PCS] = "Global Memory Interconnect PCS Unit", + [SMCA_XGMI_PHY] = "Ext Global Memory Interconnect PHY Unit", + [SMCA_WAFL_PHY] = "WAFL PHY Unit", + [SMCA_GMI_PHY] = "Global Memory Interconnect PHY Unit", +}; + +static const char *smca_get_long_name(enum smca_bank_types t) +{ + if (t >= N_SMCA_BANK_TYPES) + return NULL; + + return smca_long_names[t]; +} + /* Decode errors according to Scalable MCA specification */ static void decode_smca_error(struct mce *m) { enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); - const char *ip_name; u8 xec = XEC(m->status, xec_mask); if (bank_type >= N_SMCA_BANK_TYPES) @@ -1178,9 +1218,7 @@ static void decode_smca_error(struct mce *m) return; } - ip_name = smca_get_long_name(bank_type); - - pr_emerg(HW_ERR "%s Ext. Error Code: %d", ip_name, xec); + pr_emerg(HW_ERR "%s Ext. Error Code: %d", smca_get_long_name(bank_type), xec); /* Only print the decode of valid error codes */ if (xec < smca_mce_descs[bank_type].num_descs) From 1b2a2cb8e72488fa0bd319e65562b9ac9a54492a Mon Sep 17 00:00:00 2001 From: Muralidhara M K Date: Thu, 2 Nov 2023 11:42:23 +0000 Subject: [PATCH 2/5] x86/MCE/AMD: Add new MA_LLC, USR_DP, and USR_CP bank types commit 47b744ea5e3cf855087951a74ba9f89180fa1ba5 upstream. Add HWID and McaType values for new SMCA bank types. Signed-off-by: Muralidhara M K Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20231102114225.2006878-3-muralimk@amd.com Signed-off-by: priyanka-mani Signed-off-by: mohanasv2 --- arch/x86/include/asm/mce.h | 3 +++ arch/x86/kernel/cpu/mce/amd.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 06442336dea0..ea73d3e35491 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -360,6 +360,7 @@ enum smca_bank_types { SMCA_PIE, /* Power, Interrupts, etc. */ SMCA_UMC, /* Unified Memory Controller */ SMCA_UMC_V2, + SMCA_MA_LLC, /* Memory Attached Last Level Cache */ SMCA_PB, /* Parameter Block */ SMCA_PSP, /* Platform Security Processor */ SMCA_PSP_V2, @@ -375,6 +376,8 @@ enum smca_bank_types { SMCA_SHUB, /* System HUB Unit */ SMCA_SATA, /* SATA Unit */ SMCA_USB, /* USB Unit */ + SMCA_USR_DP, /* Ultra Short Reach Data Plane Controller */ + SMCA_USR_CP, /* Ultra Short Reach Control Plane Controller */ SMCA_GMI_PCS, /* GMI PCS Unit */ SMCA_XGMI_PHY, /* xGMI PHY Unit */ SMCA_WAFL_PHY, /* WAFL PHY Unit */ diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 888bb1557919..c80121281d3d 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -109,6 +109,7 @@ static const char * const smca_names[] = { /* UMC v2 is separate because both of them can exist in a single system. */ [SMCA_UMC] = "umc", [SMCA_UMC_V2] = "umc_v2", + [SMCA_MA_LLC] = "ma_llc", [SMCA_PB] = "param_block", [SMCA_PSP ... SMCA_PSP_V2] = "psp", [SMCA_SMU ... SMCA_SMU_V2] = "smu", @@ -121,6 +122,8 @@ static const char * const smca_names[] = { [SMCA_SHUB] = "shub", [SMCA_SATA] = "sata", [SMCA_USB] = "usb", + [SMCA_USR_DP] = "usr_dp", + [SMCA_USR_CP] = "usr_cp", [SMCA_GMI_PCS] = "gmi_pcs", [SMCA_XGMI_PHY] = "xgmi_phy", [SMCA_WAFL_PHY] = "wafl_phy", @@ -171,6 +174,7 @@ static const struct smca_hwid smca_hwid_mcatypes[] = { { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, + { SMCA_MA_LLC, HWID_MCATYPE(0x2E, 0x4) }, /* Unified Memory Controller MCA type */ { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, @@ -205,6 +209,8 @@ static const struct smca_hwid smca_hwid_mcatypes[] = { { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) }, { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) }, + { SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) }, + { SMCA_USR_CP, HWID_MCATYPE(0x180, 0x0) }, { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) }, From bf072f038a39bcb49737fcebc66aff26a9cf1691 Mon Sep 17 00:00:00 2001 From: Yazen Ghannam Date: Sat, 7 Mar 2026 11:33:14 -0500 Subject: [PATCH 3/5] x86/mce, EDAC/mce_amd: Reorder SMCA bank type enums commit bee9f4178b4a3fec70414c82ddc4bceff182f2ba upstream. Originally, the SMCA bank type enums were ordered based on processor documentation. However, the ordering became inconsistent after new bank types were added over time. Sort the bank type enums alphanumerically in most places. Sort the "enum to HWID/McaType" mapping by HWID/McaType. Drop redundant code comments. No functional changes. [ bp: Sort them alphanumerically. ] Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20260307163316.345923-2-yazen.ghannam@amd.com Signed-off-by: priyanka-mani Signed-off-by: mohanasv2 --- arch/x86/include/asm/mce.h | 51 ++++++++------- arch/x86/kernel/cpu/mce/amd.c | 115 ++++++++++++++-------------------- drivers/edac/mce_amd.c | 38 +++++------ 3 files changed, 95 insertions(+), 109 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index ea73d3e35491..fa39acb41a61 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -344,44 +344,49 @@ extern void apei_mce_report_mem_error(int corrected, */ #ifdef CONFIG_X86_MCE_AMD -/* These may be used by multiple smca_hwid_mcatypes */ +/* + * These may be used by multiple smca_hwid_mcatypes. + * + * Keep in alphanumeric order, numerals before letters. + * Exception: Keep "V2, etc." with their originals. + */ enum smca_bank_types { - SMCA_LS = 0, /* Load Store */ - SMCA_LS_V2, - SMCA_IF, /* Instruction Fetch */ - SMCA_L2_CACHE, /* L2 Cache */ + SMCA_CS, /* Coherent Slave */ + SMCA_CS_V2, SMCA_DE, /* Decoder Unit */ - SMCA_RESERVED, /* Reserved */ SMCA_EX, /* Execution Unit */ SMCA_FP, /* Floating Point */ + SMCA_GMI_PCS, /* GMI PCS Unit */ + SMCA_GMI_PHY, /* GMI PHY Unit */ + SMCA_IF, /* Instruction Fetch */ + SMCA_L2_CACHE, /* L2 Cache */ SMCA_L3_CACHE, /* L3 Cache */ - SMCA_CS, /* Coherent Slave */ - SMCA_CS_V2, - SMCA_PIE, /* Power, Interrupts, etc. */ - SMCA_UMC, /* Unified Memory Controller */ - SMCA_UMC_V2, + SMCA_LS, /* Load Store */ + SMCA_LS_V2, SMCA_MA_LLC, /* Memory Attached Last Level Cache */ - SMCA_PB, /* Parameter Block */ - SMCA_PSP, /* Platform Security Processor */ - SMCA_PSP_V2, - SMCA_SMU, /* System Management Unit */ - SMCA_SMU_V2, SMCA_MP5, /* Microprocessor 5 Unit */ SMCA_MPDMA, /* MPDMA Unit */ + SMCA_NBIF, /* NBIF Unit */ SMCA_NBIO, /* Northbridge IO Unit */ + SMCA_PB, /* Parameter Block */ SMCA_PCIE, /* PCI Express Unit */ SMCA_PCIE_V2, - SMCA_XGMI_PCS, /* xGMI PCS Unit */ - SMCA_NBIF, /* NBIF Unit */ - SMCA_SHUB, /* System HUB Unit */ + SMCA_PIE, /* Power, Interrupts, etc. */ + SMCA_PSP, /* Platform Security Processor */ + SMCA_PSP_V2, + SMCA_RESERVED, /* Reserved */ SMCA_SATA, /* SATA Unit */ + SMCA_SHUB, /* System HUB Unit */ + SMCA_SMU, /* System Management Unit */ + SMCA_SMU_V2, + SMCA_UMC, /* Unified Memory Controller */ + SMCA_UMC_V2, SMCA_USB, /* USB Unit */ - SMCA_USR_DP, /* Ultra Short Reach Data Plane Controller */ SMCA_USR_CP, /* Ultra Short Reach Control Plane Controller */ - SMCA_GMI_PCS, /* GMI PCS Unit */ - SMCA_XGMI_PHY, /* xGMI PHY Unit */ + SMCA_USR_DP, /* Ultra Short Reach Data Plane Controller */ SMCA_WAFL_PHY, /* WAFL PHY Unit */ - SMCA_GMI_PHY, /* GMI PHY Unit */ + SMCA_XGMI_PCS, /* xGMI PCS Unit */ + SMCA_XGMI_PHY, /* xGMI PHY Unit */ N_SMCA_BANK_TYPES }; diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index c80121281d3d..762597a84567 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -95,39 +95,39 @@ static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks); static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts); static const char * const smca_names[] = { - [SMCA_LS ... SMCA_LS_V2] = "load_store", - [SMCA_IF] = "insn_fetch", - [SMCA_L2_CACHE] = "l2_cache", + [SMCA_CS ... SMCA_CS_V2] = "coherent_slave", [SMCA_DE] = "decode_unit", - [SMCA_RESERVED] = "reserved", [SMCA_EX] = "execution_unit", [SMCA_FP] = "floating_point", + [SMCA_GMI_PCS] = "gmi_pcs", + [SMCA_GMI_PHY] = "gmi_phy", + [SMCA_IF] = "insn_fetch", + [SMCA_L2_CACHE] = "l2_cache", [SMCA_L3_CACHE] = "l3_cache", - [SMCA_CS ... SMCA_CS_V2] = "coherent_slave", - [SMCA_PIE] = "pie", - - /* UMC v2 is separate because both of them can exist in a single system. */ - [SMCA_UMC] = "umc", - [SMCA_UMC_V2] = "umc_v2", + [SMCA_LS ... SMCA_LS_V2] = "load_store", [SMCA_MA_LLC] = "ma_llc", - [SMCA_PB] = "param_block", - [SMCA_PSP ... SMCA_PSP_V2] = "psp", - [SMCA_SMU ... SMCA_SMU_V2] = "smu", [SMCA_MP5] = "mp5", [SMCA_MPDMA] = "mpdma", + [SMCA_NBIF] = "nbif", [SMCA_NBIO] = "nbio", + [SMCA_PB] = "param_block", [SMCA_PCIE ... SMCA_PCIE_V2] = "pcie", - [SMCA_XGMI_PCS] = "xgmi_pcs", - [SMCA_NBIF] = "nbif", - [SMCA_SHUB] = "shub", + [SMCA_PIE] = "pie", + [SMCA_PSP ... SMCA_PSP_V2] = "psp", + [SMCA_RESERVED] = "reserved", [SMCA_SATA] = "sata", + [SMCA_SHUB] = "shub", + [SMCA_SMU ... SMCA_SMU_V2] = "smu", + + /* UMC v2 is separate because both of them can exist in a single system. */ + [SMCA_UMC] = "umc", + [SMCA_UMC_V2] = "umc_v2", [SMCA_USB] = "usb", - [SMCA_USR_DP] = "usr_dp", [SMCA_USR_CP] = "usr_cp", - [SMCA_GMI_PCS] = "gmi_pcs", - [SMCA_XGMI_PHY] = "xgmi_phy", + [SMCA_USR_DP] = "usr_dp", [SMCA_WAFL_PHY] = "wafl_phy", - [SMCA_GMI_PHY] = "gmi_phy", + [SMCA_XGMI_PCS] = "xgmi_pcs", + [SMCA_XGMI_PHY] = "xgmi_phy", }; static const char *smca_get_name(enum smca_bank_types t) @@ -153,68 +153,49 @@ enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) } EXPORT_SYMBOL_GPL(smca_get_bank_type); +/* + * Format: + * { bank_type, hwid_mcatype } + * + * alphanumerically sorted by bank type. + */ static const struct smca_hwid smca_hwid_mcatypes[] = { - /* { bank_type, hwid_mcatype } */ - - /* Reserved type */ - { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) }, - - /* ZN Core (HWID=0xB0) MCA types */ - { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) }, - { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, - { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) }, - { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) }, + { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, + { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) }, - /* HWID 0xB0 MCATYPE 0x4 is Reserved */ { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) }, { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) }, + { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, + { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) }, + { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) }, + { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) }, { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) }, - - /* Data Fabric MCA types */ - { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, - { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, - { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, + { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) }, + { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, { SMCA_MA_LLC, HWID_MCATYPE(0x2E, 0x4) }, - - /* Unified Memory Controller MCA type */ - { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, - { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, - - /* Parameter Block MCA type */ - { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, - - /* Platform Security Processor MCA type */ - { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, - { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, - - /* System Management Unit MCA type */ - { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, - { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, - - /* Microprocessor 5 Unit MCA type */ { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) }, - - /* MPDMA MCA type */ { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) }, - - /* Northbridge IO Unit MCA type */ + { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) }, { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) }, - - /* PCI Express Unit MCA type */ + { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) }, { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) }, - - { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) }, - { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) }, - { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, + { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, + { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, + { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, + { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) }, { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) }, + { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, + { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, + { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, + { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, + { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) }, - { SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) }, { SMCA_USR_CP, HWID_MCATYPE(0x180, 0x0) }, - { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, - { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, + { SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) }, { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) }, - { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) }, + { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) }, + { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, }; /* diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index e6867b1bc9c5..ca8141793d53 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1164,36 +1164,36 @@ static void decode_mc6_mce(struct mce *m) } static const char * const smca_long_names[] = { - [SMCA_LS ... SMCA_LS_V2] = "Load Store Unit", - [SMCA_IF] = "Instruction Fetch Unit", - [SMCA_L2_CACHE] = "L2 Cache", + [SMCA_CS ... SMCA_CS_V2] = "Coherent Slave", [SMCA_DE] = "Decode Unit", - [SMCA_RESERVED] = "Reserved", [SMCA_EX] = "Execution Unit", [SMCA_FP] = "Floating Point Unit", + [SMCA_GMI_PCS] = "Global Memory Interconnect PCS Unit", + [SMCA_GMI_PHY] = "Global Memory Interconnect PHY Unit", + [SMCA_IF] = "Instruction Fetch Unit", + [SMCA_L2_CACHE] = "L2 Cache", [SMCA_L3_CACHE] = "L3 Cache", - [SMCA_CS ... SMCA_CS_V2] = "Coherent Slave", - [SMCA_PIE] = "Power, Interrupts, etc.", - - /* UMC v2 is separate because both of them can exist in a single system. */ - [SMCA_UMC] = "Unified Memory Controller", - [SMCA_UMC_V2] = "Unified Memory Controller v2", - [SMCA_PB] = "Parameter Block", - [SMCA_PSP ... SMCA_PSP_V2] = "Platform Security Processor", - [SMCA_SMU ... SMCA_SMU_V2] = "System Management Unit", + [SMCA_LS ... SMCA_LS_V2] = "Load Store Unit", [SMCA_MP5] = "Microprocessor 5 Unit", [SMCA_MPDMA] = "MPDMA Unit", + [SMCA_NBIF] = "NBIF Unit", [SMCA_NBIO] = "Northbridge IO Unit", + [SMCA_PB] = "Parameter Block", [SMCA_PCIE ... SMCA_PCIE_V2] = "PCI Express Unit", - [SMCA_XGMI_PCS] = "Ext Global Memory Interconnect PCS Unit", - [SMCA_NBIF] = "NBIF Unit", - [SMCA_SHUB] = "System Hub Unit", + [SMCA_PIE] = "Power, Interrupts, etc.", + [SMCA_PSP ... SMCA_PSP_V2] = "Platform Security Processor", + [SMCA_RESERVED] = "Reserved", [SMCA_SATA] = "SATA Unit", + [SMCA_SHUB] = "System Hub Unit", + [SMCA_SMU ... SMCA_SMU_V2] = "System Management Unit", + + /* UMC v2 is separate because both of them can exist in a single system. */ + [SMCA_UMC] = "Unified Memory Controller", + [SMCA_UMC_V2] = "Unified Memory Controller v2", [SMCA_USB] = "USB Unit", - [SMCA_GMI_PCS] = "Global Memory Interconnect PCS Unit", - [SMCA_XGMI_PHY] = "Ext Global Memory Interconnect PHY Unit", [SMCA_WAFL_PHY] = "WAFL PHY Unit", - [SMCA_GMI_PHY] = "Global Memory Interconnect PHY Unit", + [SMCA_XGMI_PCS] = "Ext Global Memory Interconnect PCS Unit", + [SMCA_XGMI_PHY] = "Ext Global Memory Interconnect PHY Unit", }; static const char *smca_get_long_name(enum smca_bank_types t) From a3f2db13cd719ca7d9d2f80a196b3dac5f48feba Mon Sep 17 00:00:00 2001 From: Yazen Ghannam Date: Sat, 7 Mar 2026 11:33:15 -0500 Subject: [PATCH 4/5] x86/mce, EDAC/mce_amd: Update CS bank type naming commit b595a009726b706fdadedace90c54831e19188e2 upstream. Recent documentation updated the "CS" bank type name from "Coherent Slave" to "Coherent Station". Apply this change in the kernel also. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20260307163316.345923-3-yazen.ghannam@amd.com Signed-off-by: priyanka-mani Signed-off-by: mohanasv2 --- arch/x86/include/asm/mce.h | 2 +- arch/x86/kernel/cpu/mce/amd.c | 2 +- drivers/edac/mce_amd.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index fa39acb41a61..1712c3fda608 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -351,7 +351,7 @@ extern void apei_mce_report_mem_error(int corrected, * Exception: Keep "V2, etc." with their originals. */ enum smca_bank_types { - SMCA_CS, /* Coherent Slave */ + SMCA_CS, /* Coherent Station */ SMCA_CS_V2, SMCA_DE, /* Decoder Unit */ SMCA_EX, /* Execution Unit */ diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 762597a84567..43a7ce8afe69 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -95,7 +95,7 @@ static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks); static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts); static const char * const smca_names[] = { - [SMCA_CS ... SMCA_CS_V2] = "coherent_slave", + [SMCA_CS ... SMCA_CS_V2] = "coherent_station", [SMCA_DE] = "decode_unit", [SMCA_EX] = "execution_unit", [SMCA_FP] = "floating_point", diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index ca8141793d53..94eac5d648d7 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1164,7 +1164,7 @@ static void decode_mc6_mce(struct mce *m) } static const char * const smca_long_names[] = { - [SMCA_CS ... SMCA_CS_V2] = "Coherent Slave", + [SMCA_CS ... SMCA_CS_V2] = "Coherent Station", [SMCA_DE] = "Decode Unit", [SMCA_EX] = "Execution Unit", [SMCA_FP] = "Floating Point Unit", From 7f5f7221ea4d61614eced51ccd7501389669a977 Mon Sep 17 00:00:00 2001 From: Yazen Ghannam Date: Sat, 7 Mar 2026 11:33:16 -0500 Subject: [PATCH 5/5] x86/mce, EDAC/mce_amd: Add new SMCA bank types commit b90d398138ab3088d168cacb2c3d5248feaa1ef7 upstream. Recognize new SMCA bank types and include their short names for sysfs and long names for decoding. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20260307163316.345923-4-yazen.ghannam@amd.com Signed-off-by: priyanka-mani Signed-off-by: mohanasv2 --- arch/x86/include/asm/mce.h | 11 +++++++++++ arch/x86/kernel/cpu/mce/amd.c | 21 +++++++++++++++++++++ drivers/edac/mce_amd.c | 10 ++++++++++ 3 files changed, 42 insertions(+) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 1712c3fda608..661ed4f88f2f 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -353,7 +353,10 @@ extern void apei_mce_report_mem_error(int corrected, enum smca_bank_types { SMCA_CS, /* Coherent Station */ SMCA_CS_V2, + SMCA_DACC_BE, /* Data Acceleration Back-end */ + SMCA_DACC_FE, /* Data Acceleration Front-end */ SMCA_DE, /* Decoder Unit */ + SMCA_EDDR5CMN, /* eDDR5 CMN */ SMCA_EX, /* Execution Unit */ SMCA_FP, /* Floating Point */ SMCA_GMI_PCS, /* GMI PCS Unit */ @@ -365,12 +368,19 @@ enum smca_bank_types { SMCA_LS_V2, SMCA_MA_LLC, /* Memory Attached Last Level Cache */ SMCA_MP5, /* Microprocessor 5 Unit */ + SMCA_MPART, /* AMD Root of Trust Microprocessor */ + SMCA_MPASP, /* AMD Secure Processor */ + SMCA_MPASP_V2, + SMCA_MPDACC, /* MP for Data Acceleration */ SMCA_MPDMA, /* MPDMA Unit */ + SMCA_MPM, /* Microprocessor Manageability Core */ + SMCA_MPRAS, /* MP for RAS */ SMCA_NBIF, /* NBIF Unit */ SMCA_NBIO, /* Northbridge IO Unit */ SMCA_PB, /* Parameter Block */ SMCA_PCIE, /* PCI Express Unit */ SMCA_PCIE_V2, + SMCA_PCIE_PL, /* PCIe Link */ SMCA_PIE, /* Power, Interrupts, etc. */ SMCA_PSP, /* Platform Security Processor */ SMCA_PSP_V2, @@ -379,6 +389,7 @@ enum smca_bank_types { SMCA_SHUB, /* System HUB Unit */ SMCA_SMU, /* System Management Unit */ SMCA_SMU_V2, + SMCA_SSBDCI, /* Die to Die Interconnect */ SMCA_UMC, /* Unified Memory Controller */ SMCA_UMC_V2, SMCA_USB, /* USB Unit */ diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 43a7ce8afe69..1dc7300f8f1e 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -96,7 +96,10 @@ static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts); static const char * const smca_names[] = { [SMCA_CS ... SMCA_CS_V2] = "coherent_station", + [SMCA_DACC_BE] = "dacc_be", + [SMCA_DACC_FE] = "dacc_fe", [SMCA_DE] = "decode_unit", + [SMCA_EDDR5CMN] = "eddr5_cmn", [SMCA_EX] = "execution_unit", [SMCA_FP] = "floating_point", [SMCA_GMI_PCS] = "gmi_pcs", @@ -107,17 +110,24 @@ static const char * const smca_names[] = { [SMCA_LS ... SMCA_LS_V2] = "load_store", [SMCA_MA_LLC] = "ma_llc", [SMCA_MP5] = "mp5", + [SMCA_MPART] = "mpart", + [SMCA_MPASP ... SMCA_MPASP_V2] = "mpasp", + [SMCA_MPDACC] = "mpdacc", [SMCA_MPDMA] = "mpdma", + [SMCA_MPM] = "mpm", + [SMCA_MPRAS] = "mpras", [SMCA_NBIF] = "nbif", [SMCA_NBIO] = "nbio", [SMCA_PB] = "param_block", [SMCA_PCIE ... SMCA_PCIE_V2] = "pcie", + [SMCA_PCIE_PL] = "pcie_pl", [SMCA_PIE] = "pie", [SMCA_PSP ... SMCA_PSP_V2] = "psp", [SMCA_RESERVED] = "reserved", [SMCA_SATA] = "sata", [SMCA_SHUB] = "shub", [SMCA_SMU ... SMCA_SMU_V2] = "smu", + [SMCA_SSBDCI] = "ssbdci", /* UMC v2 is separate because both of them can exist in a single system. */ [SMCA_UMC] = "umc", @@ -162,7 +172,10 @@ EXPORT_SYMBOL_GPL(smca_get_bank_type); static const struct smca_hwid smca_hwid_mcatypes[] = { { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, + { SMCA_DACC_BE, HWID_MCATYPE(0x164, 0x0) }, + { SMCA_DACC_FE, HWID_MCATYPE(0x157, 0x0) }, { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) }, + { SMCA_EDDR5CMN, HWID_MCATYPE(0x1E0, 0x0) }, { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) }, { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) }, { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, @@ -174,12 +187,19 @@ static const struct smca_hwid smca_hwid_mcatypes[] = { { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, { SMCA_MA_LLC, HWID_MCATYPE(0x2E, 0x4) }, { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) }, + { SMCA_MPART, HWID_MCATYPE(0xFF, 0x2) }, + { SMCA_MPASP, HWID_MCATYPE(0xFD, 0x0) }, + { SMCA_MPASP_V2, HWID_MCATYPE(0xFD, 0x1) }, + { SMCA_MPDACC, HWID_MCATYPE(0xBE, 0x0) }, { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) }, + { SMCA_MPM, HWID_MCATYPE(0xF9, 0x0) }, + { SMCA_MPRAS, HWID_MCATYPE(0x12, 0x0) }, { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) }, { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) }, { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) }, { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) }, + { SMCA_PCIE_PL, HWID_MCATYPE(0x1E1, 0x0) }, { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, @@ -188,6 +208,7 @@ static const struct smca_hwid smca_hwid_mcatypes[] = { { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, + { SMCA_SSBDCI, HWID_MCATYPE(0x5C, 0x0) }, { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) }, diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index 94eac5d648d7..b6dded1e8591 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1165,7 +1165,10 @@ static void decode_mc6_mce(struct mce *m) static const char * const smca_long_names[] = { [SMCA_CS ... SMCA_CS_V2] = "Coherent Station", + [SMCA_DACC_BE] = "DACC Back-end Unit", + [SMCA_DACC_FE] = "DACC Front-end Unit", [SMCA_DE] = "Decode Unit", + [SMCA_EDDR5CMN] = "eDDR5 CMN Unit", [SMCA_EX] = "Execution Unit", [SMCA_FP] = "Floating Point Unit", [SMCA_GMI_PCS] = "Global Memory Interconnect PCS Unit", @@ -1175,17 +1178,24 @@ static const char * const smca_long_names[] = { [SMCA_L3_CACHE] = "L3 Cache", [SMCA_LS ... SMCA_LS_V2] = "Load Store Unit", [SMCA_MP5] = "Microprocessor 5 Unit", + [SMCA_MPART] = "MPART Unit", + [SMCA_MPASP ... SMCA_MPASP_V2] = "MPASP Unit", + [SMCA_MPDACC] = "MPDACC Unit", [SMCA_MPDMA] = "MPDMA Unit", + [SMCA_MPM] = "MPM Unit", + [SMCA_MPRAS] = "MPRAS Unit", [SMCA_NBIF] = "NBIF Unit", [SMCA_NBIO] = "Northbridge IO Unit", [SMCA_PB] = "Parameter Block", [SMCA_PCIE ... SMCA_PCIE_V2] = "PCI Express Unit", + [SMCA_PCIE_PL] = "PCIe Link Unit", [SMCA_PIE] = "Power, Interrupts, etc.", [SMCA_PSP ... SMCA_PSP_V2] = "Platform Security Processor", [SMCA_RESERVED] = "Reserved", [SMCA_SATA] = "SATA Unit", [SMCA_SHUB] = "System Hub Unit", [SMCA_SMU ... SMCA_SMU_V2] = "System Management Unit", + [SMCA_SSBDCI] = "Die to Die Interconnect Unit", /* UMC v2 is separate because both of them can exist in a single system. */ [SMCA_UMC] = "Unified Memory Controller",