SystemRDL
Users following SystemRDL
Gabriel Villanova
gvillanovanm
Digital Design & Verification Engineer (RTL/UVM) | FPGA, ASIC & SoC Architecture | PhD researcher in Computer Engineering
Felipe Costa
FelipeWcosta
I'm a graduate student that works with digital systems, hardware description languages and microelectronics
University of São Paulo Brazil
Mikhail Lunacharskiy
lunacharskiym
I'm RTL-designer, verification engineer and python developer, interested in software development, low-level programming, hardware design and verification
MPEI
Hidemasa Kawasaki
h1demasa
I'm interested in System/Computer Architecture.
Ritsumeikan University Japan
sibeov
sibeov
HW-, FPGA-developer.
Interests:
- Design methodology
- Verification
- Automation
- SW-HW-interface / interaction
- DSP
- Cryptography
Norway
Jevin Sweval
jevinskie
Senior Security Researcher, compilers/optimizations/[de]obfuscation, SCA, program analysis, NFC ninja, HW hacker w/ FPGA hammer.
Lafayette, Indiana
Steve Glaser
sglaser
Engineer at Nvidia. Member, Board of Directors, PCI-SIG.
NVIDIA San Francisco, CA
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