diff --git a/src/cc_edge_detect.sv b/src/cc_edge_detect.sv
index 7bd510ac..4227ebda 100644
--- a/src/cc_edge_detect.sv
+++ b/src/cc_edge_detect.sv
@@ -14,7 +14,6 @@
 module cc_edge_detect (
     input  logic clk_i,   // Clock
     input  logic rst_ni,  // Asynchronous reset active low
-    input  logic clr_i,   // Synchronous clear active high
     input  logic d_i,     // Data stream in
     output logic re_o,    // Rising edge detected
     output logic fe_o     // Falling edge detected
@@ -23,8 +22,6 @@ module cc_edge_detect (
     cc_sync_wedge i_sync_wedge (
         .clk_i    ( clk_i  ),
         .rst_ni   ( rst_ni ),
-        .clr_i    ( clr_i  ),
-        .en_i     ( 1'b1   ),
         .serial_i ( d_i    ),
         .r_edge_o ( re_o   ),
         .f_edge_o ( fe_o   ),
diff --git a/src/cc_edge_propagator_ack.sv b/src/cc_edge_propagator_ack.sv
index 36d8c319..6df3457a 100644
--- a/src/cc_edge_propagator_ack.sv
+++ b/src/cc_edge_propagator_ack.sv
@@ -43,8 +43,6 @@ module cc_edge_propagator_ack (
   cc_sync_wedge u_sync_clkb (
     .clk_i    ( clk_rx_i    ),
     .rst_ni   ( rst_rx_ni   ),
-    .clr_i    ( '0          ),
-    .en_i     ( 1'b1        ),
     .serial_i ( r_input_reg ),
     .r_edge_o ( edge_o      ),
     .f_edge_o (             ),
diff --git a/src/cc_edge_propagator_rx.sv b/src/cc_edge_propagator_rx.sv
index 3377beaf..b5d2f379 100644
--- a/src/cc_edge_propagator_rx.sv
+++ b/src/cc_edge_propagator_rx.sv
@@ -21,8 +21,6 @@ module cc_edge_propagator_rx (
     cc_sync_wedge i_sync_clkb (
         .clk_i    ( clk_i   ),
         .rst_ni   ( rst_ni  ),
-        .clr_i    ( '0      ),
-        .en_i     ( 1'b1    ),
         .serial_i ( valid_i ),
         .r_edge_o ( valid_o ),
         .f_edge_o (         ),
diff --git a/src/cc_sync_wedge.sv b/src/cc_sync_wedge.sv
index f0168872..bd450cef 100644
--- a/src/cc_sync_wedge.sv
+++ b/src/cc_sync_wedge.sv
@@ -17,14 +17,11 @@ module cc_sync_wedge #(
 ) (
     input  logic clk_i,    // Clock
     input  logic rst_ni,   // Asynchronous reset active low
-    input  logic clr_i,    // Synchronous clear active high
-    input  logic en_i,
     input  logic serial_i,
     output logic r_edge_o,
     output logic f_edge_o,
     output logic serial_o
 );
-    logic clk;
     logic serial, serial_q;
 
     assign serial_o =  serial_q;
@@ -40,12 +37,5 @@ module cc_sync_wedge #(
         .serial_o ( serial )
     );
 
-    pulp_clock_gating i_pulp_clock_gating (
-        .clk_i,
-        .en_i,
-        .test_en_i ( 1'b0 ),
-        .clk_o     ( clk  )
-    );
-
-    `FFLARNC(serial_q, serial, en_i, clr_i, 1'b0, clk, rst_ni)
+    `FF(serial_q, serial, 1'b0, clk_i, rst_ni)
 endmodule
diff --git a/src/deprecated/edge_detect.sv b/src/deprecated/edge_detect.sv
index d65ea66d..f4f78dff 100644
--- a/src/deprecated/edge_detect.sv
+++ b/src/deprecated/edge_detect.sv
@@ -17,7 +17,6 @@ module edge_detect (
   cc_edge_detect i_cc_edge_detect (
     .clk_i  ( clk_i  ),
     .rst_ni ( rst_ni ),
-    .clr_i  ( 1'b0  ),
     .d_i    ( d_i    ),
     .re_o   ( re_o   ),
     .fe_o   ( fe_o   )
diff --git a/src/deprecated/sync_wedge.sv b/src/deprecated/sync_wedge.sv
index 675646f6..9b122e05 100644
--- a/src/deprecated/sync_wedge.sv
+++ b/src/deprecated/sync_wedge.sv
@@ -9,7 +9,7 @@ module sync_wedge #(
 ) (
   input  logic clk_i,
   input  logic rst_ni,
-  input  logic en_i,
+  input  logic en_i, // Retained for source compatibility; intentionally ignored.
   input  logic serial_i,
   output logic r_edge_o,
   output logic f_edge_o,
@@ -18,13 +18,12 @@ module sync_wedge #(
   // synthesis translate_off
   initial $warning("Module '%m' is deprecated. Use 'cc_sync_wedge' instead.");
   // synthesis translate_on
+
   cc_sync_wedge #(
     .Stages ( STAGES )
   ) i_cc_sync_wedge (
     .clk_i    ( clk_i    ),
     .rst_ni   ( rst_ni   ),
-    .clr_i   ( 1'b0   ),
-    .en_i     ( en_i     ),
     .serial_i ( serial_i ),
     .r_edge_o ( r_edge_o ),
     .f_edge_o ( f_edge_o ),