diff --git a/libplatsupport/CMakeLists.txt b/libplatsupport/CMakeLists.txt index 5e3b9896e..a93189978 100644 --- a/libplatsupport/CMakeLists.txt +++ b/libplatsupport/CMakeLists.txt @@ -115,7 +115,7 @@ endif() if(KernelPlatformExynos5422) list(APPEND deps src/mach/${LibPlatSupportMach}/clock/exynos_5422_clock.c) -elseif(KernelPlatformExynos4 OR KernelPlatformExynos5410 OR KernelPlatformExynos5250) +elseif(KernelPlatformExynos5410) list(APPEND deps src/mach/${LibPlatSupportMach}/clock/exynos_common_clock.c) endif() diff --git a/libplatsupport/plat_include/apq8064/platsupport/plat/clock.h b/libplatsupport/plat_include/apq8064/platsupport/plat/clock.h deleted file mode 100644 index 3b608a6da..000000000 --- a/libplatsupport/plat_include/apq8064/platsupport/plat/clock.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -#define PXO_HZ 27000000UL -#define CXO_HZ 19200000UL -#define WCNXO_HZ 48000000UL /* WLAN */ -#define SLPXO_HZ 32768UL - -#define TCXO_HZ 19200000UL /* Alias: TXCO (typo in docs) */ - -#define APQ8064_CLK_CTL0_PADDR 0x00900000 -#define APQ8064_CLK_CTL1_PADDR 0x00901000 -#define APQ8064_CLK_CTL2_PADDR 0x00902000 -#define APQ8064_CLK_CTL3_PADDR 0x00903000 - -#define APQ8064_CLK_CTL_SIZE 0x1000 -#define APQ8064_CLK_CTL0_SIZE APQ8064_CLK_CTL_SIZE -#define APQ8064_CLK_CTL1_SIZE APQ8064_CLK_CTL_SIZE -#define APQ8064_CLK_CTL2_SIZE APQ8064_CLK_CTL_SIZE -#define APQ8064_CLK_CTL3_SIZE APQ8064_CLK_CTL_SIZE - -enum clk_id { - CLK_MASTER, - CLK_PXO, - CLK_TCXO, - CLK_WCNXO, - CLK_SLPXO, -#if 0 - PLL0 GPLL0 PXO 800MHz - PLL1 MMPLL0 PXO 1332MHz - PLL2 MMPLL1 PXO 800MHz - PLL3 QDSPLL PXO 1200MHz - PLL4 LPAPLL PXO 393.2160MHz (491.52 ver2) - PLL5 MPLL0 CXO 288MHz - PLL8 SPPLL PXO 384MHz - PLL9 SCPLL0 PXO 2000MHz - PLL10 SCPLL1 PXO 2000MHz - PLL11 EBI1PLL PXO 1066MHz - PLL12 SCL2PLL PXO 1700MHz - PLL13 WCNPLL WCNXO (CXO used if WCNXO absent) 960MHz - PLL14 SP2PLL PXO 480MHz - PLL15 MMPLL3 PXO 975MHz - PLL16 SCPLL2 PXO 2000MHz - PLL17 SCPLL3 PXO 2000MHz - -#endif - NCLOCKS -}; - -enum clock_gate { - NCLKGATES, -}; - -int apq_clock_sys_init(void* clk_ctl_base0, void* clk_ctl_base1, - void* clk_ctl_base2, void* clk_ctl_base3, - clock_sys_t* clk_sys); - diff --git a/libplatsupport/plat_include/apq8064/platsupport/plat/i2c.h b/libplatsupport/plat_include/apq8064/platsupport/plat/i2c.h deleted file mode 100644 index 40efe17b5..000000000 --- a/libplatsupport/plat_include/apq8064/platsupport/plat/i2c.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -enum i2c_id { - NI2C -}; - diff --git a/libplatsupport/plat_include/apq8064/platsupport/plat/serial.h b/libplatsupport/plat_include/apq8064/platsupport/plat/serial.h deleted file mode 100644 index 345ec031f..000000000 --- a/libplatsupport/plat_include/apq8064/platsupport/plat/serial.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -#define GSBI3_UART_PADDR 0x16240000 -#define GSBI4_UART_PADDR 0x16340000 -#define GSBI5_UART_PADDR 0x1A240000 -#define GSBI6_UART_PADDR 0x16540000 -#define GSBI7_UART_PADDR 0x16640000 - -#define GSBI3_UART_IRQ -1 -#define GSBI4_UART_IRQ -1 -#define GSBI5_UART_IRQ -1 -#define GSBI6_UART_IRQ -1 -#define GSBI7_UART_IRQ -1 - -/* official device names */ -enum chardev_id { - GSBI3_UART, - GSBI4_UART, - GSBI5_UART, - GSBI6_UART, - GSBI7_UART, - /* Aliases */ - PS_SERIAL0 = GSBI3_UART, - PS_SERIAL1 = GSBI4_UART, - PS_SERIAL2 = GSBI5_UART, - PS_SERIAL3 = GSBI6_UART, - PS_SERIAL4 = GSBI7_UART, - /* defaults */ - PS_SERIAL_DEFAULT = GSBI7_UART -}; - -#define DEFAULT_SERIAL_PADDR GSBI7_UART_PADDR -#define DEFAULT_SERIAL_INTERRUPT GSBI7_UART_IRQ diff --git a/libplatsupport/plat_include/apq8064/platsupport/plat/timer.h b/libplatsupport/plat_include/apq8064/platsupport/plat/timer.h deleted file mode 100644 index b9c282c6e..000000000 --- a/libplatsupport/plat_include/apq8064/platsupport/plat/timer.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ -/* @AUTHOR(akroh@ertos.nicta.com.au) */ - -#pragma once - -#include - -#include - -/* frequency of the generic timer */ -#define PCT_TICKS_PER_US 208llu - -/* Memory maps */ -#define RPM_TIMERS_PADDR 0x00062000 -#define RPM_TIMERS_SIZE 0x1000 - -#define KPSS_TIMERS_PADDR 0x0200A000 -#define KPSS_TIMERS_SIZE 0x1000 - -#define GSS_TIMERS_PADDR 0x10002000 -#define GSS_TIMERS_SIZE 0x1000 - -#define PPSS_XO_TIMERS_PADDR 0x12080000 -#define PPSS_XO_TIMERS_SIZE 0x1000 -#define PPSS_SLP_TIMERS_PADDR 0x12081000 -#define PPSS_SLP_TIMERS_SIZE 0x1000 - -/* IRQs */ -#define DUMMY_IRQ 99 - -#define PPSS_XO_TMR0_INTERRUPT 241 -#define PPSS_XO_TMR1_INTERRUPT 242 -#define PPSS_SLP_TMR0_INTERRUPT 243 -#define PPSS_SLP_TMR1_INTERRUPT 244 -#define PPSS_SLP_WDOG_INTERRUPT 245 - -#define KPSS_DGT_INTERRUPT 17 -#define KPSS_GPT0_INTERRUPT 18 -#define KPSS_GPT1_INTERRUPT 19 -#define KPSS_WDT0_INTERRUPT 20 -#define KPSS_WDT1_INTERRUPT 21 - -#define GSS_GPT0_INTERRUPT DUMMY_IRQ -#define GSS_GPT1_INTERRUPT DUMMY_IRQ -#define GSS_DGT_INTERRUPT 34 /* ? */ -#define GSS_WDT0_INTERRUPT 68 /* ? */ -#define GSS_WDT1_INTERRUPT DUMMY_IRQ - -#define RPM_GPT0_INTERRUPT 66 -#define RPM_GPT1_INTERRUPT 67 -#define RPM_WDOG_INTERRUPT 68 - -/* Timers */ -enum timer_id { - TMR_PPSS_XO_TMR0, - TMR_PPSS_XO_TMR1, - TMR_PPSS_SLP_TMR0, - TMR_PPSS_SLP_TMR1, - TMR_PPSS_SLP_WDOG, - TMR_RPM_GPT0, - TMR_RPM_GPT1, - TMR_RPM_WDOG, - TMR_KPSS_GPT0, - TMR_KPSS_GPT1, - TMR_KPSS_DGT, /* Currently used by the kernel */ - TMR_KPSS_WDT0, - TMR_KPSS_WDT1, - TMR_GSS_GPT0, - TMR_GSS_GPT1, - TMR_GSS_DGT, - TMR_GSS_WDT0, - TMR_GSS_WDT1, - /* More timers in Audio subsystem 0x28880000 */ - NTIMERS -}; -#define TMR_DEFAULT TMR_KPSS_GPT0 - -static const uintptr_t apq8064_timer_paddrs[] = { - [TMR_PPSS_XO_TMR0 ] = PPSS_XO_TIMERS_PADDR, - [TMR_PPSS_XO_TMR1 ] = PPSS_XO_TIMERS_PADDR, - [TMR_PPSS_SLP_TMR0] = PPSS_SLP_TIMERS_PADDR, - [TMR_PPSS_SLP_TMR1] = PPSS_SLP_TIMERS_PADDR, - [TMR_PPSS_SLP_WDOG] = PPSS_SLP_TIMERS_PADDR, - [TMR_RPM_GPT0 ] = RPM_TIMERS_PADDR, - [TMR_RPM_GPT1 ] = RPM_TIMERS_PADDR, - [TMR_RPM_WDOG ] = RPM_TIMERS_PADDR, - [TMR_KPSS_GPT0 ] = KPSS_TIMERS_PADDR, - [TMR_KPSS_GPT1 ] = KPSS_TIMERS_PADDR, - [TMR_KPSS_DGT ] = KPSS_TIMERS_PADDR, - [TMR_KPSS_WDT0 ] = KPSS_TIMERS_PADDR, - [TMR_KPSS_WDT1 ] = KPSS_TIMERS_PADDR, - [TMR_GSS_GPT0 ] = GSS_TIMERS_PADDR, - [TMR_GSS_GPT1 ] = GSS_TIMERS_PADDR, - [TMR_GSS_DGT ] = GSS_TIMERS_PADDR, - [TMR_GSS_WDT0 ] = GSS_TIMERS_PADDR, - [TMR_GSS_WDT1 ] = GSS_TIMERS_PADDR -}; - -static const int apq8064_timer_irqs[] = { - [TMR_PPSS_XO_TMR0 ] = PPSS_XO_TMR0_INTERRUPT, - [TMR_PPSS_XO_TMR1 ] = PPSS_XO_TMR0_INTERRUPT, - [TMR_PPSS_SLP_TMR0] = PPSS_SLP_TMR0_INTERRUPT, - [TMR_PPSS_SLP_TMR1] = PPSS_SLP_TMR1_INTERRUPT, - [TMR_PPSS_SLP_WDOG] = PPSS_SLP_WDOG_INTERRUPT, - [TMR_RPM_GPT0 ] = RPM_GPT0_INTERRUPT, - [TMR_RPM_GPT1 ] = RPM_GPT1_INTERRUPT, - [TMR_RPM_WDOG ] = RPM_WDOG_INTERRUPT, - [TMR_KPSS_GPT0 ] = KPSS_GPT0_INTERRUPT, - [TMR_KPSS_GPT1 ] = KPSS_GPT1_INTERRUPT, - [TMR_KPSS_DGT ] = KPSS_DGT_INTERRUPT, - [TMR_KPSS_WDT0 ] = KPSS_WDT0_INTERRUPT, - [TMR_KPSS_WDT1 ] = KPSS_WDT1_INTERRUPT, - [TMR_GSS_GPT0 ] = GSS_GPT0_INTERRUPT, - [TMR_GSS_GPT1 ] = GSS_GPT1_INTERRUPT, - [TMR_GSS_DGT ] = GSS_DGT_INTERRUPT, - [TMR_GSS_WDT0 ] = GSS_WDT0_INTERRUPT, - [TMR_GSS_WDT1 ] = GSS_WDT1_INTERRUPT -}; - -typedef struct { - /* vaddr pwm is mapped to */ - void *vaddr; - int id; -} timer_config_t; - -typedef struct { - void *data; - int id; -} timer_t; - -int gpt_timer_start(timer_t *timer); -int gpt_timer_stop(timer_t *timer); -uint64_t gpt_get_time(timer_t *timer); -void gpt_handle_irq(timer_t *timer); -int gpt_periodic(timer_t *timer, uint64_t ns); - -int dgt_timer_start(timer_t *timer); -int dgt_timer_stop(timer_t *timer); -uint64_t dpt_get_time(timer_t *timer); -int dgt_periodic(timer_t *timer, uint64_t ns); -void dgt_handle_irq(timer_t *timer); - -int tmr_timer_start(timer_t *timer); -int tmr_timer_stop(timer_t *timer); -uint64_t tmr_get_time(timer_t *timer); -int tmr_periodic(timer_t *timer, uint64_t ns); -void tmr_handle_irq(timer_t *timer); - -int wdt_timer_start(timer_t *timer); -uint64_t wdt_get_time(timer_t *timer); -int wdt_periodic(timer_t *timer, uint64_t ns); - -int timer_init(timer_t *timer, timer_config_t config); diff --git a/libplatsupport/plat_include/exynos4/platsupport/plat/clock.h b/libplatsupport/plat_include/exynos4/platsupport/plat/clock.h deleted file mode 100644 index 3a755b662..000000000 --- a/libplatsupport/plat_include/exynos4/platsupport/plat/clock.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -enum clk_id { - CLK_MASTER, - /* PLLS */ - CLK_SCLKMPLL, - CLK_SCLKEPLL, - CLK_SCLKVPLL, - CLK_MOUTAPLL, - CLK_SCLKAPLL, - CLK_SCLKMPLL_USERC, - CLK_ACLK_COREM0, - CLK_ACLK_CORES, - CLK_ACLK_COREM1, - CLK_PERIPHCLK, - CLK_SCLKHPM, - CLK_ATCLK, - CLK_PCLK_DBG, - /* Dividers */ - CLK_DIVCORE, - CLK_DIVCORE2, - CLK_DIVCOPY, - /* Muxes */ - CLK_MUXCORE, - CLK_MUXHPM, - /* Peripherals */ - CLK_UART0, - CLK_UART1, - CLK_UART2, - CLK_UART3, - - CLK_SPI0, - CLK_SPI1, - CLK_SPI2, - CLK_SPI0_ISP, - CLK_SPI1_ISP, - /* ----- */ - NCLOCKS, - /* Aliases */ - DIV_HPM = CLK_SCLKHPM, - CLK_ARMCLK = CLK_DIVCORE2, - CLK_TRACECLK = CLK_ATCLK, - CLK_CTMCLK = CLK_ATCLK, - CLK_HCLK_CSSYS = CLK_ATCLK, - CLK_TSVAL_UECKL = CLK_PCLK_DBG, - CLK_FINPLL = CLK_MASTER, -}; - -enum clock_gate { - NCLKGATES, -}; - diff --git a/libplatsupport/plat_include/exynos4/platsupport/plat/dma330.h b/libplatsupport/plat_include/exynos4/platsupport/plat/dma330.h deleted file mode 100644 index bfe040d6f..000000000 --- a/libplatsupport/plat_include/exynos4/platsupport/plat/dma330.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -#define MDMA0_PADDR 0x10800000 -#define MDMA1_PADDR 0x11C10000 -#define PDMA0_PADDR 0x121A0000 -#define PDMA1_PADDR 0x121B0000 - -#define DMA330_SIZE 0x1000 -#define MDMA0_SIZE DMA330_SIZE -#define MDMA1_SIZE DMA330_SIZE -#define PDMA0_SIZE DMA330_SIZE -#define PDMA1_SIZE DMA330_SIZE - -#define MDMA0_IRQ 65 -#define MDMA1_IRQ 156 -#define MDMA0_ABORT_IRQ 47 -#define MDMA1_ABORT_IRQ 45 -#define PDMA0_IRQ 66 -#define PDMA1_IRQ 67 - -enum dma330_id { - PL330_MDMA0, - PL330_MDMA1, - PL330_PDMA0, - PL330_PDMA1, - NPL330 -}; - -static const uint32_t dma330_paddr[] = { - [PL330_MDMA0] = MDMA0_PADDR, - [PL330_MDMA1] = MDMA1_PADDR, - [PL330_PDMA0] = PDMA0_PADDR, - [PL330_PDMA1] = PDMA1_PADDR -}; - -static const uint32_t dma330_size[] = { - [PL330_MDMA0] = MDMA0_SIZE, - [PL330_MDMA1] = MDMA1_SIZE, - [PL330_PDMA0] = PDMA0_SIZE, - [PL330_PDMA1] = PDMA1_SIZE -}; - -static const int dma330_irq[] = { - [PL330_MDMA0] = MDMA0_IRQ, - [PL330_MDMA1] = MDMA1_IRQ, - [PL330_PDMA0] = PDMA0_IRQ, - [PL330_PDMA1] = PDMA1_IRQ -}; - -static const int dma330_abort_irq[] = { - [PL330_MDMA0] = MDMA0_ABORT_IRQ, - [PL330_MDMA1] = MDMA1_ABORT_IRQ, - [PL330_PDMA0] = -1, - [PL330_PDMA1] = -1 -}; - diff --git a/libplatsupport/plat_include/exynos4/platsupport/plat/gpio.h b/libplatsupport/plat_include/exynos4/platsupport/plat/gpio.h deleted file mode 100644 index f7f2d3a8d..000000000 --- a/libplatsupport/plat_include/exynos4/platsupport/plat/gpio.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -#include -#include - -/* Port encodings */ -#define _GPIOPORT(bank, port) (((bank) << 8) | (port)) -#define GPIOPORT_GET_BANK(port) ((port) >> 8) -#define GPIOPORT_GET_PORT(port) ((port) & 0xff) -#define GPIOPORT(bank, port) _GPIOPORT(GPIO_##bank##_BANK, port) -#define GPIOPORT_NONE _GPIOPORT(GPIO_NBANKS, 0) - -#define XEINT0 GPIOID(GPX0, 0) -#define XEINT1 GPIOID(GPX0, 1) -#define XEINT2 GPIOID(GPX0, 2) -#define XEINT3 GPIOID(GPX0, 3) -#define XEINT4 GPIOID(GPX0, 4) -#define XEINT5 GPIOID(GPX0, 5) -#define XEINT6 GPIOID(GPX0, 6) -#define XEINT7 GPIOID(GPX0, 7) -#define XEINT8 GPIOID(GPX1, 0) -#define XEINT9 GPIOID(GPX1, 1) -#define XEINT10 GPIOID(GPX1, 2) -#define XEINT11 GPIOID(GPX1, 3) -#define XEINT12 GPIOID(GPX1, 4) -#define XEINT13 GPIOID(GPX1, 5) -#define XEINT14 GPIOID(GPX1, 6) -#define XEINT15 GPIOID(GPX1, 7) -#define XEINT16 GPIOID(GPX2, 0) -#define XEINT17 GPIOID(GPX2, 1) -#define XEINT18 GPIOID(GPX2, 2) -#define XEINT19 GPIOID(GPX2, 3) -#define XEINT20 GPIOID(GPX2, 4) -#define XEINT21 GPIOID(GPX2, 5) -#define XEINT22 GPIOID(GPX2, 6) -#define XEINT23 GPIOID(GPX2, 7) -#define XEINT24 GPIOID(GPX3, 0) -#define XEINT25 GPIOID(GPX3, 1) -#define XEINT26 GPIOID(GPX3, 2) -#define XEINT27 GPIOID(GPX3, 3) -#define XEINT28 GPIOID(GPX3, 4) -#define XEINT29 GPIOID(GPX3, 5) -#define XEINT30 GPIOID(GPX3, 6) -#define XEINT31 GPIOID(GPX3, 7) - -#define MAX_GPIO_ID XEINT31 - -enum gpio_bank { - GPIO_LEFT_BANK, - GPIO_RIGHT_BANK, - GPIO_C2C_BANK, - GPIO_AUDIO_BANK, - GPIO_NBANKS -}; - -enum gpio_port { - /* LEFT */ - GPA0 = GPIOPORT(LEFT, 0), /* 0x000 */ - GPA1 = GPIOPORT(LEFT, 1), /* 0x020 */ - GPB = GPIOPORT(LEFT, 2), /* 0x040 */ - GPC0 = GPIOPORT(LEFT, 3), /* 0x060 */ - GPC1 = GPIOPORT(LEFT, 4), /* 0x080 */ - GPD0 = GPIOPORT(LEFT, 5), /* 0x0A0 */ - GPD1 = GPIOPORT(LEFT, 6), /* 0x0C0 */ - - GPF0 = GPIOPORT(LEFT, 12), /* 0x180 */ - GPF1 = GPIOPORT(LEFT, 13), /* 0x1A0 */ - GPF2 = GPIOPORT(LEFT, 14), /* 0x1C0 */ - GPF3 = GPIOPORT(LEFT, 15), /* 0x1E0 */ - ETC1 = GPIOPORT(LEFT, 17), /* 0x220 */ - GPJ0 = GPIOPORT(LEFT, 18), /* 0x240 */ - GPJ1 = GPIOPORT(LEFT, 19), /* 0x260 */ - - /* RIGHT */ - GPK0 = GPIOPORT(RIGHT, 2), /* 0x040 */ - GPK1 = GPIOPORT(RIGHT, 3), /* 0x060 */ - GPK2 = GPIOPORT(RIGHT, 4), /* 0x080 */ - GPK3 = GPIOPORT(RIGHT, 5), /* 0x0A0 */ - GPL0 = GPIOPORT(RIGHT, 6), /* 0x0C0 */ - GPL1 = GPIOPORT(RIGHT, 7), /* 0x0E0 */ - GPL2 = GPIOPORT(RIGHT, 8), /* 0x100 */ - GPY0 = GPIOPORT(RIGHT, 9), /* 0x120 */ - GPY1 = GPIOPORT(RIGHT, 10), /* 0x140 */ - GPY2 = GPIOPORT(RIGHT, 11), /* 0x160 */ - GPY3 = GPIOPORT(RIGHT, 12), /* 0x180 */ - GPY4 = GPIOPORT(RIGHT, 13), /* 0x1A0 */ - GPY5 = GPIOPORT(RIGHT, 14), /* 0x1C0 */ - GPY6 = GPIOPORT(RIGHT, 15), /* 0x1E0 */ - ETC0 = GPIOPORT(RIGHT, 16), /* 0x200 */ - GPM0 = GPIOPORT(RIGHT, 19), /* 0x260 */ - GPM1 = GPIOPORT(RIGHT, 20), /* 0x280 */ - GPM2 = GPIOPORT(RIGHT, 21), /* 0x2A0 */ - GPM3 = GPIOPORT(RIGHT, 22), /* 0x2C0 */ - GPM4 = GPIOPORT(RIGHT, 23), /* 0x2E0 */ - /* GPX */ - GPX0 = GPIOPORT(RIGHT, 96), /* 0xC00 */ - GPX1 = GPIOPORT(RIGHT, 97), /* 0xC20 */ - GPX2 = GPIOPORT(RIGHT, 98), /* 0xC40 */ - GPX3 = GPIOPORT(RIGHT, 99), /* 0xC60 */ - - /* C2C */ - GPZ = GPIOPORT(C2C, 0), /* 0x000 */ - - /* AUDIO */ - GPV0 = GPIOPORT(AUDIO, 0), /* 0x000 */ - GPV1 = GPIOPORT(AUDIO, 1), /* 0x020 */ - ETC7 = GPIOPORT(AUDIO, 2), /* 0x040 */ - GPV2 = GPIOPORT(AUDIO, 3), /* 0x060 */ - GPV3 = GPIOPORT(AUDIO, 4), /* 0x080 */ - ETC8 = GPIOPORT(AUDIO, 5), /* 0x0A0 */ - GPV4 = GPIOPORT(AUDIO, 6), /* 0x0C0 */ -}; - -/** - * Initialise the exynos GPIO system given an exynos MUX subsystem - * @param[in] mux_sys A handle to the mux subsystem. This subsystem - * must contain memory mapped IO for the MUX regions. - * @param[out] gpio_sys A handle to a gpio subsystem to populate. - * @return 0 on success - */ -int exynos_gpio_sys_init(mux_sys_t *mux_sys, gpio_sys_t *gpio_sys); - diff --git a/libplatsupport/plat_include/exynos4/platsupport/plat/i2c.h b/libplatsupport/plat_include/exynos4/platsupport/plat/i2c.h deleted file mode 100644 index 25b6b4bfc..000000000 --- a/libplatsupport/plat_include/exynos4/platsupport/plat/i2c.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -enum i2c_id { - I2C0, - I2C1, - I2C2, - I2C3, - I2C4, - I2C5, - I2C6, - I2C7, - NI2C -}; - -/** - * Initalise an exynos I2C bus with memory mapped i2c deviced - * @param[in] id The id of the I2C bus to initalise - * @param[in] base The base address of the i2c device's mapped memory - * @param[in] mux Mux system for exynos - * @param[out] i2c I2C bus struct to be populated - */ -int exynos_i2c_init(enum i2c_id id, void* base, mux_sys_t* mux, i2c_bus_t* i2c); - diff --git a/libplatsupport/plat_include/exynos4/platsupport/plat/irq_combiner.h b/libplatsupport/plat_include/exynos4/platsupport/plat/irq_combiner.h deleted file mode 100644 index a7e6ba83d..000000000 --- a/libplatsupport/plat_include/exynos4/platsupport/plat/irq_combiner.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -enum irq_combiner_id { - IRQ_COMBINER0, - NIRQ_COMBINERS -}; - -#define EXYNOS4_IRQ_COMBINER_PADDR 0x10440000 -#define EXYNOS4_IRQ_COMBINER_SIZE 0x1000 - -#define EXYNOS_IRQ_COMBINER_PADDR EXYNOS4_IRQ_COMBINER_PADDR -#define EXYNOS_IRQ_COMBINER_SIZE EXYNOS4_IRQ_COMBINER_SIZE - -/** - * Initialise the IRQ combiner with a provided address for IO access - * @param[in] base The memory address of the combiner registers - * @param[out] combiner An IRQ combiner structure to populate - * @return 0 on success. - */ -int exynos_irq_combiner_init(void* base, irq_combiner_t* combiner); - diff --git a/libplatsupport/plat_include/exynos4/platsupport/plat/mux.h b/libplatsupport/plat_include/exynos4/platsupport/plat/mux.h deleted file mode 100644 index 85b0f7e92..000000000 --- a/libplatsupport/plat_include/exynos4/platsupport/plat/mux.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -#define EXYNOS_GPIOLEFT_PADDR 0x11400000 -#define EXYNOS_GPIORIGHT_PADDR 0x11000000 -#define EXYNOS_GPIOC2C_PADDR 0x106E0000 -#define EXYNOS_GPIOAUDIO_PADDR 0x03860000 - -#define EXYNOS_GPIOX_SIZE 0x1000 -#define EXYNOS_GPIOLEFT_SIZE EXYNOS_GPIOX_SIZE -#define EXYNOS_GPIORIGHT_SIZE EXYNOS_GPIOX_SIZE -#define EXYNOS_GPIOC2C_SIZE EXYNOS_GPIOX_SIZE -#define EXYNOS_GPIOAUDIO_SIZE EXYNOS_GPIOX_SIZE - -enum mux_feature { - MUX_I2C0, - MUX_I2C1, - MUX_I2C2, - MUX_I2C3, - MUX_I2C4, - MUX_I2C5, - MUX_I2C6, - MUX_I2C7, - MUX_SPI0, - MUX_SPI1, - MUX_SPI2, - MUX_UART0, - MUX_UART0_FLOW, - MUX_UART1, - MUX_UART1_FLOW, - MUX_UART2, - MUX_UART2_FLOW, - MUX_UART3, - MUX_UART3_FLOW, - MUX_SROM, - MUX_EBI, - NMUX_FEATURES -}; - -/** - * Initialise the mux subsystem with pre-mapped regions. - * @param[in] bankX A virtual mapping for bank X of the MUX subsystem. - * bank3 and bank4 are present for compatibility reasons - * only and can be passed as NULL. - * @param[out] mux On success, this will be filled with the appropriate - * subsystem data. - * @return 0 on success - */ -int exynos_mux_init(void* bank1, - void* bank2, - void* bank3, - void* bank4, - mux_sys_t* mux); - diff --git a/libplatsupport/plat_include/exynos4/platsupport/plat/pmic.h b/libplatsupport/plat_include/exynos4/platsupport/plat/pmic.h deleted file mode 100644 index d52cb0b90..000000000 --- a/libplatsupport/plat_include/exynos4/platsupport/plat/pmic.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -#define PMIC_BUSADDR MAX77686_BUSADDR -#define PMIC_I2C I2C0 - -#define LDO_VDDIO 3 -#define LDO_MMC2 4 -#define LDO_MMC13 5 -#define LDO_EMMC 20 -#define LDO_TFLASH 21 -#define LDO_VDDQLCD 25 - diff --git a/libplatsupport/plat_include/exynos4/platsupport/plat/pwm.h b/libplatsupport/plat_include/exynos4/platsupport/plat/pwm.h deleted file mode 100644 index 87d2a9e2f..000000000 --- a/libplatsupport/plat_include/exynos4/platsupport/plat/pwm.h +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ -#pragma once - -#define PWM_TIMER_PATH "/soc/pwm@139d0000" diff --git a/libplatsupport/plat_include/exynos4/platsupport/plat/serial.h b/libplatsupport/plat_include/exynos4/platsupport/plat/serial.h deleted file mode 100644 index bc57ffe92..000000000 --- a/libplatsupport/plat_include/exynos4/platsupport/plat/serial.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -#define EXYNOS_UART0_PADDR 0x13800000 -#define EXYNOS_UART1_PADDR 0x13810000 -#define EXYNOS_UART2_PADDR 0x13820000 -#define EXYNOS_UART3_PADDR 0x13830000 -#define EXYNOS_UART4_PADDR 0x13840000 - -#define EXYNOS_UART0_IRQ 84 -#define EXYNOS_UART1_IRQ 85 -#define EXYNOS_UART2_IRQ 86 -#define EXYNOS_UART3_IRQ 87 -#define EXYNOS_UART4_IRQ 88 - -#define UART_DEFAULT_FIN 90000000 - -/* official device names */ -enum chardev_id { - PS_SERIAL0, - PS_SERIAL1, - PS_SERIAL2, - PS_SERIAL3, - PS_NSERIAL, - /* defaults */ - PS_SERIAL_DEFAULT = PS_SERIAL1 -}; - -#include - -#define DEFAULT_SERIAL_PADDR EXYNOS_UART1_PADDR -#define DEFAULT_SERIAL_INTERRUPT EXYNOS_UART1_IRQ diff --git a/libplatsupport/plat_include/exynos4/platsupport/plat/spi.h b/libplatsupport/plat_include/exynos4/platsupport/plat/spi.h deleted file mode 100644 index 01a7053a3..000000000 --- a/libplatsupport/plat_include/exynos4/platsupport/plat/spi.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -/* IRQS */ -#define EXYNOS_SPI0_IRQ 98 -#define EXYNOS_SPI1_IRQ 99 -#define EXYNOS_SPI2_IRQ 100 -#define EXYNOS_SPI0_ISP_IRQ 122 -#define EXYNOS_SPI1_ISP_IRQ 127 - -/* Physical addresses */ -#define EXYNOS_SPI0_PADDR 0x13920000 -#define EXYNOS_SPI1_PADDR 0x13930000 -#define EXYNOS_SPI2_PADDR 0x13940000 -#define EXYNOS_SPI0_ISP_PADDR 0x121A0000 -#define EXYNOS_SPI1_ISP_PADDR 0x121B0000 - -/* Sizes */ -#define EXYNOS_SPIX_SIZE 0x1000 -#define EXYNOS_SPI0_SIZE EXYNOS_SPIX_SIZE -#define EXYNOS_SPI1_SIZE EXYNOS_SPIX_SIZE -#define EXYNOS_SPI2_SIZE EXYNOS_SPIX_SIZE -#define EXYNOS_SPI0_ISP_SIZE EXYNOS_SPIX_SIZE -#define EXYNOS_SPI1_ISP_SIZE EXYNOS_SPIX_SIZE - -enum spi_id { - SPI0, - SPI1, - SPI2, - NSPI -}; - -int exynos_spi_init(enum spi_id id, void* base, - mux_sys_t* mux_sys, clock_sys_t* clock_sys, - spi_bus_t** spi_bus); - diff --git a/libplatsupport/plat_include/exynos4/platsupport/plat/src.h b/libplatsupport/plat_include/exynos4/platsupport/plat/src.h deleted file mode 100644 index aff813843..000000000 --- a/libplatsupport/plat_include/exynos4/platsupport/plat/src.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -/* IRQS */ - -/* Physical addresses */ -#define EXYNOS_SYSREG_PADDR 0x10010000 -#define EXYNOS_PMU_PADDR 0x10020000 - -/* Sizes */ -#define EXYNOS_SYSREG_SIZE 0x1000 -#define EXYNOS_PMU_SIZE 0x5000 - -enum src_id { - SRC1, - /* ---- */ - NSRC, - SRC_DEFAULT = SRC1 -}; - -enum src_rst_id { - SRCRST_SW_RST, - SRCRST_USBPHY_EN, - /* ---- */ - NSRCRST -}; - diff --git a/libplatsupport/plat_include/exynos4/platsupport/plat/tmu.h b/libplatsupport/plat_include/exynos4/platsupport/plat/tmu.h deleted file mode 100644 index 5ae5c771a..000000000 --- a/libplatsupport/plat_include/exynos4/platsupport/plat/tmu.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -#include - -#include - -#define TMU_IRQ0 COMBINER_IRQ(2, 4) -#define TMU_IRQ1 COMBINER_IRQ(3, 4) - -#define EXYNOS_TMU_PADDR 0x100C0000 -#define EXYNOS_TMU_SIZE 0x1000 - -enum tmu_id { - TMU_CORE0, -// TMU_CORE1, -// TMU_CORE2, -// TMU_CORE3, -// TMU_CORE4, - NTMU, - /* Aliases */ - TMU_CORE = TMU_CORE0 -}; - -/** - * Initialise a Thermal Management Unit - * @param[in] id The ID of the TMU that is to be initialised - * @param[in] vaddr The virtual address of the TMU - * @param[out] tmu A TMU structure to populate - * @return 0 on success - */ -int exynos4_tmu_init(enum tmu_id id, void* vaddr, tmu_t* tmu); - diff --git a/libplatsupport/plat_include/exynos5/platsupport/plat/dma330.h b/libplatsupport/plat_include/exynos5/platsupport/plat/dma330.h index e8e0f46c3..c37df3d01 100644 --- a/libplatsupport/plat_include/exynos5/platsupport/plat/dma330.h +++ b/libplatsupport/plat_include/exynos5/platsupport/plat/dma330.h @@ -29,9 +29,6 @@ enum dma330_id { PL330_MDMA0, -#if defined CONFIG_PLAT_EXYNOS5250 - PL330_MDMA1, -#endif PL330_PDMA0, PL330_PDMA1, NPL330 @@ -39,36 +36,24 @@ enum dma330_id { static const uint32_t dma330_paddr[] = { [PL330_MDMA0] = PL330_MDMA0_PADDR, -#if defined CONFIG_PLAT_EXYNOS5250 - [PL330_MDMA1] = PL330_MDMA1_PADDR, -#endif [PL330_PDMA0] = PL330_PDMA0_PADDR, [PL330_PDMA1] = PL330_PDMA1_PADDR }; static const uint32_t dma330_size[] = { [PL330_MDMA0] = PL330_MDMA0_SIZE, -#if defined CONFIG_PLAT_EXYNOS5250 - [PL330_MDMA1] = PL330_MDMA1_SIZE, -#endif [PL330_PDMA0] = PL330_PDMA0_SIZE, [PL330_PDMA1] = PL330_PDMA1_SIZE }; static const int dma330_irq[] = { [PL330_MDMA0] = PL330_MDMA0_IRQ, -#if defined CONFIG_PLAT_EXYNOS5250 - [PL330_MDMA1] = PL330_MDMA1_IRQ, -#endif [PL330_PDMA0] = PL330_PDMA0_IRQ, [PL330_PDMA1] = PL330_PDMA1_IRQ }; static const int dma330_abort_irq[] = { [PL330_MDMA0] = PL330_MDMA0_ABORT_IRQ, -#if defined CONFIG_PLAT_EXYNOS5250 - [PL330_MDMA1] = PL330_MDMA1_ABORT_IRQ, -#endif [PL330_PDMA0] = -1, [PL330_PDMA1] = -1 }; diff --git a/libplatsupport/plat_include/exynos5/platsupport/plat/mux.h b/libplatsupport/plat_include/exynos5/platsupport/plat/mux.h index 016217f05..0d4479036 100644 --- a/libplatsupport/plat_include/exynos5/platsupport/plat/mux.h +++ b/libplatsupport/plat_include/exynos5/platsupport/plat/mux.h @@ -8,13 +8,7 @@ #include #include -#if defined(CONFIG_PLAT_EXYNOS5250) -/* These are for the arndale */ -#define EXYNOS_GPIOLEFT_PADDR 0x11400000 -#define EXYNOS_GPIORIGHT_PADDR 0x13400000 -#define EXYNOS_GPIOC2C_PADDR 0x10D10000 -#define EXYNOS_GPIOAUDIO_PADDR 0x03860000 -#elif defined(CONFIG_PLAT_EXYNOS54XX) +#if defined(CONFIG_PLAT_EXYNOS54XX) /* These are for Odroid-XU and XU3 */ #define EXYNOS_GPIOLEFT_PADDR 0x13400000 #define EXYNOS_GPIORIGHT_PADDR 0x14000000 @@ -73,9 +67,9 @@ enum mux_feature { * subsystem data. * @return 0 on success */ -int exynos_mux_init(void* gpioleft, - void* gpioright, - void* gpioc2c, - void* gpioaudio, - mux_sys_t* mux); +int exynos_mux_init(void *gpioleft, + void *gpioright, + void *gpioc2c, + void *gpioaudio, + mux_sys_t *mux); diff --git a/libplatsupport/plat_include/exynos5/platsupport/plat/serial.h b/libplatsupport/plat_include/exynos5/platsupport/plat/serial.h index 274d6711a..9dea703b9 100644 --- a/libplatsupport/plat_include/exynos5/platsupport/plat/serial.h +++ b/libplatsupport/plat_include/exynos5/platsupport/plat/serial.h @@ -19,9 +19,7 @@ #define EXYNOS_UART2_IRQ 85 #define EXYNOS_UART3_IRQ 86 -#if defined(CONFIG_PLAT_EXYNOS5250) -#define UART_DEFAULT_FIN 100000000 -#elif defined(CONFIG_PLAT_EXYNOS5410) +#if defined(CONFIG_PLAT_EXYNOS5410) #define UART_DEFAULT_FIN 64000000 #elif defined(CONFIG_PLAT_EXYNOS5422) #define UART_DEFAULT_FIN 53200000 diff --git a/libplatsupport/plat_include/exynos5/platsupport/plat/tmu.h b/libplatsupport/plat_include/exynos5/platsupport/plat/tmu.h index 99dd13ff9..d880d6717 100644 --- a/libplatsupport/plat_include/exynos5/platsupport/plat/tmu.h +++ b/libplatsupport/plat_include/exynos5/platsupport/plat/tmu.h @@ -40,5 +40,5 @@ enum tmu_id { * @param[out] tmu A TMU structure to populate * @return 0 on success */ -int exynos4_tmu_init(enum tmu_id id, void* vaddr, tmu_t* tmu); +int exynos5_tmu_init(enum tmu_id id, void *vaddr, tmu_t *tmu); diff --git a/libplatsupport/plat_include/hikey/platsupport/plat/clock.h b/libplatsupport/plat_include/hikey/platsupport/plat/clock.h deleted file mode 100644 index 072a13ddd..000000000 --- a/libplatsupport/plat_include/hikey/platsupport/plat/clock.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -enum clk_id { - CLK_MASTER, - /* ----- */ - NCLOCKS, - /* Custom clock */ - CLK_CUSTOM, -}; - -enum clock_gate { - NCLKGATES -}; - diff --git a/libplatsupport/plat_include/hikey/platsupport/plat/dmt.h b/libplatsupport/plat_include/hikey/platsupport/plat/dmt.h deleted file mode 100644 index a661f3fc1..000000000 --- a/libplatsupport/plat_include/hikey/platsupport/plat/dmt.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ -#pragma once - -#include -#include - -#define DMT_PATH "/soc/timer@f8008000" - -#define DMT_REG_CHOICE 0 -#define DMT_IRQ_CHOICE 0 - -static UNUSED timer_properties_t dmtimer_props = { - .upcounter = false, - .timeouts = true, - .absolute_timeouts = false, - .relative_timeouts = true, - .periodic_timeouts = true, - .bit_width = 32, - .irqs = 1 -}; - -typedef volatile struct dmt_regs { - uint32_t load; - uint32_t value; - uint32_t control; - uint32_t intclr; - uint32_t ris; - uint32_t mis; - uint32_t bgload; -} dmt_regs_t; - -typedef struct { - /* set in init */ - ps_io_ops_t ops; - ltimer_callback_fn_t user_cb_fn; - void *user_cb_token; - ltimer_event_t user_cb_event; /* what are we being used for? */ - - /* set in fdt helper */ - volatile dmt_regs_t *dmt_map; - void *dmt_map_base; - pmem_region_t pmem; - irq_id_t irq_id; - - /* set in setup */ - uint32_t time_h; -} dmt_t; - -typedef struct { - const char *fdt_path; - ltimer_callback_fn_t user_cb_fn; - void *user_cb_token; - ltimer_event_t user_cb_event; -} dmt_config_t; - -int dmt_init(dmt_t *dmt, ps_io_ops_t ops, dmt_config_t config); -int dmt_init_secondary(dmt_t *dmt, dmt_t *dmtp, ps_io_ops_t ops, dmt_config_t config); -/* convert between dmt ticks and ns */ -uint64_t dmt_ticks_to_ns(uint64_t ticks); -/* return true if an overflow irq is pending */ -bool dmt_is_irq_pending(dmt_t *dmt); -int dmt_set_timeout_ticks(dmt_t *dmt, uint32_t ticks, bool periodic, bool irqs); -/* set a timeout in nano seconds */ -int dmt_set_timeout(dmt_t *dmt, uint64_t ns, bool periodic, bool irqs); -int dmt_start(dmt_t *dmt); -int dmt_stop(dmt_t *dmt); -uint64_t dmt_get_time(dmt_t *dmt); -uint64_t dmt_get_ticks(dmt_t *dmt); -void dmt_destroy(dmt_t *dmt); diff --git a/libplatsupport/plat_include/hikey/platsupport/plat/i2c.h b/libplatsupport/plat_include/hikey/platsupport/plat/i2c.h deleted file mode 100644 index 40efe17b5..000000000 --- a/libplatsupport/plat_include/hikey/platsupport/plat/i2c.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -enum i2c_id { - NI2C -}; - diff --git a/libplatsupport/plat_include/hikey/platsupport/plat/rtc.h b/libplatsupport/plat_include/hikey/platsupport/plat/rtc.h deleted file mode 100644 index e1f59e1a0..000000000 --- a/libplatsupport/plat_include/hikey/platsupport/plat/rtc.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ -#pragma once - -#include - -#define RTC0_PADDR 0xF8003000 -#define RTC1_PADDR 0xF8004000 - -#define RTC0_INTERRUPT 44 -#define RTC1_INTERRUPT 40 - -typedef enum rtc_id { - RTC0, - RTC1, - NUM_RTCS = 2, -} rtc_id_t; - -static inline void *rtc_get_paddr(rtc_id_t id) { - switch (id) { - case RTC0: - return (void *) RTC0_PADDR; - case RTC1: - return (void *) RTC1_PADDR; - default: - return NULL; - } -} - -static inline long rtc_get_irq(rtc_id_t id) { - switch (id) { - case RTC0: - return RTC0_INTERRUPT; - case RTC1: - return RTC1_INTERRUPT; - default: - return 0; - } -} - -typedef struct { - int timer_id; - void *vaddr; - uint32_t irq; -} rtc_t; - -typedef struct { - void *vaddr; - rtc_id_t id; -} rtc_config_t; - -static UNUSED timer_properties_t rtc_props = { - .upcounter = true, - .timeouts = false, - .bit_width = 32, - .irqs = 0 -}; - -int rtc_stop(rtc_t *rtc); -int rtc_start(rtc_t *rtc); -uint32_t rtc_get_time(rtc_t *rtc); -int rtc_init(rtc_t *rtc, rtc_config_t config); diff --git a/libplatsupport/plat_include/hikey/platsupport/plat/serial.h b/libplatsupport/plat_include/hikey/platsupport/plat/serial.h deleted file mode 100644 index b2224935e..000000000 --- a/libplatsupport/plat_include/hikey/platsupport/plat/serial.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -#define UART0_PADDR 0xF8015000 -#define UART1_PADDR 0xF7111000 -#define UART2_PADDR 0xF7112000 -#define UART3_PADDR 0xF7113000 -#define UART4_PADDR 0xF7114000 - -#define UART0_IRQ 68 -#define UART1_IRQ 69 -#define UART2_IRQ 70 -#define UART3_IRQ 71 -#define UART4_IRQ 72 - -enum chardev_id { - DM_UART0, - DM_UART1, - DM_UART2, - DM_UART3, - DM_UART4, - /* Aliases */ - PS_SERIAL0 = DM_UART0, - PS_SERIAL1 = DM_UART1, - PS_SERIAL2 = DM_UART2, - PS_SERIAL3 = DM_UART3, - PS_SERIAL4 = DM_UART4, - /* defaults */ - PS_SERIAL_DEFAULT = DM_UART0 -}; - -#define DEFAULT_SERIAL_PADDR UART0_PADDR -#define DEFAULT_SERIAL_INTERRUPT UART0_IRQ diff --git a/libplatsupport/src/arch/arm/delay.c b/libplatsupport/src/arch/arm/delay.c index b1cf20113..5afb60a40 100644 --- a/libplatsupport/src/arch/arm/delay.c +++ b/libplatsupport/src/arch/arm/delay.c @@ -11,11 +11,7 @@ #include #include -#if defined(CONFIG_PLAT_EXYNOS5250) -#define DEFAULT_CPUFREQ 1000000000UL -#elif defined(CONFIG_PLAT_EXYNOS5410) -#define DEFAULT_CPUFREQ 1000000000UL -#elif defined(CONFIG_PLAT_EXYNOS4) +#if defined(CONFIG_PLAT_EXYNOS5410) #define DEFAULT_CPUFREQ 1000000000UL #elif defined(CONFIG_PLAT_IMX6) #define DEFAULT_CPUFREQ 792000000UL diff --git a/libplatsupport/src/arch/arm/i2c_bitbang.c b/libplatsupport/src/arch/arm/i2c_bitbang.c index 9d2e7d1fa..c25e6ab75 100644 --- a/libplatsupport/src/arch/arm/i2c_bitbang.c +++ b/libplatsupport/src/arch/arm/i2c_bitbang.c @@ -8,7 +8,7 @@ #include /* To extend support, provide platform specific i2c.h and gpio.h and delay.c */ -#if defined(CONFIG_PLAT_EXYNOS5) || defined(CONFIG_PLAT_EXYNOS4) || defined(CONFIG_PLAT_IMX6) +#if defined(CONFIG_PLAT_EXYNOS5) || defined(CONFIG_PLAT_IMX6) #include #include @@ -16,128 +16,118 @@ #define DEFAULT_SPEED 100*1000 -static inline struct i2c_bb* -i2c_bus_get_priv(struct i2c_bus* i2c_bus) { - return (struct i2c_bb*)i2c_bus->priv; +static inline struct i2c_bb *i2c_bus_get_priv(struct i2c_bus *i2c_bus) +{ + return (struct i2c_bb *)i2c_bus->priv; } -static inline void -_hold(struct i2c_bb* d) +static inline void _hold(struct i2c_bb *d) { ps_udelay(1000000 / d->speed + 1); } -static inline void -pin_l(struct i2c_bb* d, int gpio) +static inline void pin_l(struct i2c_bb *d, int gpio) { gpio_t g; gpio_new(d->gpio_sys, gpio, GPIO_DIR_OUT, &g); gpio_clr(&g); } -static inline int -pin_r(struct i2c_bb* d, int gpio) +static inline int pin_r(struct i2c_bb *d, int gpio) { gpio_t g; gpio_new(d->gpio_sys, gpio, GPIO_DIR_IN, &g); return gpio_get(&g); } -static inline void -pin_h(struct i2c_bb* d, int gpio) +static inline void pin_h(struct i2c_bb *d, int gpio) { pin_r(d, gpio); } -static inline int sda_r (struct i2c_bb* d) +static inline int sda_r(struct i2c_bb *d) { return pin_r(d, d->sda); } -static inline void sda_l (struct i2c_bb* d) +static inline void sda_l(struct i2c_bb *d) { pin_l(d, d->sda); } -static inline void sda_h (struct i2c_bb* d) +static inline void sda_h(struct i2c_bb *d) { pin_h(d, d->sda); } -static inline void scl_l (struct i2c_bb* d) +static inline void scl_l(struct i2c_bb *d) { pin_l(d, d->scl); } -static inline void scl_h (struct i2c_bb* d) +static inline void scl_h(struct i2c_bb *d) { while (!pin_r(d, d->scl)); } -static inline void -clk(struct i2c_bb* d) +static inline void clk(struct i2c_bb *d) { - _hold (d); - scl_h (d); - _hold (d); - scl_l (d); + _hold(d); + scl_h(d); + _hold(d); + scl_l(d); } -static inline void -i2c_bb_start(struct i2c_bb* d) +static inline void i2c_bb_start(struct i2c_bb *d) { /* init */ while (!sda_r(d)); - _hold (d); + _hold(d); /* Start */ - sda_l (d); - _hold (d); - scl_l (d); + sda_l(d); + _hold(d); + scl_l(d); } -static inline void -i2c_bb_stop(struct i2c_bb* d) +static inline void i2c_bb_stop(struct i2c_bb *d) { - sda_l (d); - _hold (d); - scl_h (d); + sda_l(d); + _hold(d); + scl_h(d); ps_udelay(1000); while (!sda_r(d)); - _hold (d); + _hold(d); } -static inline void -i2c_bb_sendbit(struct i2c_bb* d, int bit) +static inline void i2c_bb_sendbit(struct i2c_bb *d, int bit) { /* Setup bit */ if (bit) { - sda_h (d); + sda_h(d); } else { - sda_l (d); + sda_l(d); } - _hold (d); + _hold(d); /* Raise clock, wait for clock stretching */ - scl_h (d); - _hold (d); + scl_h(d); + _hold(d); /* Lower clock */ - scl_l (d); + scl_l(d); } -static inline int -i2c_bb_readbit(struct i2c_bb* d) +static inline int i2c_bb_readbit(struct i2c_bb *d) { int bit; /* Release SDA */ - sda_r (d); - _hold (d); + sda_r(d); + _hold(d); /* Raise clock, wait for clock stretching */ - scl_h (d); + scl_h(d); /* Data now read to be read */ bit = sda_r(d); - _hold (d); - scl_l (d); + _hold(d); + scl_l(d); return bit; } -static int -i2c_bb_sendbyte(struct i2c_bb* d, char b) +static int i2c_bb_sendbyte(struct i2c_bb *d, char b) { int i; unsigned char mask = 0x80; @@ -149,8 +139,7 @@ i2c_bb_sendbyte(struct i2c_bb* d, char b) return i2c_bb_readbit(d); } -static int -i2c_bb_readbyte(struct i2c_bb* d, int send_nak) +static int i2c_bb_readbyte(struct i2c_bb *d, int send_nak) { int i; char data = 0; @@ -162,41 +151,37 @@ i2c_bb_readbyte(struct i2c_bb* d, int send_nak) return data; } -static int -i2c_bb_read(i2c_bus_t* bus, void* buf, size_t size, - UNUSED bool end_with_repeat_start, - i2c_callback_fn cb, void* token) +static int i2c_bb_read(i2c_bus_t *bus, void *buf, size_t size, + UNUSED bool end_with_repeat_start, + i2c_callback_fn cb, void *token) { assert(!"Not implemented\n"); return -1; } -static int -i2c_bb_write(i2c_bus_t* bus, const void* buf, size_t size, - UNUSED bool end_with_repeat_start, - i2c_callback_fn cb, void* token) +static int i2c_bb_write(i2c_bus_t *bus, const void *buf, size_t size, + UNUSED bool end_with_repeat_start, + i2c_callback_fn cb, void *token) { assert(!"Not implemented\n"); return -1; } -static int -i2c_bb_master_stop(i2c_bus_t* bus) +static int i2c_bb_master_stop(i2c_bus_t *bus) { assert(!"Not implemented\n"); return -1; } -static int -i2c_bb_start_read(i2c_slave_t *sl, - void* vdata, size_t size, - UNUSED bool end_with_repeat_start, - i2c_callback_fn cb, void* token) +static int i2c_bb_start_read(i2c_slave_t *sl, + void *vdata, size_t size, + UNUSED bool end_with_repeat_start, + i2c_callback_fn cb, void *token) { - struct i2c_bb* d; + struct i2c_bb *d; int nak; int count; - char* data = (char*)vdata; + char *data = (char *)vdata; assert(sl != NULL && sl->bus != NULL); @@ -220,16 +205,15 @@ i2c_bb_start_read(i2c_slave_t *sl, return count; } -static int -i2c_bb_start_write(i2c_slave_t *sl, - const void* vdata, size_t size, - UNUSED bool end_with_repeat_start, - i2c_callback_fn cb, void* token) +static int i2c_bb_start_write(i2c_slave_t *sl, + const void *vdata, size_t size, + UNUSED bool end_with_repeat_start, + i2c_callback_fn cb, void *token) { - struct i2c_bb* d; + struct i2c_bb *d; int nak; int count; - const char* data = (const char*)vdata; + const char *data = (const char *)vdata; assert(sl != NULL && sl->bus != NULL); @@ -252,28 +236,25 @@ i2c_bb_start_write(i2c_slave_t *sl, return count; } -static void -i2c_bb_handle_irq(i2c_bus_t* i2c_bus) +static void i2c_bb_handle_irq(i2c_bus_t *i2c_bus) { - struct i2c_bb* d; + struct i2c_bb *d; /* BB is a blocking call, but in case someone tried to poll, we ignore the call */ d = i2c_bus_get_priv(i2c_bus); (void)d; } -static int -i2c_bb_set_self_slave_address(i2c_bus_t *i2c_bus, int addr) +static int i2c_bb_set_self_slave_address(i2c_bus_t *i2c_bus, int addr) { - struct i2c_bb* d; + struct i2c_bb *d; d = i2c_bus_get_priv(i2c_bus); (void)d; assert(!"Not implemented"); return -1; } -static void -i2c_bb_register_slave_event_handler(i2c_bus_t *bus, - i2c_aas_callback_fn aas_cb, void* aas_token) +static void i2c_bb_register_slave_event_handler(i2c_bus_t *bus, + i2c_aas_callback_fn aas_cb, void *aas_token) { assert(bus != NULL); bus->aas_cb = aas_cb; @@ -287,10 +268,9 @@ static const uint32_t i2c_speed_freqs[] = { [I2C_SLAVE_SPEED_HIGHSPEED] = 3400000 }; -static long -i2c_bb_set_speed(i2c_bus_t* i2c_bus, enum i2c_slave_speed speed) +static long i2c_bb_set_speed(i2c_bus_t *i2c_bus, enum i2c_slave_speed speed) { - struct i2c_bb* d; + struct i2c_bb *d; d = i2c_bus_get_priv(i2c_bus); if (speed < I2C_SLAVE_SPEED_STANDARD || speed > I2C_SLAVE_SPEED_HIGHSPEED) { @@ -302,12 +282,11 @@ i2c_bb_set_speed(i2c_bus_t* i2c_bus, enum i2c_slave_speed speed) return speed; } -static int -i2c_bb_slave_init(i2c_bus_t* i2c_bus, int address, - enum i2c_slave_address_size address_size, - enum i2c_slave_speed max_speed, - uint32_t flags, - i2c_slave_t* sl) +static int i2c_bb_slave_init(i2c_bus_t *i2c_bus, int address, + enum i2c_slave_address_size address_size, + enum i2c_slave_speed max_speed, + uint32_t flags, + i2c_slave_t *sl) { assert(sl != NULL); @@ -323,9 +302,8 @@ i2c_bb_slave_init(i2c_bus_t* i2c_bus, int address, return 0; } -int -i2c_bb_init(gpio_sys_t* gpio_sys, gpio_id_t scl, gpio_id_t sda, - struct i2c_bb* i2c_bb, struct i2c_bus* i2c) +int i2c_bb_init(gpio_sys_t *gpio_sys, gpio_id_t scl, gpio_id_t sda, + struct i2c_bb *i2c_bb, struct i2c_bus *i2c) { /* Initialise the BB structure */ i2c_bb->scl = scl; @@ -341,7 +319,7 @@ i2c_bb_init(gpio_sys_t* gpio_sys, gpio_id_t scl, gpio_id_t sda, i2c->register_slave_event_handler = i2c_bb_register_slave_event_handler; i2c->master_stop = i2c_bb_master_stop; i2c->handle_irq = i2c_bb_handle_irq; - i2c->priv = (void*)i2c_bb; + i2c->priv = (void *)i2c_bb; /* Done */ return 0; } diff --git a/libplatsupport/src/mach/exynos/i2c.c b/libplatsupport/src/mach/exynos/i2c.c index 825221beb..aa60aa7ed 100644 --- a/libplatsupport/src/mach/exynos/i2c.c +++ b/libplatsupport/src/mach/exynos/i2c.c @@ -16,35 +16,6 @@ *** SoC specifics *** *********************/ -#if defined(CONFIG_PLAT_EXYNOS4) -/* IRQS */ -#define EXYNOS_I2C0_IRQ 90 -#define EXYNOS_I2C1_IRQ 91 -#define EXYNOS_I2C2_IRQ 92 -#define EXYNOS_I2C3_IRQ 93 -#define EXYNOS_I2C4_IRQ 94 -#define EXYNOS_I2C5_IRQ 95 -#define EXYNOS_I2C6_IRQ 96 -#define EXYNOS_I2C7_IRQ 97 -#define EXYNOS_I2C8_IRQ 0 -#define EXYNOS_I2C9_IRQ 0 -#define EXYNOS_I2C10_IRQ 0 -#define EXYNOS_I2C11_IRQ 0 -/* Physical addresses */ -#define EXYNOS_I2C0_PADDR 0x13860000 -#define EXYNOS_I2C1_PADDR 0x13870000 -#define EXYNOS_I2C2_PADDR 0x13880000 -#define EXYNOS_I2C3_PADDR 0x13890000 -#define EXYNOS_I2C4_PADDR 0x138A0000 -#define EXYNOS_I2C5_PADDR 0x138B0000 -#define EXYNOS_I2C6_PADDR 0x138C0000 -#define EXYNOS_I2C7_PADDR 0x138D0000 -#define EXYNOS_I2C8_PADDR 0x138E0000 -#define EXYNOS_I2C9_PADDR 0xDEADBEEF -#define EXYNOS_I2C10_PADDR 0xDEADBEEF -#define EXYNOS_I2C11_PADDR 0xDEADBEEF - -#elif defined(CONFIG_PLAT_EXYNOS5) /* IRQS */ #define EXYNOS_I2C0_IRQ 88 #define EXYNOS_I2C1_IRQ 89 @@ -72,10 +43,6 @@ #define EXYNOS_I2C10_PADDR 0x13140000 #define EXYNOS_I2C11_PADDR 0x121D0000 -#else /* EXYNOS? */ -#error Unknown Exynos based platform -#endif /* EXYNOSX */ - /* Sizes */ #define EXYNOS_I2CX_SIZE 0x1000 #define EXYNOS_I2C0_SIZE EXYNOS_I2CX_SIZE @@ -140,11 +107,11 @@ struct exynos_i2c_regs { }; struct i2c_bus_priv { - volatile struct exynos_i2c_regs* regs; - const char* tx_buf; + volatile struct exynos_i2c_regs *regs; + const char *tx_buf; int tx_len; int tx_count; - char* rx_buf; + char *rx_buf; int rx_len; int rx_count; enum mux_feature mux; @@ -159,62 +126,50 @@ static struct i2c_bus_priv _i2c[NI2C] = { { .regs = NULL, .mux = MUX_I2C5 }, { .regs = NULL, .mux = MUX_I2C6 }, { .regs = NULL, .mux = MUX_I2C7 }, -#if defined(CONFIG_PLAT_EXYNOS4) -#elif defined(CONFIG_PLAT_EXYNOS5) { .regs = NULL, .mux = MUX_I2C8 }, { .regs = NULL, .mux = MUX_I2C9 }, { .regs = NULL, .mux = MUX_I2C10 }, { .regs = NULL, .mux = MUX_I2C11 } -#else /* EXYNOS? */ -#error Unknown Exynos based platform -#endif /* EXYNOSX */ }; -static inline struct i2c_bus_priv* -i2c_bus_get_priv(i2c_bus_t* i2c_bus) { - return (struct i2c_bus_priv*)i2c_bus->priv; +static inline struct i2c_bus_priv *i2c_bus_get_priv(i2c_bus_t *i2c_bus) +{ + return (struct i2c_bus_priv *)i2c_bus->priv; } -static inline int -irq_pending(struct i2c_bus_priv* dev) +static inline int irq_pending(struct i2c_bus_priv *dev) { return !!(dev->regs->control & I2CCON_IRQ_PEND); } -static inline void -clear_pending(struct i2c_bus_priv* dev) +static inline void clear_pending(struct i2c_bus_priv *dev) { uint32_t v = dev->regs->control; v &= ~(I2CCON_IRQ_PEND); dev->regs->control = v; } -static inline int -addressed_as_slave(struct i2c_bus_priv* dev) +static inline int addressed_as_slave(struct i2c_bus_priv *dev) { return !!(dev->regs->status & I2CSTAT_ADDR_SLAVE); } -static inline int -busy(struct i2c_bus_priv* dev) +static inline int busy(struct i2c_bus_priv *dev) { return !!(dev->regs->status & I2CSTAT_BUSY); } -static inline int -acked(struct i2c_bus_priv* dev) +static inline int acked(struct i2c_bus_priv *dev) { return !(dev->regs->status & I2CSTAT_ACK); } -static inline int -enabled(struct i2c_bus_priv* dev) +static inline int enabled(struct i2c_bus_priv *dev) { return !!(dev->regs->status & I2CSTAT_ENABLE); } -static void -master_txstart(struct i2c_bus_priv* dev, int slave) +static void master_txstart(struct i2c_bus_priv *dev, int slave) { dev->regs->control |= I2CCON_ACK_EN; /** Configure Master Tx mode **/ @@ -226,8 +181,7 @@ master_txstart(struct i2c_bus_priv* dev, int slave) dev->regs->status |= I2CSTAT_BUSY; } -static void -master_rxstart(struct i2c_bus_priv* dev, int slave) +static void master_rxstart(struct i2c_bus_priv *dev, int slave) { dev->regs->control |= I2CCON_ACK_EN; /** Configure Master Rx mode **/ @@ -238,22 +192,20 @@ master_rxstart(struct i2c_bus_priv* dev, int slave) dev->regs->status |= I2CSTAT_BUSY; } -static void -slave_init(struct i2c_bus_priv* dev, char addr) +static void slave_init(struct i2c_bus_priv *dev, char addr) { dev->regs->address = addr; /** Configure Master Rx mode **/ dev->regs->status = I2CSTAT_ENABLE | I2CSTAT_MODE_SRX; } -int -exynos_i2c_read(i2c_bus_t* i2c_bus, void* vdata, size_t len, - UNUSED bool send_stop, - i2c_callback_fn cb, void* token) +int exynos_i2c_read(i2c_bus_t *i2c_bus, void *vdata, size_t len, + UNUSED bool send_stop, + i2c_callback_fn cb, void *token) { - struct i2c_bus_priv* dev = i2c_bus_get_priv(i2c_bus); + struct i2c_bus_priv *dev = i2c_bus_get_priv(i2c_bus); - dev->rx_buf = (char*)vdata; + dev->rx_buf = (char *)vdata; dev->rx_len = len; dev->rx_count = 0; i2c_bus->cb = cb; @@ -275,14 +227,13 @@ exynos_i2c_read(i2c_bus_t* i2c_bus, void* vdata, size_t len, } } -static int -exynos_i2c_write(i2c_bus_t* i2c_bus, const void* vdata, size_t len, - UNUSED bool send_stop, - i2c_callback_fn cb, void* token) +static int exynos_i2c_write(i2c_bus_t *i2c_bus, const void *vdata, size_t len, + UNUSED bool send_stop, + i2c_callback_fn cb, void *token) { - struct i2c_bus_priv* dev = i2c_bus_get_priv(i2c_bus); + struct i2c_bus_priv *dev = i2c_bus_get_priv(i2c_bus); - dev->tx_buf = (char*)vdata; + dev->tx_buf = (char *)vdata; dev->tx_len = len; dev->tx_count = 0; i2c_bus->cb = cb; @@ -303,20 +254,18 @@ exynos_i2c_write(i2c_bus_t* i2c_bus, const void* vdata, size_t len, } } -static int -exynos_i2c_master_stop(i2c_bus_t* i2c_bus) +static int exynos_i2c_master_stop(i2c_bus_t *i2c_bus) { assert(!"Not implemented"); return -1; } /* Exynos4 manual Figure 14-6 p14-9 */ -static int -exynos_i2c_start_read(i2c_slave_t* sl, void* vdata, size_t len, - UNUSED bool end_with_repeat_start, - i2c_callback_fn cb, void* token) +static int exynos_i2c_start_read(i2c_slave_t *sl, void *vdata, size_t len, + UNUSED bool end_with_repeat_start, + i2c_callback_fn cb, void *token) { - struct i2c_bus_priv* dev; + struct i2c_bus_priv *dev; assert(sl != NULL && sl->bus != NULL); @@ -325,7 +274,7 @@ exynos_i2c_start_read(i2c_slave_t* sl, void* vdata, size_t len, master_rxstart(dev, sl->address); /* Setup the RX descriptor */ - dev->rx_buf = (char*)vdata; + dev->rx_buf = (char *)vdata; dev->rx_len = len; dev->rx_count = -1; sl->bus->cb = cb; @@ -344,12 +293,11 @@ exynos_i2c_start_read(i2c_slave_t* sl, void* vdata, size_t len, } /* Exynos4 manual Figure 14-6 p14-8 */ -static int -exynos_i2c_start_write(i2c_slave_t* sl, const void* vdata, size_t len, - UNUSED bool end_with_repeat_start, - i2c_callback_fn cb, void* token) +static int exynos_i2c_start_write(i2c_slave_t *sl, const void *vdata, size_t len, + UNUSED bool end_with_repeat_start, + i2c_callback_fn cb, void *token) { - struct i2c_bus_priv* dev; + struct i2c_bus_priv *dev; assert(sl != NULL && sl->bus != NULL); @@ -359,7 +307,7 @@ exynos_i2c_start_write(i2c_slave_t* sl, const void* vdata, size_t len, dev->tx_count = -1; dev->tx_len = len; - dev->tx_buf = (const char*)vdata; + dev->tx_buf = (const char *)vdata; sl->bus->cb = cb; sl->bus->token = token; @@ -374,8 +322,7 @@ exynos_i2c_start_write(i2c_slave_t* sl, const void* vdata, size_t len, return dev->tx_count; } -static void -exynos_i2c_send_stop(i2c_bus_t* i2c_bus, enum i2c_stat status) +static void exynos_i2c_send_stop(i2c_bus_t *i2c_bus, enum i2c_stat status) { struct i2c_bus_priv *dev = i2c_bus_get_priv(i2c_bus); dev->regs->status &= ~(I2CSTAT_BUSY); @@ -385,10 +332,9 @@ exynos_i2c_send_stop(i2c_bus_t* i2c_bus, enum i2c_stat status) } } -static enum i2c_mode -exynos_i2c_probe_aas(i2c_bus_t* i2c_bus) +static enum i2c_mode exynos_i2c_probe_aas(i2c_bus_t *i2c_bus) { - struct i2c_bus_priv* dev; + struct i2c_bus_priv *dev; enum i2c_mode mode = I2CMODE_IDLE; dev = i2c_bus_get_priv(i2c_bus); @@ -425,10 +371,9 @@ exynos_i2c_probe_aas(i2c_bus_t* i2c_bus) return mode; } -static void -exynos_i2c_handle_irq(i2c_bus_t* i2c_bus) +static void exynos_i2c_handle_irq(i2c_bus_t *i2c_bus) { - struct i2c_bus_priv* dev; + struct i2c_bus_priv *dev; uint32_t v; dev = i2c_bus_get_priv(i2c_bus); @@ -543,38 +488,34 @@ exynos_i2c_handle_irq(i2c_bus_t* i2c_bus) clear_pending(dev); } -static long -exynos_i2c_set_speed(i2c_bus_t* i2c_bus, UNUSED enum i2c_slave_speed speed) +static long exynos_i2c_set_speed(i2c_bus_t *i2c_bus, UNUSED enum i2c_slave_speed speed) { ZF_LOGF("Not implemented"); return -1; } -static int -exynos_i2c_set_self_slave_address(i2c_bus_t* i2c_bus, int addr) +static int exynos_i2c_set_self_slave_address(i2c_bus_t *i2c_bus, int addr) { - struct i2c_bus_priv* dev; + struct i2c_bus_priv *dev; dev = i2c_bus_get_priv(i2c_bus); slave_init(dev, addr); dev->regs->line_control = BIT(2) | 0x3 ; return 0; } -static void -exynos_i2c_register_slave_event_handler(i2c_bus_t *bus, - i2c_aas_callback_fn cb, void *token) +static void exynos_i2c_register_slave_event_handler(i2c_bus_t *bus, + i2c_aas_callback_fn cb, void *token) { assert(bus != NULL); bus->aas_cb = cb; bus->aas_token = token; } -static int -exynos_i2c_slave_init(i2c_bus_t* i2c_bus, int address, - enum i2c_slave_address_size address_size, - enum i2c_slave_speed max_speed, - uint32_t flags, - i2c_slave_t* sl) +static int exynos_i2c_slave_init(i2c_bus_t *i2c_bus, int address, + enum i2c_slave_address_size address_size, + enum i2c_slave_speed max_speed, + uint32_t flags, + i2c_slave_t *sl) { assert(sl != NULL); @@ -594,8 +535,7 @@ exynos_i2c_slave_init(i2c_bus_t* i2c_bus, int address, return 0; } -static int -i2c_init_common(mux_sys_t* mux, i2c_bus_t* i2c, struct i2c_bus_priv* dev) +static int i2c_init_common(mux_sys_t *mux, i2c_bus_t *i2c, struct i2c_bus_priv *dev) { /* Check that our memory was mapped */ if (dev->regs == NULL) { @@ -623,7 +563,7 @@ i2c_init_common(mux_sys_t* mux, i2c_bus_t* i2c, struct i2c_bus_priv* dev) i2c->probe_aas = exynos_i2c_probe_aas; i2c->master_stop = exynos_i2c_master_stop; i2c->handle_irq = exynos_i2c_handle_irq; - i2c->priv = (void*)dev; + i2c->priv = (void *)dev; i2c->cb = NULL; i2c->token = NULL; @@ -632,20 +572,18 @@ i2c_init_common(mux_sys_t* mux, i2c_bus_t* i2c, struct i2c_bus_priv* dev) return 0; } -int -exynos_i2c_init(enum i2c_id id, void* base, mux_sys_t* mux, i2c_bus_t* i2c) +int exynos_i2c_init(enum i2c_id id, void *base, mux_sys_t *mux, i2c_bus_t *i2c) { - struct i2c_bus_priv* dev = _i2c + id; + struct i2c_bus_priv *dev = _i2c + id; ZF_LOGD("Mapping i2c %d", id); dev->regs = base; return i2c_init_common(mux, i2c, dev); } -int -i2c_init(enum i2c_id id, ps_io_ops_t* io_ops, i2c_bus_t* i2c) +int i2c_init(enum i2c_id id, ps_io_ops_t *io_ops, i2c_bus_t *i2c) { - struct i2c_bus_priv* dev = _i2c + id; - mux_sys_t* mux = &io_ops->mux_sys; + struct i2c_bus_priv *dev = _i2c + id; + mux_sys_t *mux = &io_ops->mux_sys; /* Map memory */ ZF_LOGD("Mapping i2c %d", id); switch (id) { @@ -673,8 +611,6 @@ i2c_init(enum i2c_id id, ps_io_ops_t* io_ops, i2c_bus_t* i2c) case I2C7: MAP_IF_NULL(io_ops, EXYNOS_I2C7, dev->regs); break; -#if defined(CONFIG_PLAT_EXYNOS4) -#elif defined(CONFIG_PLAT_EXYNOS5) case I2C8: MAP_IF_NULL(io_ops, EXYNOS_I2C8, dev->regs); break; @@ -687,9 +623,6 @@ i2c_init(enum i2c_id id, ps_io_ops_t* io_ops, i2c_bus_t* i2c) case I2C11: MAP_IF_NULL(io_ops, EXYNOS_I2C11, dev->regs); break; -#else /* EXYNOS? */ -#error Unknown Exynos based platform -#endif /* EXYNOSX */ default : return -1; } diff --git a/libplatsupport/src/mach/exynos/mux.c b/libplatsupport/src/mach/exynos/mux.c index 1c39dbcf9..63398db7c 100644 --- a/libplatsupport/src/mach/exynos/mux.c +++ b/libplatsupport/src/mach/exynos/mux.c @@ -270,11 +270,9 @@ static int gpio_get_extint_idx(gpio_t *gpio) return port - 1; } else if (portid == GPV4) { return port - 2; -#ifdef CONFIG_PLAT_EXYNOS5 /* GPC4 on EXYNOS5 is very special indeed. */ } else if (portid == GPC4) { return 13; -#endif /* General case */ } else if (port >= 0 && port <= PORTS_PER_BANK) { return port; diff --git a/libplatsupport/src/mach/exynos/pwm.c b/libplatsupport/src/mach/exynos/pwm.c index 2be2bb645..893468aab 100644 --- a/libplatsupport/src/mach/exynos/pwm.c +++ b/libplatsupport/src/mach/exynos/pwm.c @@ -16,11 +16,7 @@ #include #include -#if defined CONFIG_PLAT_EXYNOS5 #define CLK_FREQ 66ull /* MHz */ -#else -#define CLK_FREQ 100ull /* MHz */ -#endif #define T4_ENABLE BIT(20) #define T4_MANUALRELOAD BIT(21) diff --git a/libplatsupport/src/mach/exynos/spi.c b/libplatsupport/src/mach/exynos/spi.c index 7dda12bf1..9122d2bd7 100644 --- a/libplatsupport/src/mach/exynos/spi.c +++ b/libplatsupport/src/mach/exynos/spi.c @@ -117,7 +117,7 @@ enum spi_mode { }; struct spi_bus { - volatile struct spi_regs* regs; + volatile struct spi_regs *regs; enum mux_feature mux; enum clk_id clkid; int mode: 1; //0 -- Master, 1 -- Slave @@ -131,21 +131,18 @@ struct spi_bus { size_t txcnt, rxcnt; size_t txsize, rxsize; spi_callback_fn cb; - void* token; + void *token; }; static spi_bus_t _spi[NSPI] = { { .regs = NULL, .mux = MUX_SPI0, .clkid = CLK_SPI0 }, { .regs = NULL, .mux = MUX_SPI1, .clkid = CLK_SPI1 }, { .regs = NULL, .mux = MUX_SPI2, .clkid = CLK_SPI2 }, -#if defined(CONFIG_PLAT_EXYNOS5) { .regs = NULL, .mux = MUX_SPI0_ISP, .clkid = CLK_SPI0_ISP }, { .regs = NULL, .mux = MUX_SPI1_ISP, .clkid = CLK_SPI1_ISP }, -#endif /* EXYNOSX */ }; -static void -spi_reset(spi_bus_t *spi_bus) +static void spi_reset(spi_bus_t *spi_bus) { uint32_t v; @@ -170,8 +167,7 @@ spi_reset(spi_bus_t *spi_bus) spi_bus->regs->ch_cfg = v; } -static void -spi_config(spi_bus_t *spi_bus) +static void spi_config(spi_bus_t *spi_bus) { uint32_t v; @@ -228,8 +224,7 @@ spi_config(spi_bus_t *spi_bus) spi_bus->regs->cs_reg = v; } -static void -spi_cs(spi_bus_t* spi_bus, enum spi_cs_state state) +static void spi_cs(spi_bus_t *spi_bus, enum spi_cs_state state) { if (!spi_bus->cs_auto) { uint32_t v; @@ -243,8 +238,7 @@ spi_cs(spi_bus_t* spi_bus, enum spi_cs_state state) } } -static int -spi_init_common(spi_bus_t* spi_bus, mux_sys_t* mux_sys, clock_sys_t* clock_sys) +static int spi_init_common(spi_bus_t *spi_bus, mux_sys_t *mux_sys, clock_sys_t *clock_sys) { if (mux_sys && mux_sys_valid(mux_sys)) { mux_feature_enable(mux_sys, spi_bus->mux, MUX_DIR_NOT_A_GPIO); @@ -268,8 +262,7 @@ spi_init_common(spi_bus_t* spi_bus, mux_sys_t* mux_sys, clock_sys_t* clock_sys) return 0; } -int -transfer_data(spi_bus_t* spi_bus) +int transfer_data(spi_bus_t *spi_bus) { int rxfifo_cnt, txfifo_cnt, txfifo_space; uint32_t stat; @@ -333,18 +326,16 @@ transfer_data(spi_bus_t* spi_bus) return 1; } -void -spi_handle_irq(spi_bus_t* spi_bus) +void spi_handle_irq(spi_bus_t *spi_bus) { transfer_data(spi_bus); } -int -spi_xfer(spi_bus_t* spi_bus, const void* txdata, size_t txcnt, - void* rxdata, size_t rxcnt, spi_callback_fn cb, void* token) +int spi_xfer(spi_bus_t *spi_bus, const void *txdata, size_t txcnt, + void *rxdata, size_t rxcnt, spi_callback_fn cb, void *token) { - spi_bus->txbuf = (const char*)txdata; - spi_bus->rxbuf = (char*)rxdata; + spi_bus->txbuf = (const char *)txdata; + spi_bus->rxbuf = (char *)rxdata; spi_bus->rxsize = rxcnt; spi_bus->txsize = txcnt; spi_bus->rxcnt = 0; @@ -372,14 +363,12 @@ spi_xfer(spi_bus_t* spi_bus, const void* txdata, size_t txcnt, return spi_bus->rxcnt; } -long -spi_set_speed(spi_bus_t* spi_bus, long bps) +long spi_set_speed(spi_bus_t *spi_bus, long bps) { return 0; } -void -spi_prepare_transfer(spi_bus_t* spi_bus, const spi_slave_config_t* cfg) +void spi_prepare_transfer(spi_bus_t *spi_bus, const spi_slave_config_t *cfg) { if (spi_bus->clk && clk_get_freq(spi_bus->clk) != cfg->speed_hz) { clk_set_freq(spi_bus->clk, cfg->speed_hz); @@ -391,13 +380,12 @@ spi_prepare_transfer(spi_bus_t* spi_bus, const spi_slave_config_t* cfg) } } -int -exynos_spi_init(enum spi_id id, void* base, - mux_sys_t* mux_sys, clock_sys_t* clock_sys, - spi_bus_t** ret_spi_bus) +int exynos_spi_init(enum spi_id id, void *base, + mux_sys_t *mux_sys, clock_sys_t *clock_sys, + spi_bus_t **ret_spi_bus) { if (id >= 0 && id < NSPI) { - spi_bus_t* spi_bus = _spi + id; + spi_bus_t *spi_bus = _spi + id; *ret_spi_bus = spi_bus; spi_bus->regs = base; return spi_init_common(spi_bus, mux_sys, clock_sys); @@ -406,10 +394,9 @@ exynos_spi_init(enum spi_id id, void* base, } } -int -spi_init(enum spi_id id, ps_io_ops_t* io_ops, spi_bus_t** ret_spi_bus) +int spi_init(enum spi_id id, ps_io_ops_t *io_ops, spi_bus_t **ret_spi_bus) { - spi_bus_t* spi_bus = _spi + id; + spi_bus_t *spi_bus = _spi + id; *ret_spi_bus = spi_bus; /* Map memory */ DSPI("Mapping spi %d\n", id); @@ -423,14 +410,12 @@ spi_init(enum spi_id id, ps_io_ops_t* io_ops, spi_bus_t** ret_spi_bus) case SPI2: MAP_IF_NULL(io_ops, EXYNOS_SPI2, spi_bus->regs); break; -#ifdef CONFIG_PLAT_EXYNOS5 case SPI0_ISP: MAP_IF_NULL(io_ops, EXYNOS_SPI0_ISP, spi_bus->regs); break; case SPI1_ISP: MAP_IF_NULL(io_ops, EXYNOS_SPI1_ISP, spi_bus->regs); break; -#endif default: return -1; } diff --git a/libplatsupport/src/mach/exynos/tmu.c b/libplatsupport/src/mach/exynos/tmu.c index 96bce23e4..0704cda39 100644 --- a/libplatsupport/src/mach/exynos/tmu.c +++ b/libplatsupport/src/mach/exynos/tmu.c @@ -76,18 +76,16 @@ struct tmu_regs { }; typedef volatile struct tmu_regs tmu_regs_t; -static tmu_regs_t* _tmu_regs[NTMU]; +static tmu_regs_t *_tmu_regs[NTMU]; -static inline tmu_regs_t* -tmu_priv_get_regs(tmu_t* tmu) +static inline tmu_regs_t *tmu_priv_get_regs(tmu_t *tmu) { - return (tmu_regs_t*)tmu->priv; + return (tmu_regs_t *)tmu->priv; } -static int -do_exynos_tmu_init(enum tmu_id id, void* vaddr, tmu_t* tmu) +static int do_exynos_tmu_init(enum tmu_id id, void *vaddr, tmu_t *tmu) { - tmu_regs_t* regs; + tmu_regs_t *regs; uint32_t v; uint32_t te1, te2; @@ -106,7 +104,7 @@ do_exynos_tmu_init(enum tmu_id id, void* vaddr, tmu_t* tmu) } regs = _tmu_regs[id]; - tmu->priv = (void*)_tmu_regs[id]; + tmu->priv = (void *)_tmu_regs[id]; /* Reset alarms */ regs->int_enable = 0; @@ -141,20 +139,12 @@ do_exynos_tmu_init(enum tmu_id id, void* vaddr, tmu_t* tmu) return 0; } -int -exynos4_tmu_init(enum tmu_id id, void* vaddr, tmu_t* tmu) +int exynos5_tmu_init(enum tmu_id id, void *vaddr, tmu_t *tmu) { return do_exynos_tmu_init(id, vaddr, tmu); } -int -exynos5_tmu_init(enum tmu_id id, void* vaddr, tmu_t* tmu) -{ - return do_exynos_tmu_init(id, vaddr, tmu); -} - -int -exynos_tmu_init(enum tmu_id id, ps_io_ops_t* io_ops, tmu_t* tmu) +int exynos_tmu_init(enum tmu_id id, ps_io_ops_t *io_ops, tmu_t *tmu) { /* Check bounds */ if (id < 0 || id >= NTMU) { @@ -165,13 +155,12 @@ exynos_tmu_init(enum tmu_id id, ps_io_ops_t* io_ops, tmu_t* tmu) if (_tmu_regs[id] == NULL) { return -1; } - return do_exynos_tmu_init(id, (void*)_tmu_regs[id], tmu); + return do_exynos_tmu_init(id, (void *)_tmu_regs[id], tmu); } -int -exynos_tmu_get_temperature(tmu_t* tmu) +int exynos_tmu_get_temperature(tmu_t *tmu) { - tmu_regs_t* regs; + tmu_regs_t *regs; uint32_t currTemp; temperature_t temperature; regs = tmu_priv_get_regs(tmu); @@ -192,10 +181,9 @@ exynos_tmu_get_temperature(tmu_t* tmu) return temperature; } -void -exynos_tmu_handle_irq(tmu_t* tmu) +void exynos_tmu_handle_irq(tmu_t *tmu) { - tmu_regs_t* regs; + tmu_regs_t *regs; uint32_t sts; temperature_t t = exynos_tmu_get_temperature(tmu); regs = tmu_priv_get_regs(tmu); @@ -228,15 +216,14 @@ exynos_tmu_handle_irq(tmu_t* tmu) regs->int_clear = sts; } -int -exynos_tmu_set_alarms_rising(tmu_t* tmu, - temperature_t level0, - temperature_t level1, - temperature_t level2, - tmu_alarm_callback cb, - void* token) +int exynos_tmu_set_alarms_rising(tmu_t *tmu, + temperature_t level0, + temperature_t level1, + temperature_t level2, + tmu_alarm_callback cb, + void *token) { - tmu_regs_t* regs; + tmu_regs_t *regs; uint32_t threshold; uint32_t int_enable; @@ -261,15 +248,14 @@ exynos_tmu_set_alarms_rising(tmu_t* tmu, return 0; } -int -exynos_tmu_set_alarms_falling(tmu_t* tmu, - temperature_t level0, - temperature_t level1, - temperature_t level2, - tmu_alarm_callback cb, - void* token) +int exynos_tmu_set_alarms_falling(tmu_t *tmu, + temperature_t level0, + temperature_t level1, + temperature_t level2, + tmu_alarm_callback cb, + void *token) { - tmu_regs_t* regs; + tmu_regs_t *regs; uint32_t threshold; uint32_t int_enable; diff --git a/libplatsupport/src/plat/apq8064/chardev.c b/libplatsupport/src/plat/apq8064/chardev.c deleted file mode 100644 index 9698eb2cc..000000000 --- a/libplatsupport/src/plat/apq8064/chardev.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -/** - * Contains the definition for all character devices on this platform. - * Currently this is just a simple patch. - */ - -#include "../../chardev.h" -#include "../../common.h" -#include - -static const int gsbi3_uart_irqs[] = {GSBI3_UART_IRQ, -1}; -static const int gsbi4_uart_irqs[] = {GSBI4_UART_IRQ, -1}; -static const int gsbi5_uart_irqs[] = {GSBI5_UART_IRQ, -1}; -static const int gsbi6_uart_irqs[] = {GSBI6_UART_IRQ, -1}; -static const int gsbi7_uart_irqs[] = {GSBI7_UART_IRQ, -1}; - -#define GSBI_UART_DEFN(devid) { \ - .id = GSBI##devid##_UART, \ - .paddr = GSBI##devid##_UART_PADDR, \ - .size = BIT(12), \ - .irqs = gsbi##devid##_uart_irqs, \ - .init_fn = &uart_init \ -} - -static const struct dev_defn dev_defn[] = { - GSBI_UART_DEFN(3), - GSBI_UART_DEFN(4), - GSBI_UART_DEFN(5), - GSBI_UART_DEFN(6), - GSBI_UART_DEFN(7) -}; - -struct ps_chardevice* -ps_cdev_init(enum chardev_id id, const ps_io_ops_t* o, struct ps_chardevice* d) { - unsigned int i; - for (i = 0; i < ARRAY_SIZE(dev_defn); i++) { - if (dev_defn[i].id == id) { - return (dev_defn[i].init_fn(dev_defn + i, o, d)) ? NULL : d; - } - } - return NULL; -} diff --git a/libplatsupport/src/plat/apq8064/clock.c b/libplatsupport/src/plat/apq8064/clock.c deleted file mode 100644 index a6854c78d..000000000 --- a/libplatsupport/src/plat/apq8064/clock.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#include "../../arch/arm/clock.h" -#include "../../common.h" - -#define MXO_SRC_CLK_INV (1U << 12) -#define MXO_SRC_BRANCH_ENA (1U << 11) -#define PXO_SRC_CLK_INV (1U << 10) -#define PXO_SRC_BRANCH_ENA (1U << 9) -#define CLK_INV (1U << 5) -#define CLK_BRANCH_ENA (1U << 4) -#define SRC_SEL (1U << 0) -#define SRC_SEL_PXO (0U << 0) -#define SRC_SEL_MXO (1U << 0) -#define PPSS_TIMER0_CLK_CTL 0x0090258C -#define PPSS_TIMER1_CLK_CTL 0x00902590 - -#define REG_READ(base, offset) *(uint32_t*)((uintptr_t)base + (offset)) -#define REG_WRITE(base, offset, v) *(uint32_t*)((uintptr_t)base + (offset)) = v - -struct clock_sys_regs { - void* block0; - void* block1; - void* block2; - void* block3; -}; - -struct clock_sys_regs clk_sys_regs; - -static inline uint32_t reg_read(uintptr_t addr) -{ - uint32_t* reg; - switch (addr & 0x3000) { - case 0x0000: - reg = (uint32_t*)clk_sys_regs.block0; - break; - case 0x1000: - reg = (uint32_t*)clk_sys_regs.block1; - break; - case 0x2000: - reg = (uint32_t*)clk_sys_regs.block2; - break; - case 0x3000: - reg = (uint32_t*)clk_sys_regs.block3; - break; - default: - printf("Invalid memory access: 0x%x\n", (uint32_t)addr); - return 0; - } - - if (addr & 0x3) { - printf("Unaligned memory access: 0x%x\n", (uint32_t)addr); - } - addr &= 0xfff; - addr /= 4; - return reg[addr]; -} - -static inline void reg_write(uintptr_t addr, uint32_t v) -{ - uint32_t* reg; - switch (addr & 0x3000) { - case 0x0000: - reg = (uint32_t*)clk_sys_regs.block0; - break; - case 0x1000: - reg = (uint32_t*)clk_sys_regs.block1; - break; - case 0x2000: - reg = (uint32_t*)clk_sys_regs.block2; - break; - case 0x3000: - reg = (uint32_t*)clk_sys_regs.block3; - break; - default: - printf("Invalid memory access: 0x%x\n", (uint32_t)addr); - return; - } - - if (addr & 0x3) { - printf("Unaligned memory access: 0x%x\n", (uint32_t)addr); - } - addr &= 0xfff; - addr /= 4; - reg[addr] = v; -} - -void test(void) -{ - reg_write(PPSS_TIMER0_CLK_CTL, CLK_BRANCH_ENA); - reg_write(PPSS_TIMER1_CLK_CTL, CLK_BRANCH_ENA); -} - -static struct clock master_clk = { CLK_OPS_DEFAULT(MASTER) }; -static struct clock pxo_clk = { CLK_OPS_DEFAULT(PXO) }; -static struct clock tcxo_clk = { CLK_OPS_DEFAULT(TCXO) }; -static struct clock wcnxo_clk = { CLK_OPS_DEFAULT(WCNXO) }; -static struct clock slpxo_clk = { CLK_OPS_DEFAULT(SLPXO) }; - -static int -apq8064_gate_enable(clock_sys_t* sys, enum clock_gate gate, enum clock_gate_mode mode) -{ - (void)sys; - (void)gate; - (void)mode; - return 0; -} - -void -clk_print_clock_tree(clock_sys_t* sys) -{ - clk_t *clk = clk_get_clock(sys, CLK_MASTER); - clk_print_tree(clk, ""); -} - -static int apq8064_clock_sys_init_common(clock_sys_t* clk_sys) -{ - clk_sys->gate_enable = &apq8064_gate_enable; - clk_sys->get_clock = &ps_get_clock; - return 0; -} - -int -clock_sys_init(ps_io_ops_t* io_ops, clock_sys_t* clk_sys) -{ - struct clock_sys_regs* d = &clk_sys_regs; - MAP_IF_NULL(io_ops, APQ8064_CLK_CTL0, d->block0); - MAP_IF_NULL(io_ops, APQ8064_CLK_CTL1, d->block1); - MAP_IF_NULL(io_ops, APQ8064_CLK_CTL2, d->block2); - MAP_IF_NULL(io_ops, APQ8064_CLK_CTL3, d->block3); - clk_sys->priv = d; - return 0; -} - -int -apq8064_clock_sys_init(void* clk_ctl_base0, void* clk_ctl_base1, - void* clk_ctl_base2, void* clk_ctl_base3, - clock_sys_t* clk_sys) -{ - struct clock_sys_regs* d = &clk_sys_regs; - if (clk_ctl_base0) { - d->block0 = clk_ctl_base0; - } - if (clk_ctl_base1) { - d->block1 = clk_ctl_base1; - } - if (clk_ctl_base2) { - d->block2 = clk_ctl_base2; - } - if (clk_ctl_base3) { - d->block3 = clk_ctl_base3; - } - clk_sys->priv = d; - return apq8064_clock_sys_init_common(clk_sys); -} - -clk_t* ps_clocks[] = { - [CLK_MASTER] = &master_clk, - [CLK_PXO ] = &pxo_clk, - [CLK_WCNXO ] = &wcnxo_clk, - [CLK_TCXO ] = &tcxo_clk, - [CLK_SLPXO ] = &slpxo_clk -}; - -freq_t ps_freq_default[] = { - [CLK_MASTER] = 24 * MHZ, - [CLK_PXO ] = 27 * MHZ, - [CLK_WCNXO ] = 48 * MHZ, - [CLK_TCXO ] = 19200 * KHZ, - [CLK_SLPXO ] = 32768 -}; diff --git a/libplatsupport/src/plat/apq8064/intc.c b/libplatsupport/src/plat/apq8064/intc.c deleted file mode 100644 index 86a30b8cf..000000000 --- a/libplatsupport/src/plat/apq8064/intc.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ -#include -#include -#include - -#define INTCTL0 0x12100000 -#define INTCTL1 0x12100800 -#define INTCTL2 0x12101000 -#define INTCTL3 0x12101800 -#define INTCTL4 0x12102000 -#define INTCTL5 0x12102800 -#define INTCTL6 0x12103000 -#define INTCTL7 0x12103800 - -struct intctl { -#define INTSELECT_IRQ 0x0 -#define INTSELECT_FIQ 0x1 - uint32_t select[2]; /* +0x000 */ - uint32_t res0[2]; -#define INTENABLE_ENABLE 0x1 -#define INTENABLE_DISABLE 0x0 - uint32_t enable[2]; /* +0x010 */ - uint32_t res1[2]; - uint32_t enable_clear[2]; /* +0x020 */ - uint32_t res2[2]; - uint32_t enable_set[2]; /* +0x030 */ - uint32_t res3[2]; -#define INTTYPE_EDGE 0x1 -#define INTTYPE_LEVEL 0x0 - uint32_t type[2]; /* +0x040 */ - uint32_t res4[2]; -#define INTPOL_NEG 0x1 -#define INTPOL_POS 0x0 - uint32_t polariy[2]; /* +0x050 */ - uint32_t res5[2]; - uint32_t no_pend_val; /* +0x060 */ -#define INTMASTER_IRQEN (BIT(0)) -#define INTMASTER_FIQEN (BIT(1)) - uint32_t master_enable; /* +0x064 */ -#define INTVIC_VECTOR_MODE 0x1 - uint32_t vic_config; /* +0x068 */ -#define INTSECURE 0x1 - uint32_t security; /* +0x06C */ - uint32_t res6[4]; - uint32_t irq_status[2]; /* +0x080 */ - uint32_t res7[2]; - uint32_t fiq_status[2]; /* +0x090 */ - uint32_t res8[2]; - uint32_t raw_status[2]; /* +0x0A0 */ - uint32_t res9[2]; - uint32_t raw_clear[2]; /* +0x0B0 */ - uint32_t res10[2]; - uint32_t raw_soft_int[2]; /* +0x0C0 */ - uint32_t res11[2]; - uint32_t vec_rd; /* +0x0D0 */ - uint32_t pend_rd; /* +0x0D4 */ - uint32_t vec_wr; /* +0x0D8 */ - uint32_t res12; - uint32_t in_service; /* +0x0E0 */ - uint32_t in_stack; /* +0x0E4 */ - uint32_t test_bus_sel; /* +0x0E8 */ - uint32_t ctl_config; /* +0x0EC */ - uint32_t res13[4]; - uint32_t res14[64]; - uint32_t priority[64]; /* +0x200 */ - uint32_t res15[64]; - uint32_t vec_addr[64]; /* +0x400 */ - uint32_t res16[64]; -}; -typedef volatile struct intctl intctl_t; - -#define PPSS_INTC 0x12080000 -#define PPSSINTC_IRQ_OFFSET 0x000 -#define PPSSINTC_FIQ_OFFSET 0x100 -struct ppss_intc { - uint32_t stat; /* +0x00 */ - uint32_t rawstat; /* +0x04 */ - uint32_t seten; /* +0x08 */ - uint32_t clren; /* +0x0C */ - uint32_t soft; /* +0x10 */ -}; -typedef volatile struct ppss_intc ppss_intc_t; - -intctl_t* intctl[8]; -ppss_intc_t* fiq; -ppss_intc_t* irq; - -void -test_intc(ps_io_ops_t* o) -{ - void* vaddr[4]; - if (intctl[0] == NULL) { - /* intc */ - vaddr[0] = ps_io_map(&o->io_mapper, INTCTL0, 0x1000, 0, PS_MEM_NORMAL); - vaddr[1] = ps_io_map(&o->io_mapper, INTCTL2, 0x1000, 0, PS_MEM_NORMAL); - vaddr[2] = ps_io_map(&o->io_mapper, INTCTL3, 0x1000, 0, PS_MEM_NORMAL); - vaddr[3] = ps_io_map(&o->io_mapper, INTCTL4, 0x1000, 0, PS_MEM_NORMAL); - assert(vaddr[0]); - assert(vaddr[1]); - assert(vaddr[2]); - assert(vaddr[3]); - intctl[0] = (intctl_t*)((uintptr_t)vaddr[0] + 0x000); - intctl[1] = (intctl_t*)((uintptr_t)vaddr[0] + 0x800); - intctl[2] = (intctl_t*)((uintptr_t)vaddr[1] + 0x000); - intctl[3] = (intctl_t*)((uintptr_t)vaddr[1] + 0x800); - intctl[4] = (intctl_t*)((uintptr_t)vaddr[2] + 0x000); - intctl[5] = (intctl_t*)((uintptr_t)vaddr[2] + 0x800); - intctl[6] = (intctl_t*)((uintptr_t)vaddr[3] + 0x000); - intctl[7] = (intctl_t*)((uintptr_t)vaddr[3] + 0x800); - /* ppss intc */ - vaddr[0] = ps_io_map(&o->io_mapper, PPSS_INTC, 0x1000, 0, PS_MEM_NORMAL); - irq = (ppss_intc_t*)((uintptr_t)vaddr[0] + PPSSINTC_IRQ_OFFSET); - fiq = (ppss_intc_t*)((uintptr_t)vaddr[0] + PPSSINTC_FIQ_OFFSET); - printf("irq: 0x%x 0x%x 0x%x 0x%x 0x%x\n", irq->stat, irq->rawstat, irq->seten, irq->clren, irq->soft); - printf("fiq: 0x%x 0x%x 0x%x 0x%x 0x%x\n", fiq->stat, fiq->rawstat, fiq->seten, fiq->clren, fiq->soft); - irq->soft = 1; - irq->seten = 0xffff; - printf("irq: 0x%x 0x%x 0x%x 0x%x 0x%x\n", irq->stat, irq->rawstat, irq->seten, irq->clren, irq->soft); - } -}; diff --git a/libplatsupport/src/plat/apq8064/mux.c b/libplatsupport/src/plat/apq8064/mux.c deleted file mode 100644 index ad209e6bb..000000000 --- a/libplatsupport/src/plat/apq8064/mux.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ -#include -#include -#include -#include "../../services.h" - -struct apq8064_mux_regs { - int dummy; -}; - -static struct apq8064_mux { - volatile struct apq8064_mux_regs* mux; -} _mux; - -static inline struct apq8064_mux* get_mux_priv(const mux_sys_t* mux) { - return (struct apq8064_mux*)mux->priv; -} - -static inline void set_mux_priv(mux_sys_t* mux, struct apq8064_mux* apq8064_mux) -{ - assert(mux != NULL); - assert(apq8064_mux != NULL); - mux->priv = apq8064_mux; -} - -static int -apq8064_mux_feature_enable(const mux_sys_t* mux, mux_feature_t mux_feature, UNUSED enum mux_gpio_dir mgd) -{ - struct apq8064_mux* m; - if (mux == NULL || mux->priv == NULL) { - return -1; - } - m = get_mux_priv(mux); - - switch (mux_feature) { - default: - (void)m; - return -1; - } -} - -static int -apq8064_mux_init_common(mux_sys_t* mux) -{ - set_mux_priv(mux, &_mux); - mux->feature_enable = &apq8064_mux_feature_enable; - return 0; -} - -int -apq8064_mux_init(void* bank1, - mux_sys_t* mux) -{ - (void)bank1; - return apq8064_mux_init_common(mux); -} - -int -mux_sys_init(ps_io_ops_t* io_ops, UNUSED void *dependencies, mux_sys_t* mux) -{ - (void)io_ops; - return apq8064_mux_init_common(mux); -} diff --git a/libplatsupport/src/plat/apq8064/serial.c b/libplatsupport/src/plat/apq8064/serial.c deleted file mode 100644 index 51884047b..000000000 --- a/libplatsupport/src/plat/apq8064/serial.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#include -#include -#include -#include - -#include "../../chardev.h" - -#define USR 0x0008 /* Status register */ -#define UCR 0x0010 /* Control register */ -#define UTF 0x0070 /* TX fifo */ -#define UNTX 0x0040 /* Number of bytes to send */ - -#define USR_TXRDY (1U << 2) -#define USR_TXEMP (1U << 3) - -#define CMD_TXRDY_RESET (3U << 8) - -#define UART_REG(base, x) ((volatile uint32_t *)((uintptr_t)(base) + (x))) - -static void -uart_handle_irq(ps_chardevice_t* d UNUSED) -{ -} - -int uart_putchar(ps_chardevice_t* d, int c) -{ - while (!(*UART_REG(d->vaddr, USR) & USR_TXEMP)); - - *UART_REG(d->vaddr, UNTX) = 1; - *UART_REG(d->vaddr, UTF) = c & 0xff; - if (c == '\n' && (d->flags & SERIAL_AUTO_CR)) { - uart_putchar(d, '\r'); - } - return 0; -} - -int uart_getchar(ps_chardevice_t* d UNUSED) -{ - return EOF; -} - -int uart_init(const struct dev_defn* defn, - const ps_io_ops_t* ops, - ps_chardevice_t* dev) -{ - /* Attempt to map the virtual address, assure this works */ - void* vaddr = chardev_map(defn, ops); - memset(dev, 0, sizeof(*dev)); - if (vaddr == NULL) { - return -1; - } - - /* Set up all the device properties. */ - dev->id = defn->id; - dev->vaddr = (void*)vaddr; - dev->read = &uart_read; - dev->write = &uart_write; - dev->handle_irq = &uart_handle_irq; - dev->irqs = defn->irqs; - dev->ioops = *ops; - dev->flags = SERIAL_AUTO_CR; - - return 0; -} diff --git a/libplatsupport/src/plat/apq8064/timer.c b/libplatsupport/src/plat/apq8064/timer.c deleted file mode 100644 index b684ccbe6..000000000 --- a/libplatsupport/src/plat/apq8064/timer.c +++ /dev/null @@ -1,548 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ -/* @AUTHOR(akroh@ertos.nicta.com.au) */ - -#include -#include -#include -#include - -#include - -#include - -#define XOTMR_FIN 19200000UL -#define SLPTMR_FIN 32768UL -static inline uint64_t -get_tcxo_hz(void) -{ - return 7 * 1000 * 1000; -} - -static inline uint64_t -get_xo_hz(void) -{ - return XOTMR_FIN; -} - -static inline uint64_t -get_slp_hz(void) -{ - return SLPTMR_FIN; -} - -/** Timer map offsets **/ -#define KPSSSECURE_OFFSET 0x000 -#define KPSSGPT0_OFFSET 0x004 -#define KPSSGPT1_OFFSET 0x014 -#define KPSSDGT_OFFSET 0x024 -#define KPSSWDT0_OFFSET 0x038 -#define KPSSWDT1_OFFSET 0x060 -#define KPSSSTAT_OFFSET 0x088 - -#define GSSSECURE_OFFSET KPSSSECURE_OFFSET -#define GSSGPT0_OFFSET KPSSGPT0_OFFSET -#define GSSGPT1_OFFSET KPSSGPT1_OFFSET -#define GSSDGT_OFFSET KPSSDGT_OFFSET -#define GSSWDT0_OFFSET KPSSWDT0_OFFSET -#define GSSWDT1_OFFSET KPSSWDT1_OFFSET -#define GSSSTAT_OFFSET KPSSSTAT_OFFSET - -#define PPSSXOTMR0_OFFSET 0x800 -#define PPSSXOTMR1_OFFSET 0x818 - -#define PPSSTMR0_OFFSET 0x000 -#define PPSSTMR1_OFFSET 0x018 -#define PPSSWDT_OFFSET 0x800 -#define PPSSCLKCTNTL_OFFSET 0x824 - -#define RPMGPT0_OFFSET 0x000 -#define RPMGPT0_CLK_CTL 0x010 -#define RPMGPT1_OFFSET 0x040 -#define RPMWDT_OFFSET 0x060 -#define RPMTMRSTS_OFFSET 0x100 - -/* Clock control Bitmaps */ -#define PPSSCLKCTNTL_WDGON (1U << 1) -#define PPSSCLKCTNTL_SLPON (1U << 1) - -#define TMRSTS(x, i) ((x) << (8 * i)) -#define TMRSTS_WR_PEND(i) TMRSTS(1U << 3, i) -#define TMRSTS_CLR_PEND(i) TMRSTS(1U << 2, i) -#define TMRSTS_CLR_ON_MTCH_EN(i) TMRSTS(1U << 1, i) -#define TMRSTS_EN(i) TMRSTS(1U << 0, i) -#define TMRSTS_PEND(i) (TMRSTS_WR_PEND(i) | TMRSTS_CLR_PEND(i)) - -#define RPMTMRSTS_WDOG_EN (1U << 17) -#define RPMTMRSTS_WDOG_UNMASKED_INT_EN (1U << 16) -#define RPMTMRSTS_TMR1_WR_PEND TMRSTS_WR_PEND(1) -#define RPMTMRSTS_TMR1_CLR_PEND TMRSTS_CLR_PEND(1) -#define RPMTMRSTS_TMR1_CLK_ON_MTCH TMRSTS_CLR_ON_MTCH(1) -#define RPMTMRSTS_TMR1_PEND TMRSTS_PEND(1) -#define RPMTMRSTS_TMR1_EN TMRSTS_EN(1) -#define RPMTMRSTS_TMR0_WR_PEND TMRSTS_WR_PEND(0) -#define RPMTMRSTS_TMR0_CLR_PEND TMRSTS_CLR_PEND(0) -#define RPMTMRSTS_TMR0_CLR_ON_MTCH TMRSTS_CLR_ON_MTCH(0) -#define RPMTMRSTS_TMR0_EN TMRSTS_EN(0) -#define RPMTMRSTS_TMR0_PEND TMRSTS_PEND(0) - -#define KPSSGPTSTS_TMR1_WR_PEND TMRSTS_WR_PEND(1) -#define KPSSGPTSTS_TMR1_CLR_PEND TMRSTS_CLR_PEND(1) -#define KPSSGPTSTS_TMR1_CLK_ON_MTCH TMRSTS_CLR_ON_MTCH(1) -#define KPSSGPTSTS_TMR1_EN TMRSTS_EN(1) -#define KPSSGPTSTS_TMR1_PEND TMRSTS_PEND(1) -#define KPSSGPTSTS_TMR0_WR_PEND TMRSTS_WR_PEND(0) -#define KPSSGPTSTS_TMR0_CLR_PEND TMRSTS_CLR_PEND(0) -#define KPSSGPTSTS_TMR0_CLR_ON_MTCH TMRSTS_CLR_ON_MTCH(0) -#define KPSSGPTSTS_TMR0_EN TMRSTS_EN(0) -#define KPSSGPTSTS_TMR0_PEND TMRSTS_PEND(0) - -#define GSSGPTSTS_TMR1_WR_PEND TMRSTS_WR_PEND(1) -#define GSSGPTSTS_TMR1_CLR_PEND TMRSTS_CLR_PEND(1) -#define GSSGPTSTS_TMR1_CLK_ON_MTCH TMRSTS_CLR_ON_MTCH(1) -#define GSSGPTSTS_TMR1_EN TMRSTS_EN(1) -#define GSSGPTSTS_TMR1_PEND TMRSTS_PEND(1) -#define GSSGPTSTS_TMR0_WR_PEND TMRSTS_WR_PEND(0) -#define GSSGPTSTS_TMR0_CLR_PEND TMRSTS_CLR_PEND(0) -#define GSSGPTSTS_TMR0_CLR_ON_MTCH TMRSTS_CLR_ON_MTCH(0) -#define GSSGPTSTS_TMR0_EN TMRSTS_EN(0) -#define GSSGPTSTS_TMR0_PEND TMRSTS_PEND(0) - -#define RPMGPT0_DIV(x) ((x) - 1) -#define RPMGPT0_DIV4 RPMGPT0_DIV(4) -#define RPMGPT0_DIV3 RPMGPT0_DIV(3) -#define RPMGPT0_DIV2 RPMGPT0_DIV(2) -#define RPMGPT0_DIV1 RPMGPT0_DIV(1) - -#define TMR_CTRL_ON (1U << 5) -#define TMR_CTRL_EN (1U << 4) -#define TMR_CTRL_MODE(x) ((x) << 2) -#define TMR_CTRL_MODE_FREE_RUN TMR_CTRL_MODE(0x0) -#define TMR_CTRL_MODE_ONE_SHOT TMR_CTRL_MODE(0x1) -#define TMR_CTRL_MODE_PERIODIC TMR_CTRL_MODE(0x2) -#define TMR_CTRL_MODE_MASK TMR_CTRL_MODE(0x3) -#define TMR_CTRL_PRESCALE(x) ((x) << 0) -#define TMR_CTRL_PRESCALE_DIV32 TMR_CTRL_PRESCALE(0x0) -#define TMR_CTRL_PRESCALE_DIV8 TMR_CTRL_PRESCALE(0x1) -#define TMR_CTRL_PRESCALE_DIV4 TMR_CTRL_PRESCALE(0x2) -#define TMR_CTRL_PRESCALE_DIV2 TMR_CTRL_PRESCALE(0x3) -#define TMR_CTRL_PRESCALE_MASK TMR_CTRL_PRESCALE(0x3) - -#define TMR_STAT_MATCH_UPDATE (1U << 4) -#define TMR_STAT_COUNT_UPDATE (1U << 3) -#define TMR_STAT_CONTROL_UPDATE (1U << 2) -#define TMR_STAT_CLR_INT_UPDATE (1U << 1) -#define TMR_STAT_CLK_CNT_UPDATE (1U << 0) - -/** General bitmaps **/ -#define DGTTMR_EN_CLR_ON_MTCH_EN (1U << 1) -#define DGTTMR_EN_EN (1U << 0) -#define DGTTMR_CLK_CTRL(x) ((x) << 0) -#define DGTTMR_CLK_CTRL_DIV1 DGTTMR_CLK_CTRL(0x0) -#define DGTTMR_CLK_CTRL_DIV2 DGTTMR_CLK_CTRL(0x1) -#define DGTTMR_CLK_CTRL_DIV3 DGTTMR_CLK_CTRL(0x2) -#define DGTTMR_CLK_CTRL_DIV4 DGTTMR_CLK_CTRL(0x3) -#define DGTTMR_CLK_CTRL_MASK DGTTMR_CLK_CTRL(0x3) - -#define WDTRESET (1U << 0) -#define WDTFREEZE (1U << 0) -#define WDTINTEN_EN (1U << 1) -#define WDTINTEN_UNMASKED_INTEN (1U << 0) -#define WDTSTAT_COUNT(x) ((x) << 3) -#define WDTSTAT_GETCOUNT(x) ((x) >> 3) -#define WDTSTAT_CNT_RESET_STAT (1U << 2) -#define WDTSTAT_FROZEN(x) (1U << 1) -#define WDTSTAT_EXPIRED(x) (1U << 0) -#define WDTEXP_SYNC (1U << 14) -#define WDTEXP_DATA(x) (((x) & 0x3fff) << 0) -#define WDTEXP_GETDATA(x) (((x) >> 0) & 0x3fff) -#define WDTBARK_SYNC (1U << 14) -#define WDTBARK_DATA(x) (((x) & 0x3fff) << 0) -#define WDTBARK_GETDATA(x) (((x) >> 0) & 0x3fff) -#define WDTTESTLOADSTAT_SYNC (1U << 0) -#define WDTTESTLOAD_LOAD (1U << 0) -#define WDTTEST_SYNC (1U << 14) -#define WDTTEST_LOAD(x) (((x) & 0x3fff) << 0) -#define WDTTEST_GETLOAD(x) (((x) >> 0) & 0x3fff) - -#define GPTEN_CLR_ON_MTCH_EN (1U << 1) -#define GPTEN_EN (1U << 0) - -/** Helpers **/ -#define TIMER_VADDR_OFFSET(base, offset) ((void*)((uintptr_t)base + offset)) -#define TIMER_REG(base, offset) *(volatile uint32_t *)TIMER_VADDR_OFFSET(base, offset) - -/** Timer register maps **/ -struct tmr_regs { - uint32_t match; /* +0x00 */ - uint32_t count; /* +0x04 */ - uint32_t control; /* +0x08 */ - uint32_t clear_int; /* +0x0C */ - uint32_t clear_cnt; /* +0x10 */ - uint32_t status; /* +0x14 */ -}; -typedef volatile struct tmr_regs tmr_regs_t; - -struct dgt_regs { - uint32_t mtch; /* +0x00 */ - uint32_t cnt; /* +0x04 */ - uint32_t en; /* +0x08 */ - uint32_t clr; /* +0x0C */ - uint32_t clk_ctl; /* +0x10 */ -}; -typedef volatile struct dgt_regs dgt_regs_t; - -struct wdt_regs { - uint32_t reset; /* +0x00 */ - uint32_t freeze; /* +0x04 */ - uint32_t unmasked_int_en; /* +0x08 */ - uint32_t status; /* +0x0C */ - uint32_t expired_width; /* +0x10 */ - uint32_t bark_time; /* +0x14 */ - uint32_t test_load_status; /* +0x18 */ - uint32_t test_load; /* +0x1C */ - uint32_t test; /* +0x20 */ - /* Only for KRAIT and GSS */ - uint32_t bite_time; /* +0x24 */ -}; -typedef volatile struct wdt_regs wdt_regs_t; - -struct gpt_regs { - uint32_t mtch; /* +0x00 */ - uint32_t cnt; /* +0x04 */ - uint32_t en; /* +0x08 */ - uint32_t clr; /* +0x0C */ -}; -typedef volatile struct gpt_regs gpt_regs_t; - -/**** GPT timer functions ****/ -int -gpt_timer_start(timer_t *timer) -{ - gpt_regs_t* regs = (gpt_regs_t*)timer->data; - regs->en |= GPTEN_EN; - return 0; -} - -int -gpt_timer_stop(timer_t *timer) -{ - gpt_regs_t* regs = (gpt_regs_t*)timer->data; - regs->en &= ~GPTEN_EN; - return 0; -} - -uint64_t -gpt_get_time(timer_t *timer) -{ - gpt_regs_t* regs = (gpt_regs_t*)timer->data; - return regs->cnt; -} - -int -gpt_periodic(timer_t *timer, uint64_t ns) -{ - gpt_regs_t* regs = (gpt_regs_t*)timer->data; - uintptr_t sts_base = (uintptr_t)timer->data & ~0xfff; - volatile uint32_t* sts = (volatile uint32_t*)sts_base; - uint64_t fin; - switch (timer->id) { - case TMR_RPM_GPT0 : - fin = get_xo_hz() / 4; - break; - case TMR_RPM_GPT1: - case TMR_KPSS_GPT0: - case TMR_KPSS_GPT1: - case TMR_GSS_GPT0: - case TMR_GSS_GPT1: - fin = get_slp_hz(); - break; - default: - assert(!"invalid timer for GPT operation"); - return -1; - } - /* Clear the timer on match */ - - regs->en = GPTEN_CLR_ON_MTCH_EN; - switch (timer->id) { - case TMR_RPM_GPT0 : - while (sts[RPMTMRSTS_OFFSET / 4] & RPMTMRSTS_TMR0_WR_PEND); - break; - case TMR_RPM_GPT1: - while (sts[RPMTMRSTS_OFFSET / 4] & RPMTMRSTS_TMR1_WR_PEND); - break; - case TMR_KPSS_GPT0: - case TMR_GSS_GPT0: - while (sts[KPSSSTAT_OFFSET / 4] & KPSSGPTSTS_TMR0_WR_PEND); - break; - case TMR_KPSS_GPT1: - case TMR_GSS_GPT1: - while (sts[KPSSSTAT_OFFSET / 4] & KPSSGPTSTS_TMR1_WR_PEND); - break; - default: - break; - } - /* Reset the timer */ - regs->clr = 0xC0FFEE; - /* Configure match value */ - regs->mtch = (fin * ns) / (1000UL * 1000 * 1000); - - switch (timer->id) { - case TMR_RPM_GPT0 : - while (sts[RPMTMRSTS_OFFSET / 4] & RPMTMRSTS_TMR0_PEND); - break; - case TMR_RPM_GPT1: - while (sts[RPMTMRSTS_OFFSET / 4] & RPMTMRSTS_TMR1_PEND); - break; - case TMR_KPSS_GPT0: - case TMR_GSS_GPT0: - while (sts[KPSSSTAT_OFFSET / 4] & KPSSGPTSTS_TMR0_PEND); - break; - case TMR_KPSS_GPT1: - case TMR_GSS_GPT1: - while (sts[KPSSSTAT_OFFSET / 4] & KPSSGPTSTS_TMR1_PEND); - break; - default: - break; - } - - return 0; -} - -void -gpt_handle_irq(UNUSED timer_t *timer) -{ - /* Nothing to do */ -} - -/* DGT timer functions */ -int -dgt_timer_start(timer_t *timer) -{ - dgt_regs_t* regs = (dgt_regs_t*)timer->data; - regs->en |= DGTTMR_EN_EN; - return 0; -} - -int -dgt_timer_stop(timer_t *timer) -{ - dgt_regs_t* regs = (dgt_regs_t*)timer->data; - regs->en &= ~DGTTMR_EN_EN; - return 0; -} - -uint64_t -dgt_get_time(timer_t *timer) -{ - dgt_regs_t* regs = (dgt_regs_t*)timer->data; - return regs->cnt; -} - -int -dgt_periodic(timer_t *timer, uint64_t ns) -{ - dgt_regs_t* regs = (dgt_regs_t*)timer->data; - uint64_t fin_hz = get_tcxo_hz(); - int div; - /* Disable */ - regs->en = 0; - /* Configure */ - regs->clr = 0xC0FFEE; - /* DIV should always be 4 due to clock domain delay */ - regs->clk_ctl = DGTTMR_CLK_CTRL_DIV4; - div = 4; - regs->mtch = (fin_hz * ns) / (div * 1000 * 1000 * 1000); - regs->en = DGTTMR_EN_CLR_ON_MTCH_EN; - return 0; -} - -void -dgt_handle_irq(UNUSED timer_t *timer) -{ - /* Nothing to do */ -} - -/**** TMR ****/ -int -tmr_timer_start(timer_t *timer) -{ - tmr_regs_t* regs = (tmr_regs_t*)timer->data; - regs->control |= ~TMR_CTRL_EN; - return 0; -} - -int -tmr_timer_stop(timer_t *timer) -{ - tmr_regs_t* regs = (tmr_regs_t*)timer->data; - regs->control &= ~TMR_CTRL_EN; - return 0; -} - -uint64_t -tmr_get_time(timer_t *timer) -{ - tmr_regs_t* regs = (tmr_regs_t*)timer->data; - return regs->count; -} - -int -tmr_periodic(timer_t *timer, uint64_t ns) -{ - tmr_regs_t* regs = (tmr_regs_t*)timer->data; - uint64_t fin_hz; - /* Find input clock frequency */ - switch (timer->id) { - case TMR_PPSS_XO_TMR0: - case TMR_PPSS_XO_TMR1: - fin_hz = get_tcxo_hz(); - break; - case TMR_PPSS_SLP_TMR0: - case TMR_PPSS_SLP_TMR1: - fin_hz = get_slp_hz(); - break; - default: - assert(!"Invalid timer for this call"); - return -1; - } - /* Turn on the timer */ - regs->control = TMR_CTRL_ON; - while (regs->status & TMR_STAT_CONTROL_UPDATE); - /* Reset and config */ - regs->control |= TMR_CTRL_PRESCALE_DIV4 | TMR_CTRL_MODE_PERIODIC; - regs->clear_int = 0xC0FFEE; - regs->clear_cnt = 0xC0FFEE; - regs->match = (fin_hz * ns) / (4UL * 1000 * 1000 * 1000); - /* Wait for registers to be updated */ - while (regs->status); - return 0; -} - -void -tmr_handle_irq(timer_t *timer) -{ - tmr_regs_t* regs = (tmr_regs_t*)timer->data; - /* Reset the IRQ */ - regs->clear_int = 0xC0FFEE; -} - -/**** WDT ****/ -int -wdt_timer_start(timer_t *timer) -{ - wdt_regs_t* regs = (wdt_regs_t*)timer->data; - /* Don't send a reset */ - regs->reset = 0; - /* Enable the auto-kicker */ - regs->freeze = WDTFREEZE; - regs->unmasked_int_en = WDTINTEN_EN | WDTINTEN_UNMASKED_INTEN; - return 0; -} - -uint64_t -wdt_get_time(timer_t *timer) -{ - wdt_regs_t* regs = (wdt_regs_t*)timer->data; - return WDTSTAT_GETCOUNT(regs->status); -} - -int -wdt_periodic(timer_t *timer, uint64_t ns) -{ - wdt_regs_t* regs = (wdt_regs_t*)timer->data; - uint64_t fin_hz = get_slp_hz(); - uint32_t bark_time; - /* Disable */ - regs->unmasked_int_en = WDTINTEN_EN; - /* Enable the auto-kicker */ - regs->freeze = WDTFREEZE; - /* Don't reset */ - regs->reset = 0; - /* Set the counter value */ - bark_time = (fin_hz * ns) / (1000 * 1000); - regs->bark_time = WDTBARK_DATA(bark_time); - assert(!"Not yet implemented"); - return 0; -} - -int timer_init(timer_t *timer, timer_config_t config) -{ - if (config.id < 0 || config.id >= NTIMERS) { - return EINVAL; - } - - timer->id = config.id; - - /* Default handlers */ - switch (config.id) { - case TMR_PPSS_XO_TMR0: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, PPSSXOTMR0_OFFSET); - break; - case TMR_PPSS_XO_TMR1: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, PPSSXOTMR1_OFFSET); - break; - case TMR_PPSS_SLP_TMR0: - TIMER_REG(config.vaddr, PPSSCLKCTNTL_OFFSET) |= PPSSCLKCTNTL_SLPON; - timer->data = TIMER_VADDR_OFFSET(config.vaddr, PPSSTMR0_OFFSET); - break; - case TMR_PPSS_SLP_TMR1: - TIMER_REG(config.vaddr, PPSSCLKCTNTL_OFFSET) |= PPSSCLKCTNTL_SLPON; - timer->data = TIMER_VADDR_OFFSET(config.vaddr, PPSSTMR1_OFFSET); - break; - case TMR_PPSS_SLP_WDOG: - TIMER_REG(config.vaddr, PPSSCLKCTNTL_OFFSET) |= PPSSCLKCTNTL_WDGON; - timer->data = TIMER_VADDR_OFFSET(config.vaddr, PPSSWDT_OFFSET); - break; - /* KPSS */ - case TMR_KPSS_GPT0: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, KPSSGPT0_OFFSET); - break; - case TMR_KPSS_GPT1: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, KPSSGPT1_OFFSET); - break; - case TMR_KPSS_DGT: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, KPSSDGT_OFFSET); - break; - case TMR_KPSS_WDT0: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, KPSSGPT0_OFFSET); - break; - case TMR_KPSS_WDT1: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, KPSSGPT1_OFFSET); - break; - /* GSS */ - case TMR_GSS_GPT0: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, GSSGPT0_OFFSET); - break; - case TMR_GSS_GPT1: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, GSSGPT1_OFFSET); - break; - case TMR_GSS_DGT: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, GSSDGT_OFFSET); - break; - case TMR_GSS_WDT0: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, GSSGPT0_OFFSET); - break; - case TMR_GSS_WDT1: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, GSSGPT1_OFFSET); - break; - /* RPM */ - case TMR_RPM_GPT0: - TIMER_REG(config.vaddr, RPMGPT0_CLK_CTL) = RPMGPT0_DIV4; - timer->data = TIMER_VADDR_OFFSET(config.vaddr, RPMGPT0_OFFSET); - break; - case TMR_RPM_GPT1: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, RPMGPT1_OFFSET); - break; - case TMR_RPM_WDOG: - timer->data = TIMER_VADDR_OFFSET(config.vaddr, RPMWDT_OFFSET); - break; - default: - return EINVAL; - } - - return 0; -} diff --git a/libplatsupport/src/plat/exynos4/clock.c b/libplatsupport/src/plat/exynos4/clock.c deleted file mode 100644 index 5b6921372..000000000 --- a/libplatsupport/src/plat/exynos4/clock.c +++ /dev/null @@ -1,410 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#include "../../common.h" -#include "../../mach/exynos/clock.h" -#include - -/* Memory map */ -#define CMU_LEFTBUS_PADDR 0x10034000 -#define CMU_RIGHTBUS_PADDR 0x10038000 -#define CMU_TOP_PADDR 0x1003C000 -#define CMU_DMC1_PADDR 0x10040000 -#define CMU_DMC2_PADDR 0x10041000 -#define CMU_CPU1_PADDR 0x10044000 -#define CMU_CPU2_PADDR 0x10045000 -#define CMU_ISP_PADDR 0x10048000 - -#define CMU_LEFTBUS_SIZE 0x1000 -#define CMU_RIGHTBUS_SIZE 0x1000 -#define CMU_TOP_SIZE 0x1000 -#define CMU_DMC1_SIZE 0x1000 -#define CMU_DMC2_SIZE 0x1000 -#define CMU_CPU1_SIZE 0x1000 -#define CMU_CPU2_SIZE 0x1000 -#define CMU_ISP_SIZE 0x1000 - -/* Root clock frequencies */ -#define XUSBXTI_FREQ 24000000UL -#define XXTI_FREQ 0UL /* ? */ - -/* The input source could be read from boot switches */ -#if 1 -#define FINPLL_FREQ XUSBXTI_FREQ -#else -#define FINPLL_FREQ XXTI_FREQ -#endif - -#define OFFSET_MOUTAPLL (0x00 / 4) -#define OFFSET_SCLKMPLL (0x08 / 4) -#define OFFSET_SCLKEPLL (0x10 / 4) -#define OFFSET_SCLKVPLL (0x20 / 4) - -#define CLKID_MOUTAPLL CLKID(CPU1, 0, 0) -#define CLKID_SCLKMPLL CLKID(DMC1, 2, 3) -#define CLKID_SCLKEPLL CLKID(TOP , 4, 1) -#define CLKID_SCLKVPLL CLKID(TOP , 4, 2) - -#define CLKID_DIVCORE CLKID(CPU1, 0, 0) -#define CLKID_ACLK_COREM0 CLKID(CPU1, 0, 1) -#define CLKID_ACLK_COREM1 CLKID(CPU1, 0, 2) -#define CLKID_PERIPHCLK CLKID(CPU1, 0, 3) -#define CLKID_ATCLK CLKID(CPU1, 0, 4) -#define CLKID_PCLK_DBG CLKID(CPU1, 0, 5) -#define CLKID_SCLKAPLL CLKID(CPU1, 0, 6) -#define CLKID_DIVCORE2 CLKID(CPU1, 0, 7) -#define CLKID_DIVCOPY CLKID(CPU1, 1, 0) -#define CLKID_SCLKHPM CLKID(CPU1, 1, 1) -#define CLKID_ACLK_CORES CLKID(CPU1, 1, 2) - -/************************ - **** PLL **** - ************************/ - -static struct mpsk_tbl _ampll_tbl[] = { - { 200, PLL_MPS(100, 3, 2), 0}, - { 300, PLL_MPS(200, 4, 2), 0}, - { 400, PLL_MPS(100, 3, 1), 0}, - { 500, PLL_MPS(125, 3, 1), 0}, - { 600, PLL_MPS(200, 4, 1), 0}, - { 700, PLL_MPS(175, 3, 1), 0}, - { 800, PLL_MPS(100, 3, 0), 0}, - { 900, PLL_MPS(150, 4, 0), 0}, - {1000, PLL_MPS(125, 3, 0), 0}, - {1100, PLL_MPS(275, 6, 0), 0}, - {1200, PLL_MPS(200, 4, 0), 0}, - {1300, PLL_MPS(325, 6, 0), 0}, - {1400, PLL_MPS(175, 3, 0), 0} -}; - -/* some of the 180MHz derivations are note available here */ -static struct mpsk_tbl _epll_tbl[] = { - { 90, PLL_MPS( 60, 2, 3), 0}, - { 180, PLL_MPS( 60, 2, 2), 0}, - { 192, PLL_MPS( 64, 2, 2), 0}, - { 200, PLL_MPS(100, 3, 2), 0}, - { 400, PLL_MPS(100, 3, 1), 0}, - { 408, PLL_MPS( 68, 2, 1), 0}, - { 416, PLL_MPS(104, 3, 1), 0} -}; - -static struct mpsk_tbl _vpll_tbl[] = { - { 100, PLL_MPS(100, 3, 3), 0}, - { 160, PLL_MPS(160, 3, 3), 0}, - { 266, PLL_MPS(133, 3, 2), 0}, - { 350, PLL_MPS(175, 3, 2), 0}, - { 440, PLL_MPS(110, 3, 1), 0} -}; - -/************************ - **** source options **** - ************************/ -/* PERIL CLK SEL */ -#define CLK_SEL_BITS 4 -#define CLK_SEL_SHIFT(x) ((x)*CLK_SEL_BITS) -#define CLK_SEL_MASK ((BIT(CLK_SEL_SHIFT(1))) - 1) -#define CLK_SEL_VPLL 0x8 -#define CLK_SEL_EPLL 0x7 -#define CLK_SEL_MPLL_USER_T 0x6 -#define CLK_SEL_HDMIPHY 0x5 -#define CLK_SEL_USBPHY0 0x3 -#define CLK_SEL_HDMU24M 0x2 -#define CLK_SEL_XUSBXTI 0x1 -#define CLK_SEL_XXTI 0x0 - -enum clkregs { - CLKREGS_LEFT, - CLKREGS_RIGHT, - CLKREGS_TOP, - CLKREGS_DMC1, - CLKREGS_DMC2, - CLKREGS_CPU1, - CLKREGS_CPU2, - CLKREGS_ISP, - NCLKREGS -}; - -volatile struct clk_regs* _clk_regs[NCLKREGS]; - -static struct clock finpll_clk = { CLK_OPS_DEFAULT(MASTER) }; -/* --- Implement Me --- */ -static struct clock uart0_clk = { CLK_OPS_DEFAULT(UART0) }; -static struct clock uart1_clk = { CLK_OPS_DEFAULT(UART1) }; -static struct clock uart2_clk = { CLK_OPS_DEFAULT(UART2) }; -static struct clock uart3_clk = { CLK_OPS_DEFAULT(UART3) }; -/* -------------------- */ - -static struct pll_priv moutapll_priv = PLL_PRIV(MOUTAPLL, MPS, _ampll_tbl); -static struct pll_priv sclkmpll_priv = PLL_PRIV(SCLKMPLL, MPS, _ampll_tbl); -static struct pll_priv sclkepll_priv = PLL_PRIV(SCLKEPLL, MPSK, _epll_tbl); -static struct pll_priv sclkvpll_priv = PLL_PRIV(SCLKVPLL, MPSK, _vpll_tbl); - -static struct clock aoutpll_clk = { CLK_OPS(MOUTAPLL, pll, &moutapll_priv) }; -static struct clock sclkmpll_clk = { CLK_OPS(SCLKMPLL, pll, &sclkmpll_priv) }; -static struct clock sclkepll_clk = { CLK_OPS(SCLKEPLL, pll, &sclkepll_priv) }; -static struct clock sclkvpll_clk = { CLK_OPS(SCLKVPLL, pll, &sclkvpll_priv) }; - -static clk_t* -_div_init(clk_t* clk) -{ - clk_t* parent; - switch (clk->id) { - case CLK_SCLKAPLL: - parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MOUTAPLL); - break; - case CLK_DIVCORE: - case CLK_ATCLK: - parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MUXCORE); - break; - case CLK_DIVCORE2: - parent = clk_get_clock(clk_get_clock_sys(clk), CLK_DIVCORE); - break; - case CLK_ACLK_COREM0: - case CLK_ACLK_CORES: - case CLK_ACLK_COREM1: - case CLK_PERIPHCLK: - parent = clk_get_clock(clk_get_clock_sys(clk), CLK_DIVCORE2); - break; - case CLK_PCLK_DBG: - parent = clk_get_clock(clk_get_clock_sys(clk), CLK_ATCLK); - break; - case CLK_SCLKHPM: - parent = clk_get_clock(clk_get_clock_sys(clk), CLK_DIVCOPY); - break; - case CLK_DIVCOPY: - parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MUXHPM); - break; - default: - assert(!"Unknown clock id for div"); - parent = NULL; - } - assert(parent); - clk_init(parent); - clk_register_child(parent, clk); - return clk; -} - -static struct clock sclkapll_clk = { CLK_OPS(SCLKAPLL , div, CLKID_SCLKAPLL) }; -static struct clock divcore_clk = { CLK_OPS(DIVCORE , div, CLKID_DIVCORE) }; -static struct clock arm_clk = { CLK_OPS(DIVCORE2 , div, CLKID_DIVCORE2) }; -static struct clock corem0_clk = { CLK_OPS(ACLK_COREM0, div, CLKID_ACLK_COREM0) }; -static struct clock corem1_clk = { CLK_OPS(ACLK_COREM1, div, CLKID_ACLK_COREM1) }; -static struct clock cores_clk = { CLK_OPS(ACLK_CORES , div, CLKID_ACLK_CORES) }; -static struct clock periphclk_clk = { CLK_OPS(PERIPHCLK , div, CLKID_PERIPHCLK) }; -static struct clock atclk_clk = { CLK_OPS(ATCLK , div, CLKID_ATCLK) }; -static struct clock pclk_dbg_clk = { CLK_OPS(PCLK_DBG , div, CLKID_PCLK_DBG) }; -static struct clock sclkhpm_clk = { CLK_OPS(SCLKHPM , div, CLKID_SCLKHPM) }; -static struct clock divcopy_clk = { CLK_OPS(DIVCOPY , div, CLKID_DIVCOPY) }; - -/*************** - **** MUXes **** - ***************/ -static freq_t -_mux_get_freq(clk_t* clk) -{ - return clk_get_freq(clk->parent); -} - -static freq_t -_mux_set_freq(clk_t* clk, freq_t hz) -{ - /* TODO: we can choose a different source... */ - clk_set_freq(clk->parent, hz); - return clk_get_freq(clk); -} - -static void -_mux_recal(clk_t* clk) -{ - assert(0); -} - -static clk_t* -_mux_init(clk_t* clk) -{ - clk_t* parent = NULL; - uint32_t mux; - enum clk_id parent_id[2]; - assert(clk); - switch (clk->id) { - case CLK_SCLKMPLL_USERC: - mux = _clk_regs[CLKREGS_CPU1]->srcstat[0] >> 24; - parent_id[0] = CLK_MASTER; - parent_id[1] = CLK_SCLKMPLL; - break; - case CLK_MUXHPM: - mux = _clk_regs[CLKREGS_CPU1]->srcstat[0] >> 20; - parent_id[0] = CLK_MOUTAPLL; - parent_id[1] = CLK_SCLKMPLL; - break; - case CLK_MUXCORE: - mux = _clk_regs[CLKREGS_CPU1]->srcstat[0] >> 16; - parent_id[0] = CLK_MOUTAPLL; - /* Tree says SCLKMPLL_USERC, Table says SCLKMPLL... */ - parent_id[1] = CLK_SCLKMPLL_USERC; -// parent_id[1] = CLK_SCLKMPLL; - break; - default: - assert(!"Unknown clock id for mux"); - return NULL; - } - mux &= MASK(4); - if (mux & 0x4) { - printf("%s is in transition\n", clk->name); - assert(0); - } - parent = clk_get_clock(clk_get_clock_sys(clk), parent_id[mux - 1]); - assert(parent); - clk_init(parent); - clk_register_child(parent, clk); - return clk; -} - -static struct clock sclk_mpll_userc_clk = { CLK_OPS(SCLKMPLL_USERC, mux, NULL) }; -static struct clock muxcore_clk = { CLK_OPS(MUXCORE, mux, NULL) }; -static struct clock muxhpm_clk = { CLK_OPS(MUXHPM, mux, NULL) }; - -/*************** - **** SPI **** - ***************/ -static freq_t -_spi_get_freq(clk_t* clk) -{ - return 0; -} - -static freq_t -_spi_set_freq(clk_t* clk, freq_t hz) -{ - (void)hz; - return clk_get_freq(clk); -} - -static void -_spi_recal(clk_t* clk) -{ - assert(0); -} - -static clk_t* -_spi_init(clk_t* clk) -{ - return clk; -} - -static struct clock spi0_clk = { CLK_OPS(SPI0, spi, NULL) }; -static struct clock spi1_clk = { CLK_OPS(SPI1, spi, NULL) }; -static struct clock spi2_clk = { CLK_OPS(SPI2, spi, NULL) }; -static struct clock spi0_isp_clk = { CLK_OPS(SPI0_ISP, spi, NULL) }; -static struct clock spi1_isp_clk = { CLK_OPS(SPI1_ISP, spi, NULL) }; - -/*******************************************/ - -static int -exynos4_gate_enable(clock_sys_t* sys, enum clock_gate gate, enum clock_gate_mode mode) -{ - (void)sys; - (void)gate; - (void)mode; - return 0; -} - -static int -clock_sys_common_init(clock_sys_t* clock_sys) -{ - clock_sys->priv = (void*)_clk_regs; - clock_sys->get_clock = &ps_get_clock; - clock_sys->gate_enable = &exynos4_gate_enable; - return 0; -} - -int -clock_sys_init(ps_io_ops_t* o, clock_sys_t* clock_sys) -{ - MAP_IF_NULL(o, CMU_LEFTBUS , _clk_regs[CLKREGS_LEFT]); - MAP_IF_NULL(o, CMU_RIGHTBUS, _clk_regs[CLKREGS_RIGHT]); - MAP_IF_NULL(o, CMU_TOP , _clk_regs[CLKREGS_TOP]); - MAP_IF_NULL(o, CMU_DMC1 , _clk_regs[CLKREGS_DMC1]); - MAP_IF_NULL(o, CMU_DMC2 , _clk_regs[CLKREGS_DMC2]); - MAP_IF_NULL(o, CMU_CPU1 , _clk_regs[CLKREGS_CPU1]); - MAP_IF_NULL(o, CMU_CPU2 , _clk_regs[CLKREGS_CPU2]); - MAP_IF_NULL(o, CMU_ISP , _clk_regs[CLKREGS_ISP]); - return clock_sys_common_init(clock_sys); -} - -void -clk_print_clock_tree(clock_sys_t* sys UNUSED) -{ - clk_t* clk = ps_clocks[CLK_MASTER]; - clk_print_tree(clk, ""); -} - -clk_t* ps_clocks[] = { - [CLK_MASTER] = &finpll_clk, - [CLK_MOUTAPLL] = &aoutpll_clk, - [CLK_SCLKMPLL] = &sclkmpll_clk, - [CLK_SCLKEPLL] = &sclkepll_clk, - [CLK_SCLKVPLL] = &sclkvpll_clk, - [CLK_SCLKAPLL] = &sclkapll_clk, - [CLK_MUXCORE] = &muxcore_clk, - [CLK_DIVCORE] = &divcore_clk, - [CLK_DIVCORE2] = &arm_clk, - [CLK_ACLK_COREM0] = &corem0_clk, - [CLK_ACLK_COREM1] = &corem1_clk, - [CLK_ACLK_CORES] = &cores_clk, - [CLK_PERIPHCLK] = &periphclk_clk, - [CLK_ATCLK] = &atclk_clk, - [CLK_PCLK_DBG] = &pclk_dbg_clk, - [CLK_SCLKMPLL_USERC] = &sclk_mpll_userc_clk, - [CLK_SCLKHPM] = &sclkhpm_clk, - [CLK_DIVCOPY] = &divcopy_clk, - [CLK_MUXHPM] = &muxhpm_clk, - [CLK_UART0] = &uart0_clk, - [CLK_UART1] = &uart1_clk, - [CLK_UART2] = &uart2_clk, - [CLK_UART3] = &uart3_clk, - [CLK_SPI0] = &spi0_clk, - [CLK_SPI1] = &spi1_clk, - [CLK_SPI2] = &spi2_clk, - [CLK_SPI0_ISP] = &spi0_isp_clk, - [CLK_SPI1_ISP] = &spi1_isp_clk, -}; - -/* These frequencies are NOT the recommended - * frequencies. They are to be used when we - * need to make assumptions about what u-boot - * has left us with. */ -freq_t ps_freq_default[] = { - [CLK_MASTER] = FINPLL_FREQ, - [CLK_MOUTAPLL] = 1000 * MHZ, - [CLK_MUXHPM] = 1000 * MHZ, - [CLK_DIVCOPY] = 200 * MHZ, - [CLK_SCLKHPM] = 200 * MHZ, - [CLK_MUXCORE] = 1000 * MHZ, - [CLK_ATCLK] = 200 * MHZ, - [CLK_PCLK_DBG] = 100 * MHZ, - [CLK_DIVCORE] = 1000 * MHZ, - [CLK_DIVCORE2] = 1000 * MHZ, - [CLK_PERIPHCLK] = 125 * MHZ, - [CLK_ACLK_COREM1] = 167 * MHZ, - [CLK_ACLK_CORES] = 250 * MHZ, - [CLK_ACLK_COREM0] = 333 * MHZ, - [CLK_UART0] = 0 * MHZ, - [CLK_UART1] = 0 * MHZ, - [CLK_UART2] = 0 * MHZ, - [CLK_UART3] = 0 * MHZ, - [CLK_SCLKAPLL] = 500 * MHZ, - [CLK_SCLKVPLL] = 108 * MHZ, - [CLK_SCLKEPLL] = 96 * MHZ, - [CLK_SCLKMPLL] = 800 * MHZ, - [CLK_SCLKMPLL_USERC] = 800 * MHZ, - /* Placeholders */ - [CLK_SPI0] = 0 * MHZ, - [CLK_SPI1] = 0 * MHZ, - [CLK_SPI2] = 0 * MHZ, - [CLK_SPI0_ISP] = 0 * MHZ, - [CLK_SPI1_ISP] = 0 * MHZ, -}; diff --git a/libplatsupport/src/plat/exynos4/mux.c b/libplatsupport/src/plat/exynos4/mux.c deleted file mode 100644 index 9514bd6fc..000000000 --- a/libplatsupport/src/plat/exynos4/mux.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#include "../../mach/exynos/mux.h" -#include - -static struct mux_feature_data i2c0_data[] = { - { .port = GPD1, .pin = 0, MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)}, - { .port = GPD1, .pin = 1, MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)}, - { .port = GPIOPORT_NONE } -}; -static struct mux_feature_data i2c1_data[] = { - { .port = GPD1, .pin = 2, MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)}, - { .port = GPD1, .pin = 3, MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)}, - { .port = GPIOPORT_NONE } -}; - -static struct mux_feature_data i2c2_data[] = { - { .port = GPA0, .pin = 6, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)}, - { .port = GPA0, .pin = 7, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)}, - { .port = GPIOPORT_NONE } -}; - -static struct mux_feature_data i2c3_data[] = { - { .port = GPA1, .pin = 2, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)}, - { .port = GPA1, .pin = 3, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)}, - { .port = GPIOPORT_NONE } -}; - -static struct mux_feature_data i2c4_data[] = { - { .port = GPB, .pin = 0, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)}, - { .port = GPB, .pin = 1, MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)}, - { .port = GPIOPORT_NONE } -}; - -static struct mux_feature_data i2c5_data[] = { - { .port = GPB, .pin = 2, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)}, - { .port = GPB, .pin = 3, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)}, - { .port = GPIOPORT_NONE } -}; - -static struct mux_feature_data i2c6_data[] = { - { .port = GPC1, .pin = 3, MUXVALUE_CPD(4, PUD_PULLUP, DRV1X)}, - { .port = GPC1, .pin = 4, MUXVALUE_CPD(4, PUD_PULLUP, DRV1X)}, - { .port = GPIOPORT_NONE } -}; - -static struct mux_feature_data i2c7_data[] = { - { .port = GPD0, .pin = 2, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)}, - { .port = GPD0, .pin = 3, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)}, - { .port = GPIOPORT_NONE } -}; - -/* SPI */ -static struct mux_feature_data spi0_data[] = { - { .port = GPB, .pin = 0, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPB, .pin = 1, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPB, .pin = 2, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPB, .pin = 3, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPIOPORT_NONE } -}; -static struct mux_feature_data spi1_data[] = { - { .port = GPB, .pin = 4, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPB, .pin = 5, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPB, .pin = 6, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPB, .pin = 7, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPIOPORT_NONE } -}; -static struct mux_feature_data spi2_data[] = { - { .port = GPC1, .pin = 1, .value = MUXVALUE_CPD(5, PUD_PULLUP, DRV3X)}, - { .port = GPC1, .pin = 2, .value = MUXVALUE_CPD(5, PUD_PULLUP, DRV3X)}, - { .port = GPC1, .pin = 3, .value = MUXVALUE_CPD(5, PUD_PULLUP, DRV3X)}, - { .port = GPC1, .pin = 4, .value = MUXVALUE_CPD(5, PUD_PULLUP, DRV3X)}, - { .port = GPIOPORT_NONE } -}; - -/* UART */ -static struct mux_feature_data uart0_data[] = { - { .port = GPA0, .pin = 0, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPA0, .pin = 1, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPIOPORT_NONE } -}; -static struct mux_feature_data uart0_flow_data[] = { - { .port = GPA0, .pin = 2, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPA0, .pin = 3, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPIOPORT_NONE } -}; -static struct mux_feature_data uart1_data[] = { - { .port = GPA0, .pin = 4, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPA0, .pin = 5, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPIOPORT_NONE } -}; -static struct mux_feature_data uart1_flow_data[] = { - { .port = GPA0, .pin = 6, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPA0, .pin = 7, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPIOPORT_NONE } -}; -static struct mux_feature_data uart2_data[] = { - { .port = GPA1, .pin = 0, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPA1, .pin = 1, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPIOPORT_NONE } -}; -static struct mux_feature_data uart2_flow_data[] = { - { .port = GPA1, .pin = 2, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPA1, .pin = 3, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPIOPORT_NONE } -}; -static struct mux_feature_data uart3_data[] = { - { .port = GPA1, .pin = 4, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPA1, .pin = 5, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPIOPORT_NONE } -}; -static struct mux_feature_data uart3_flow_data[] = { - { .port = GPA1, .pin = 6, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPA1, .pin = 7, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPIOPORT_NONE } -}; - -/* EBI */ -static struct mux_feature_data srom_data[] = { - /* SROM_CSn[3:0] */ - { .port = GPY0, .pin = 0, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY0, .pin = 1, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY0, .pin = 2, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY0, .pin = 3, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - /* SROM_WAITn */ - { .port = GPY1, .pin = 2, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - /* Terminate the list */ - { .port = GPIOPORT_NONE } -}; - -static struct mux_feature_data ebi_data[] = { - /* EBI_OEn */ - { .port = GPY0, .pin = 4, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - /* EBI_WEn */ - { .port = GPY0, .pin = 5, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - /* EBI_BE[1:0] */ - { .port = GPY1, .pin = 0, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY1, .pin = 1, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - /* EBI_ADDR[15:0] */ - { .port = GPY3, .pin = 0, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY3, .pin = 1, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY3, .pin = 2, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY3, .pin = 3, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY3, .pin = 4, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY3, .pin = 5, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY3, .pin = 6, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY3, .pin = 7, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY4, .pin = 0, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY4, .pin = 1, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY4, .pin = 2, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY4, .pin = 3, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY4, .pin = 4, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY4, .pin = 5, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY4, .pin = 6, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY4, .pin = 7, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - /* EBI_DATA[15:0] */ - { .port = GPY5, .pin = 0, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY5, .pin = 1, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY5, .pin = 2, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY5, .pin = 3, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY5, .pin = 4, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY5, .pin = 5, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY5, .pin = 6, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY5, .pin = 7, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY6, .pin = 0, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY6, .pin = 1, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY6, .pin = 2, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY6, .pin = 3, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY6, .pin = 4, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY6, .pin = 5, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY6, .pin = 6, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - { .port = GPY6, .pin = 7, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, - /* Terminate the list */ - { .port = GPIOPORT_NONE } -}; - -struct mux_feature_data* feature_data[] = { - [MUX_I2C0] = i2c0_data, - [MUX_I2C1] = i2c1_data, - [MUX_I2C2] = i2c2_data, - [MUX_I2C3] = i2c3_data, - [MUX_I2C4] = i2c4_data, - [MUX_I2C5] = i2c5_data, - [MUX_I2C6] = i2c6_data, - [MUX_I2C7] = i2c7_data, - [MUX_SPI0] = spi0_data, - [MUX_SPI1] = spi1_data, - [MUX_SPI2] = spi2_data, - [MUX_UART0] = uart0_data, - [MUX_UART1] = uart1_data, - [MUX_UART2] = uart2_data, - [MUX_UART3] = uart3_data, - [MUX_UART0_FLOW] = uart0_flow_data, - [MUX_UART1_FLOW] = uart1_flow_data, - [MUX_UART2_FLOW] = uart2_flow_data, - [MUX_UART3_FLOW] = uart3_flow_data, - [MUX_EBI] = ebi_data, - [MUX_SROM] = srom_data, -}; diff --git a/libplatsupport/src/plat/exynos4/src.c b/libplatsupport/src/plat/exynos4/src.c deleted file mode 100644 index 9a633baeb..000000000 --- a/libplatsupport/src/plat/exynos4/src.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ -#include -#include "../../services.h" - -/** PWRREG **/ -#define PWRREG_PHY_CONTROL_OFFSET 0x708 -#define PWRREG_PHY_CONTROL_PHY_EN BIT(0) -#define PWRREG_SWRST_OFFSET 0x400 -#define PWRREG_SWRST BIT(0) - -/** SYSREG **/ -#define SYSREG_PHY_CONFIG_OFFSET 0x230 -#define SYSREG_PHY_CONFIG_PHY_EN BIT(0) - -struct src_priv { - void* sysreg_vaddr[1]; - void* pwrreg_vaddr[5]; -}; - -struct src_priv _src_priv; - -static inline struct src_priv* -src_get_priv(src_dev_t* d) { - return (struct src_priv*)d->priv; -} - -static inline volatile uint32_t* -sreg(struct src_priv* src, int offset) -{ - void* reg = src->sysreg_vaddr[offset >> 12] + (offset & MASK(12)); - return (volatile uint32_t*)reg; -} - -static inline volatile uint32_t* -preg(struct src_priv* src, int offset) -{ - void* reg_base; - reg_base = src->pwrreg_vaddr[offset >> 12]; - if (reg_base) { - return (volatile uint32_t*)(reg_base + (offset & MASK(12))); - } else { - return NULL; - } -} - -int -sysreg_usbphy_enable(src_dev_t* dev) -{ - volatile uint32_t* a; - struct src_priv* priv = src_get_priv(dev); - a = sreg(priv, SYSREG_PHY_CONFIG_OFFSET); - if (a) { - *a |= SYSREG_PHY_CONFIG_PHY_EN; - } - a = preg(priv, PWRREG_PHY_CONTROL_OFFSET); - if (a) { - *a |= PWRREG_PHY_CONTROL_PHY_EN; - } - return 0; -} - -int -sysreg_swrst_enable(src_dev_t* dev) -{ - struct src_priv* priv = src_get_priv(dev); - volatile uint32_t* a; - a = preg(priv, PWRREG_SWRST_OFFSET); - if (a) { - LOG_INFO("Software reset triggered"); - fflush(stdout); - *a = PWRREG_SWRST; - while (1); - } - return 0; -} - -void -reset_controller_assert_reset(src_dev_t* dev, enum src_rst_id id) -{ - switch (id) { - case SRCRST_SW_RST: - sysreg_swrst_enable(dev); - break; - case SRCRST_USBPHY_EN: - sysreg_usbphy_enable(dev); - break; - default: - LOG_ERROR("Invalid option: %d", id); - } -} - -int -reset_controller_init(enum src_id id, ps_io_ops_t* ops, src_dev_t* dev) -{ - struct src_priv* src_priv = &_src_priv; - int i; - /* Sanity check the provided ID */ - if (id < 0 || id >= NSRC) { - return -1; - } - /* Map sysreg memory */ - for (i = 0; i < EXYNOS_SYSREG_SIZE >> 12; i++) { - if (src_priv->sysreg_vaddr[i] == NULL) { - void *vaddr; - vaddr = ps_io_map(&ops->io_mapper, - EXYNOS_SYSREG_PADDR + i * BIT(12), - 0x1000, 0, PS_MEM_NORMAL); - src_priv->sysreg_vaddr[i] = vaddr; - } - } - /* Map pmu memory */ - for (i = 0; i < EXYNOS_PMU_SIZE >> 12; i++) { - if (src_priv->pwrreg_vaddr[i] == NULL) { - void *vaddr; - vaddr = ps_io_map(&ops->io_mapper, - EXYNOS_PMU_PADDR + i * BIT(12), - 0x1000 , 0, PS_MEM_NORMAL); - - src_priv->pwrreg_vaddr[i] = vaddr; - } - } - /* Assign private data */ - dev->priv = src_priv; - return 0; -} diff --git a/libplatsupport/src/plat/fvp/serial.c b/libplatsupport/src/plat/fvp/serial.c index 5b8db1ad3..b8c0f1313 100644 --- a/libplatsupport/src/plat/fvp/serial.c +++ b/libplatsupport/src/plat/fvp/serial.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-2-Clause */ -/* Mostly copy/paste from the HiKey plat. +/* Mostly copy/paste from the (removed) HiKey plat. * Should be moved to a common driver file for PL011 */ #include @@ -32,7 +32,7 @@ int uart_getchar(ps_chardevice_t *d) return ch; } -int uart_putchar(ps_chardevice_t* d, int c) +int uart_putchar(ps_chardevice_t *d, int c) { while ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_TXFF) != 0); @@ -44,25 +44,24 @@ int uart_putchar(ps_chardevice_t* d, int c) return c; } -static void -uart_handle_irq(ps_chardevice_t* dev) +static void uart_handle_irq(ps_chardevice_t *dev) { *REG_PTR(dev->vaddr, UARTICR) = 0x7f0; } -int uart_init(const struct dev_defn* defn, - const ps_io_ops_t* ops, - ps_chardevice_t* dev) +int uart_init(const struct dev_defn *defn, + const ps_io_ops_t *ops, + ps_chardevice_t *dev) { memset(dev, 0, sizeof(*dev)); - void* vaddr = chardev_map(defn, ops); + void *vaddr = chardev_map(defn, ops); if (vaddr == NULL) { return -1; } /* Set up all the device properties. */ dev->id = defn->id; - dev->vaddr = (void*)vaddr; + dev->vaddr = (void *)vaddr; dev->read = &uart_read; dev->write = &uart_write; dev->handle_irq = &uart_handle_irq; diff --git a/libplatsupport/src/plat/fvp/sp804.c b/libplatsupport/src/plat/fvp/sp804.c index b2d860989..afbc69e00 100644 --- a/libplatsupport/src/plat/fvp/sp804.c +++ b/libplatsupport/src/plat/fvp/sp804.c @@ -14,10 +14,7 @@ #include "../../ltimer.h" -/* This file is mostly the same as the dmt.c file for the hikey. - * Consider to merge the two files as a single driver file for - * SP804. - */ +/* Driver for the SP804 dual timer. */ #define TCLR_ONESHOT BIT(0) #define TCLR_VALUE_32 BIT(1) diff --git a/libplatsupport/src/plat/hikey/chardev.c b/libplatsupport/src/plat/hikey/chardev.c deleted file mode 100644 index 71cc0f9de..000000000 --- a/libplatsupport/src/plat/hikey/chardev.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -/** - * Contains the definition for all character devices on this platform. - * Currently this is just a simple patch. - */ - -#include "../../chardev.h" -#include "../../common.h" -#include - -#include "../../chardev.h" - -static const int uart0_irqs[] = {UART0_IRQ, -1}; -static const int uart1_irqs[] = {UART1_IRQ, -1}; -static const int uart2_irqs[] = {UART2_IRQ, -1}; -static const int uart3_irqs[] = {UART3_IRQ, -1}; -static const int uart4_irqs[] = {UART4_IRQ, -1}; - -#define UART_DEFN(devid) { \ - .id = DM_UART##devid, \ - .paddr = UART##devid##_PADDR, \ - .size = BIT(12), \ - .irqs = uart##devid##_irqs, \ - .init_fn = &uart_init \ -} - -static const struct dev_defn dev_defn[] = { - UART_DEFN(0), - UART_DEFN(1), - UART_DEFN(2), - UART_DEFN(3), - UART_DEFN(4), -}; - -struct ps_chardevice* -ps_cdev_init(enum chardev_id id, const ps_io_ops_t* o, struct ps_chardevice* d) { - unsigned int i; - for (i = 0; i < ARRAY_SIZE(dev_defn); i++) { - if (dev_defn[i].id == id) { - return (dev_defn[i].init_fn(dev_defn + i, o, d)) ? NULL : d; - } - } - return NULL; -} diff --git a/libplatsupport/src/plat/hikey/dmt.c b/libplatsupport/src/plat/hikey/dmt.c deleted file mode 100644 index 26f83ca6a..000000000 --- a/libplatsupport/src/plat/hikey/dmt.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include "../../ltimer.h" - -/* Driver for the HiSilison hi6220 hikey Dual-timer devices. - * - * There are 9 timer devices, each implementing two downcounters for a total - * of 18 downcounters. These downcounters run at 19.2MHz. - * - * The 9 timer devices each have their own physical frame address, but the - * 2 downcounters for each device reside in the same 4K frame. - * - * We have numbered the downcounters from 0-17 as distinct logical devices. - */ - -#define TCLR_ONESHOT BIT(0) -#define TCLR_VALUE_32 BIT(1) -#define TCLR_INTENABLE BIT(5) -#define TCLR_AUTORELOAD BIT(6) -#define TCLR_STARTTIMER BIT(7) -#define TICKS_PER_SECOND 19200000 -#define TICKS_PER_MS (TICKS_PER_SECOND / MS_IN_S) - -#define HIKEY_DUALTIMER_SECONDARY_TIMER_OFFSET (0x20) - -static void dmt_timer_reset(dmt_t *dmt) -{ - assert(dmt != NULL && dmt->dmt_map != NULL); - dmt_regs_t *dmt_regs = dmt->dmt_map; - dmt_regs->control = 0; - - dmt->time_h = 0; -} - -int dmt_stop(dmt_t *dmt) -{ - if (dmt == NULL) { - return EINVAL; - } - assert(dmt != NULL && dmt->dmt_map != NULL); - dmt_regs_t *dmt_regs = dmt->dmt_map; - dmt_regs->control = dmt_regs->control & ~TCLR_STARTTIMER; - return 0; -} - -int dmt_start(dmt_t *dmt) -{ - if (dmt == NULL) { - return EINVAL; - } - assert(dmt != NULL && dmt->dmt_map != NULL); - dmt_regs_t *dmt_regs = dmt->dmt_map; - dmt_regs->control = dmt_regs->control | TCLR_STARTTIMER; - return 0; -} - -uint64_t dmt_ticks_to_ns(uint64_t ticks) -{ - return ticks / TICKS_PER_MS * NS_IN_MS; -} - -bool dmt_is_irq_pending(dmt_t *dmt) -{ - if (dmt) { - assert(dmt != NULL && dmt->dmt_map != NULL); - return !!dmt->dmt_map->ris; - } - return false; -} - -int dmt_set_timeout(dmt_t *dmt, uint64_t ns, bool periodic, bool irqs) -{ - uint64_t ticks64 = ns * TICKS_PER_MS / NS_IN_MS; - if (ticks64 > UINT32_MAX) { - return ETIME; - } - return dmt_set_timeout_ticks(dmt, ticks64, periodic, irqs); -} - -int dmt_set_timeout_ticks(dmt_t *dmt, uint32_t ticks, bool periodic, bool irqs) -{ - if (dmt == NULL) { - return EINVAL; - } - assert(dmt != NULL && dmt->dmt_map != NULL); - - int flags = periodic ? TCLR_AUTORELOAD : TCLR_ONESHOT; - flags |= irqs ? TCLR_INTENABLE : 0; - - dmt_regs_t *dmt_regs = dmt->dmt_map; - dmt_regs->control = 0; - - /* No need to check for ticks == 0, because 0 is a valid value: - * - * Hikey Application Processor Function Description, section 2.3, "TIMERN_LOAD": - * "The minimum valid value of TIMERN_LOAD is 1. If 0 is written to TIMERN_LOAD, a - * timing interrupt is generated immediately." - * - * If the user supplies 0 as the argument, they'll just get an IRQ - * immediately. - */ - if (flags & TCLR_AUTORELOAD) { - /* Hikey Application Processor Function Description, section 2.3, "TIMERN_BGLOAD": - * "TIMERN_BGLOAD is an initial count value register in periodic mode. - * - * In periodic mode, when the value of TIMERN_BGLOAD is updated, the - * value of TIMERN_LOAD is changed to that of TIMERN_BGLOAD. However, - * the timer counter does not restart counting. After the counter - * decreases to 0, the value of TIMERN_LOAD (that is, - * the value of TIMERN_BGLOAD) is reloaded to the counter. - * dmt->regs->bgload = ticks; - * - * In other words, for periodic mode, load BGLOAD first, then write to - * LOAD. For oneshot mode, only write to LOAD. For good measure, write 0 - * to BGLOAD. - */ - dmt_regs->bgload = ticks; - } else { - dmt_regs->bgload = 0; - } - dmt_regs->load = ticks; - - /* The TIMERN_VALUE register is read-only. */ - dmt_regs->control = TCLR_STARTTIMER | TCLR_VALUE_32 - | flags; - - return 0; -} - -static void dmt_handle_irq(void *data, ps_irq_acknowledge_fn_t acknowledge_fn, void *ack_data) -{ - assert(data != NULL); - dmt_t *dmt = data; - - /* if we are being used for timestamps */ - if (dmt->user_cb_event == LTIMER_OVERFLOW_EVENT) { - dmt->time_h++; - } - - assert(dmt->dmt_map != NULL); - dmt_regs_t *dmt_regs = dmt->dmt_map; - dmt_regs->intclr = 0x1; - - ZF_LOGF_IF(acknowledge_fn(ack_data), "Failed to acknowledge the timer's interrupts"); - if (dmt->user_cb_fn) { - dmt->user_cb_fn(dmt->user_cb_token, dmt->user_cb_event); - } -} - -uint64_t dmt_get_ticks(dmt_t *dmt) -{ - assert(dmt != NULL && dmt->dmt_map != NULL); - dmt_regs_t *dmt_regs = dmt->dmt_map; - return dmt_regs->value; -} - -uint64_t dmt_get_time(dmt_t *dmt) -{ - uint32_t high, low; - - /* timer must be being used for timekeeping */ - assert(dmt->user_cb_event == LTIMER_OVERFLOW_EVENT); - - /* dmt is a down counter, invert the result */ - high = dmt->time_h; - low = UINT32_MAX - dmt_get_ticks(dmt); - - /* check after fetching low to see if we've missed a high bit */ - if (dmt_is_irq_pending(dmt)) { - high += 1; - assert(high != 0); - } - - uint64_t ticks = (((uint64_t) high << 32llu) | low); - return dmt_ticks_to_ns(ticks); -} - -void dmt_destroy(dmt_t *dmt) -{ - int error; - if (dmt->irq_id != PS_INVALID_IRQ_ID) { - error = ps_irq_unregister(&dmt->ops.irq_ops, dmt->irq_id); - ZF_LOGF_IF(error, "Failed to unregister IRQ"); - } - if (dmt->dmt_map != NULL) { - dmt_stop(dmt); - } - if (dmt->dmt_map_base != NULL) { - /* use base because dmt_map is adjusted based on whether secondary */ - ps_pmem_unmap(&dmt->ops, dmt->pmem, (void *) dmt->dmt_map_base); - } -} - -int dmt_init(dmt_t *dmt, ps_io_ops_t ops, dmt_config_t config) -{ - int error; - - if (dmt == NULL) { - ZF_LOGE("dmt cannot be null"); - return EINVAL; - } - - dmt->ops = ops; - dmt->user_cb_fn = config.user_cb_fn; - dmt->user_cb_token = config.user_cb_token; - dmt->user_cb_event = config.user_cb_event; - - error = helper_fdt_alloc_simple( - &ops, config.fdt_path, - DMT_REG_CHOICE, DMT_IRQ_CHOICE, - &dmt->dmt_map_base, &dmt->pmem, &dmt->irq_id, - dmt_handle_irq, dmt - ); - if (error) { - ZF_LOGE("Simple fdt alloc helper failed"); - return error; - } - - dmt->dmt_map = dmt->dmt_map_base; - - dmt_timer_reset(dmt); - return 0; -} - -/* initialise dmt using the base address of dmtp, so that we do not attempt to map - * that base address again but instead re-use it. */ -int dmt_init_secondary(dmt_t *dmt, dmt_t *dmtp, ps_io_ops_t ops, dmt_config_t config) -{ - int error; - - if (dmt == NULL || dmtp == NULL) { - ZF_LOGE("dmt or dmtp cannot be null"); - return EINVAL; - } - - dmt->ops = ops; - dmt->user_cb_fn = config.user_cb_fn; - dmt->user_cb_token = config.user_cb_token; - dmt->user_cb_event = config.user_cb_event; - - /* so that destroy does not try to unmap twice */ - dmt->dmt_map_base = NULL; - /* First sub-device is at offset 0, second sub-device is - * at offset 0x20 within the same page. */ - dmt->dmt_map = (void *)((uintptr_t) dmtp->dmt_map_base) + HIKEY_DUALTIMER_SECONDARY_TIMER_OFFSET; - dmt->irq_id = PS_INVALID_IRQ_ID; - - /* Gather FDT info */ - ps_fdt_cookie_t *cookie = NULL; - error = ps_fdt_read_path(&ops.io_fdt, &ops.malloc_ops, config.fdt_path, &cookie); - if (error) { - ZF_LOGE("Failed to read path (%d, %s)", error, config.fdt_path); - return error; - } - - /* choose irq 1 because secondary */ - irq_id_t irq_id = ps_fdt_index_register_irq(&ops, cookie, 1, dmt_handle_irq, dmt); - if (irq_id <= PS_INVALID_IRQ_ID) { - ZF_LOGE("Failed to register irqs (%d)", irq_id); - return irq_id; - } - - error = ps_fdt_cleanup_cookie(&ops.malloc_ops, cookie); - if (error) { - ZF_LOGE("Failed to clean up cookie (%d)", error); - return error; - } - - dmt->irq_id = irq_id; - - dmt_timer_reset(dmt); - return 0; -} diff --git a/libplatsupport/src/plat/hikey/ltimer.c b/libplatsupport/src/plat/hikey/ltimer.c deleted file mode 100644 index 355d2647e..000000000 --- a/libplatsupport/src/plat/hikey/ltimer.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include "../../ltimer.h" - -/* - * We use two dm timers: one to keep track of an absolute time, the other for timeouts. - */ -/* hikey dualtimers have 2 timers per frame, we just use one from each */ -typedef struct { - dmt_t dmt_timeout; - dmt_t dmt_timestamp; - ps_io_ops_t ops; -} hikey_ltimer_t; - -static int get_time(void *data, uint64_t *time) -{ - hikey_ltimer_t *hikey_ltimer = data; - assert(data != NULL); - assert(time != NULL); - - *time = dmt_get_time(&hikey_ltimer->dmt_timestamp); - return 0; -} - -int set_timeout(void *data, uint64_t ns, timeout_type_t type) -{ - if (type == TIMEOUT_ABSOLUTE) { - uint64_t time; - int error = get_time(data, &time); - if (error) { - return error; - } - if (time > ns) { - return ETIME; - } - ns -= time; - } - - hikey_ltimer_t *hikey_ltimer = data; - return dmt_set_timeout(&hikey_ltimer->dmt_timeout, ns, type == TIMEOUT_PERIODIC, true); -} - -static int reset(void *data) -{ - hikey_ltimer_t *hikey_ltimer = data; - /* restart the rtc */ - dmt_stop(&hikey_ltimer->dmt_timeout); - dmt_start(&hikey_ltimer->dmt_timeout); - return 0; -} - -static void destroy(void *data) -{ - assert(data != NULL); - hikey_ltimer_t *hikey_ltimer = data; - /* NOTE: Note that timeout is primary, timestamp is secondary. - * this means that timeout holds the region mapping. - * We must first destroy timestamp before destroying timeout - * so that the region is freed last. */ - dmt_destroy(&hikey_ltimer->dmt_timestamp); - dmt_destroy(&hikey_ltimer->dmt_timeout); - ps_free(&hikey_ltimer->ops.malloc_ops, sizeof(hikey_ltimer_t), hikey_ltimer); -} - -int ltimer_default_init(ltimer_t *ltimer, ps_io_ops_t ops, ltimer_callback_fn_t callback, void *callback_token) -{ - int error; - - if (ltimer == NULL) { - ZF_LOGE("ltimer cannot be NULL"); - return EINVAL; - } - - error = create_ltimer_simple( - ltimer, ops, sizeof(hikey_ltimer_t), - get_time, set_timeout, reset, destroy - ); - if (error) { - ZF_LOGE("Failed to create ltimer for hikey"); - return error; - } - - hikey_ltimer_t *hikey_ltimer = ltimer->data; - hikey_ltimer->ops = ops; - - /* set up a DMT for timeouts */ - dmt_config_t dmt_config = { - .fdt_path = DMT_PATH, - .user_cb_fn = callback, - .user_cb_token = callback_token, - .user_cb_event = LTIMER_TIMEOUT_EVENT - }; - - error = dmt_init(&hikey_ltimer->dmt_timeout, ops, dmt_config); - if (error) { - ZF_LOGE("Failed to init dmt timeout timer"); - destroy(hikey_ltimer); - return error; - } - - error = dmt_start(&hikey_ltimer->dmt_timeout); - if (error) { - ZF_LOGE("Failed to start dmt timeout timer"); - destroy(hikey_ltimer); - return error; - } - - /* set up a DMT for timestamps */ - dmt_config.user_cb_event = LTIMER_OVERFLOW_EVENT; - - error = dmt_init_secondary(&hikey_ltimer->dmt_timestamp, &hikey_ltimer->dmt_timeout, ops, dmt_config); - if (error) { - ZF_LOGE("Failed to init dmt secondary for timestamps"); - destroy(hikey_ltimer); - return error; - } - - error = dmt_start(&hikey_ltimer->dmt_timestamp); - if (error) { - ZF_LOGE("Failed to start dmt timestamp timer"); - destroy(hikey_ltimer); - return error; - } - - error = dmt_set_timeout_ticks(&hikey_ltimer->dmt_timestamp, UINT32_MAX, true, true); - if (error) { - ZF_LOGE("Failed to set ticks for dmt timestamp timer"); - destroy(hikey_ltimer); - return error; - } - - return 0; -} - -/* This function is intended to be deleted, - * this is just left here for now so that stuff can compile */ -int ltimer_default_describe(ltimer_t *ltimer, ps_io_ops_t ops) -{ - ZF_LOGE("get_(nth/num)_(irqs/pmems) are not valid"); - return EINVAL; -} diff --git a/libplatsupport/src/plat/hikey/rtc.c b/libplatsupport/src/plat/hikey/rtc.c deleted file mode 100644 index 51d06a70f..000000000 --- a/libplatsupport/src/plat/hikey/rtc.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#include -#include -#include - -#include -#include - -#include - -#define HIKEY_RTCCR_ENABLE_SHIFT (0) - -typedef volatile struct rtc_regs { - uint32_t rtcdr; /* Data reg: RO: returns current value of 1Hz upcounter */ - uint32_t rtcmr; /* Comparison reg: RW: for the alarm (irq) feature. - * Generates an IRQ when rtcmr == rtcdr. - * Don't care: we don't use the alarm feature. - */ - uint32_t rtclr; /* Load reg: RW: the initial value of the upcounter. */ - uint32_t rtccr; /* Control reg: literally only has an enable bit (bit 0) - * and that's it. Absolute control. - */ - uint32_t rtcimsc; /* Interrupt mask reg: Don't care. we don't use the alarm - * feature. - */ - uint32_t rtcris; /* Raw Interrupt status reg: don't care. */ - uint32_t rtcmis; /* Masked interrupt status reg: don't care. */ - uint32_t rtcicr; /* interrupt clear reg: don't care. */ -} rtc_regs_t; - -static inline rtc_regs_t * -rtc_get_regs(rtc_t *rtc) -{ - assert(rtc != NULL); - assert(rtc->vaddr != NULL); - return rtc->vaddr; -} - -int rtc_start(rtc_t *rtc) -{ - rtc_regs_t *regs = rtc_get_regs(rtc); - - /* We set the initial value of the upcounter to 0 when - * initializing, because we have no reason to use any - * other value, and because we have no guarantee that - * it starts at a sensibly low value if not explicitly set. - */ - regs->rtclr = 0; - regs->rtccr = BIT(HIKEY_RTCCR_ENABLE_SHIFT); - return 0; -} - -int rtc_stop(rtc_t *rtc) -{ - rtc_regs_t *regs = rtc_get_regs(rtc); - regs->rtccr = 0; - return 0; -} - -uint32_t rtc_get_time(rtc_t *rtc) -{ - rtc_regs_t *regs = rtc_get_regs(rtc); - return regs->rtcdr; -} - -int rtc_init(rtc_t *rtc, rtc_config_t config) -{ - if (config.id < RTC0 || config.id > RTC1) { - ZF_LOGE("Invalid timer device ID for a hikey RTC timer."); - return EINVAL; - } - - if (config.vaddr == NULL) { - ZF_LOGE("Vaddr of the mapped RTC device register frame is required."); - return EINVAL; - } - - rtc->vaddr = config.vaddr; - return 0; -} diff --git a/libplatsupport/src/plat/hikey/serial.c b/libplatsupport/src/plat/hikey/serial.c deleted file mode 100644 index e9f30d70b..000000000 --- a/libplatsupport/src/plat/hikey/serial.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#include -#include -#include -#include "../../chardev.h" - -#define RHR_MASK MASK(8) -#define UARTDR 0x000 -#define UARTFR 0x018 -#define UARTIMSC 0x038 -#define UARTICR 0x044 -#define PL011_UARTFR_TXFF BIT(5) -#define PL011_UARTFR_RXFE BIT(4) - -#define REG_PTR(base, off) ((volatile uint32_t *)((base) + (off))) - -int uart_getchar(ps_chardevice_t *d) -{ - int ch = EOF; - - if ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_RXFE) == 0) { - ch = *REG_PTR(d->vaddr, UARTDR) & RHR_MASK; - } - return ch; -} - -int uart_putchar(ps_chardevice_t* d, int c) -{ - while ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_TXFF) != 0); - - *REG_PTR(d->vaddr, UARTDR) = c; - if (c == '\n' && (d->flags & SERIAL_AUTO_CR)) { - uart_putchar(d, '\r'); - } - - return c; -} - -static void -uart_handle_irq(ps_chardevice_t* dev) -{ - *REG_PTR(dev->vaddr, UARTICR) = 0x7f0; -} - -int uart_init(const struct dev_defn* defn, - const ps_io_ops_t* ops, - ps_chardevice_t* dev) -{ - memset(dev, 0, sizeof(*dev)); - void* vaddr = chardev_map(defn, ops); - if (vaddr == NULL) { - return -1; - } - - /* Set up all the device properties. */ - dev->id = defn->id; - dev->vaddr = (void*)vaddr; - dev->read = &uart_read; - dev->write = &uart_write; - dev->handle_irq = &uart_handle_irq; - dev->irqs = defn->irqs; - dev->ioops = *ops; - dev->flags = SERIAL_AUTO_CR; - - *REG_PTR(dev->vaddr, UARTIMSC) = 0x50; - return 0; -} diff --git a/libplatsupport/src/plat/qemu-arm-virt/serial.c b/libplatsupport/src/plat/qemu-arm-virt/serial.c index 47b665e16..b8c0f1313 100644 --- a/libplatsupport/src/plat/qemu-arm-virt/serial.c +++ b/libplatsupport/src/plat/qemu-arm-virt/serial.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-2-Clause */ -/* Mostly copy/paste from the HiKey plat. +/* Mostly copy/paste from the (removed) HiKey plat. * Should be moved to a common driver file for PL011 */ #include