From 7493e37729e6c95221e03abf8e52b6953cdd2d2f Mon Sep 17 00:00:00 2001 From: Claude Date: Sat, 26 Sep 2026 16:11:20 +0000 Subject: [PATCH] Bump DspTap to 0eb09fa and SampleRateTap to 2b4dff1; re-record icount DspTap #38 shares the Kaiser window's Bessel series across the prototype design (bit-identical coefficients). RatioTap designs at construction for every profile, so every workload's construction got cheaper: per profile and direction, identical across float/Q15/Q31 -- M33 -37..-299 M, Hexagon -4.7..-35 M, M55 -0.6..-4.6 M. Ten M33 and eight Hexagon scenarios left the two-sided gate (M33 down_q15_eco -28.9%); baselines re-recorded on all three targets. The test-only sampleratetap pin moves in step (no header changes in 5315689..2b4dff1) so both repos keep the identical dsptap tree the dev-only include path relies on. PLAN.md: M7e ledger entry, and a correction. M7c deferred coefficient baking because "construction is <0.3% of every workload"; a construct-only measurement of every scenario shows 3-5% on M55, 5-37% on Hexagon and up to 63% of the M33 Q15 workloads (74% before this change), which dilutes the M33 gate for hot-path regressions ~2-3x. Host: 78/78 under GCC and clang with TAP_RATIO_WERROR; scripts/tidy.sh clean. Co-Authored-By: Claude Opus 5.5 Claude-Session: https://claude.ai/code/session_01G3HxzEGiZp7jStoMuYNuBK --- PLAN.md | 37 +++++++++++++++++++++++-- bench/baselines.json | 60 ++++++++++++++++++++-------------------- submodules/dsptap | 2 +- submodules/sampleratetap | 2 +- 4 files changed, 66 insertions(+), 35 deletions(-) diff --git a/PLAN.md b/PLAN.md index 3812c48..60d62ad 100644 --- a/PLAN.md +++ b/PLAN.md @@ -264,9 +264,13 @@ executed (it measures the shipping C++, not a Python re-implementation). scenarios stay loop-shaped and flat), **M33 Q15 −2.6/−3.4%**; float everywhere within noise of flat (soft-double MAC bound on M33, FP64 chain bound on M55). Coefficient *baking* (committed tables in rodata) - remains un-pulled: construction is <0.3% of every workload, so its - value is boot time and RAM on MCUs, not instruction counts — deferred - until a consumer needs it. + remains un-pulled — deferred until a consumer needs it. (This entry + first justified the deferral with "construction is <0.3% of every + workload"; measured directly on 2026-09-26 it is not — see the M7e + entry: 3–5% on M55, 5–37% on Hexagon, and on M33 up to 63% of the Q15 + workloads, 74% before the shared-window change. Baking would therefore + move the M33/Hexagon fixed-point counts a lot, while the audio path it + leaves untouched is what the ratchet is meant to watch.) - **M7d — polyphase symmetry storage halving (landed).** Lever 3, in two PRs per the substrate discipline: `tap::dsp::dot_row_reversed` landed in DspTap first (hist forward × row backward, SMLALDX swapped-lane @@ -285,6 +289,33 @@ executed (it measures the shipping C++, not a Python re-implementation). (TAP_RATIO_MIRRORED_DOT_ATTR), the same measured-per-target pattern as the tap::dsp kernel gates. Worst residual rides inside the ±3% gate (Hexagon down_q31 +2.7%); Arm came out slightly ahead (M33 Q31 −2.5%). + - **M7e — DspTap pin 28a34a1 → 0eb09fa: shared Kaiser-window Bessel + series (re-record, not a lever).** DspTap #38 evaluates the window's + `bessel_i0` series once for half the taps and mirrors it — the design + evaluated it per tap. Coefficients bit-identical (FNV-1a-64 over the + whole prototype on M33 and on x86 under GCC and clang; scipy vectors + and the cross-validation floors unmoved, 78/78 host tests), so only + construction moved: per profile × direction and identical across + float/Q15/Q31 (down economy −70.7 M on M33 in all three formats), + M33 −37…−299 M, Hexagon −4.7…−35 M, M55 −0.6…−4.6 M. That took ten + of ten M33 scenarios and eight of ten Hexagon scenarios past the + two-sided gate (M33 down_q15_eco −28.9%); baselines re-recorded on all + three targets (M55 moved −1.0…−2.1%, re-recorded to keep the gate + tight). The sampleratetap test pin moves with it (5315689 → 2b4dff1, + no header changes in that range) so both repos keep the identical + dsptap tree the dev-only include path relies on. + Measuring the delta exposed how much of each workload construction is. + A construct-only build of every scenario, after the change (before in + parentheses): M55 3–5% (4–6%); Hexagon float 5–6% (8–10%), fixed + point 32–37% (42–47%); M33 float 6–8% (10–12%), Q31 42–45% (55–57%), + **Q15 55–63% (67–74%)**. So on M33 the fixed-point baselines mostly + price the constructor, and a hot-path regression there is diluted + ~2–3× before the ±3% gate sees it; the per-lever M33 percentages + above were measured through the same dilution (the audio-path + improvements were correspondingly larger). A construct-only ratchet + scenario, or measuring a second workload length and differencing as + SampleRateTap now does (steady state = 4 s − 2 s), would restore the + gate's sensitivity. v0.1 ships at M6. Nothing in M7+ blocks it. **v0.3 (2026-08-07): the profile-ladder re-pin.** economy moved to the 18 kHz/58/38 design (the diff --git a/bench/baselines.json b/bench/baselines.json index 7050f56..e5c5cea 100644 --- a/bench/baselines.json +++ b/bench/baselines.json @@ -1,38 +1,38 @@ { "hexagon": { - "down_float_eco": 313564771, - "down_float_tr": 979598163, - "down_q15_eco": 54576857, - "down_q15_se": 39378689, - "down_q31_eco": 54524022, - "up_float_eco": 226581827, - "up_float_tr": 553818763, - "up_q15_eco": 42340774, - "up_q15_se": 32106712, - "up_q31_eco": 42358271 + "down_float_eco": 304640233, + "down_float_tr": 944369106, + "down_q15_eco": 45680933, + "down_q15_se": 33239067, + "down_q31_eco": 45626536, + "up_float_eco": 220218304, + "up_float_tr": 533814335, + "up_q15_eco": 35994330, + "up_q15_se": 27428012, + "up_q31_eco": 36011772 }, "m33": { - "down_float_eco": 1791425947, - "down_float_tr": 5772164016, - "down_q15_eco": 244450483, - "down_q15_se": 179742418, - "down_q31_eco": 315684738, - "up_float_eco": 1282189491, - "up_float_tr": 3280145822, - "up_q15_eco": 184359117, - "up_q15_se": 140538142, - "up_q31_eco": 235400465 + "down_float_eco": 1720707553, + "down_float_tr": 5473297976, + "down_q15_eco": 173755176, + "down_q15_se": 130967926, + "down_q31_eco": 244985862, + "up_float_eco": 1231730349, + "up_float_tr": 3110380470, + "up_q15_eco": 133914472, + "up_q15_se": 103390933, + "up_q31_eco": 184954171 }, "m55": { - "down_float_eco": 74885193, - "down_float_tr": 219532760, - "down_q15_eco": 58251264, - "down_q15_se": 47710153, - "down_q31_eco": 97748073, - "up_float_eco": 56229455, - "up_float_tr": 128890219, - "up_q15_eco": 45305070, - "up_q15_se": 39607853, - "up_q31_eco": 73399258 + "down_float_eco": 73794800, + "down_float_tr": 214977684, + "down_q15_eco": 57208782, + "down_q15_se": 46983269, + "down_q31_eco": 96697327, + "up_float_eco": 55451902, + "up_float_tr": 126303581, + "up_q15_eco": 44556679, + "up_q15_se": 39050794, + "up_q31_eco": 72647042 } } diff --git a/submodules/dsptap b/submodules/dsptap index 28a34a1..0eb09fa 160000 --- a/submodules/dsptap +++ b/submodules/dsptap @@ -1 +1 @@ -Subproject commit 28a34a18c40bda74b5d8cea0c54e09f31fbdc94b +Subproject commit 0eb09fa1edf5ce4f83043a05ce04ed8f3a653dbc diff --git a/submodules/sampleratetap b/submodules/sampleratetap index 5315689..2b4dff1 160000 --- a/submodules/sampleratetap +++ b/submodules/sampleratetap @@ -1 +1 @@ -Subproject commit 53156897a5afe5de4967dd33a9db5fba159dfeaf +Subproject commit 2b4dff17abd095dd01d72055a69a4385a64b2304