rtl.yml

name: RTL CI

on:
  push:
    paths: ['rtl/**', 'sim/**', 'sw/**', '.tools/riscv-gcc.sh', '.gitmodules', '.github/workflows/rtl.yml']
  pull_request:
    paths: ['rtl/**', 'sim/**', 'sw/**', '.tools/riscv-gcc.sh', '.gitmodules', '.github/workflows/rtl.yml']

jobs:
  rtl-ci:
    runs-on: ubuntu-24.04

    steps:
      - uses: actions/checkout@v4
        with:
          submodules: true   # sw/riscv-tests

      # cocotb 2.x needs Verilator >= 5.036; the ubuntu-24.04 apt package is older,
      # so build from source and cache by version tag.
      - name: Cache Verilator build
        id: cache-verilator
        uses: actions/cache@v4
        with:
          path: ~/verilator-install
          key: verilator-v5.036-ubuntu-24.04

      - name: Build Verilator v5.036 from source
        if: steps.cache-verilator.outputs.cache-hit != 'true'
        run: |
          sudo apt-get update -qq
          sudo apt-get install -y autoconf flex bison libfl2 libfl-dev help2man perl
          git clone --depth 1 --branch v5.036 https://github.com/verilator/verilator.git /tmp/verilator
          cd /tmp/verilator
          autoconf
          ./configure --prefix="$HOME/verilator-install"
          make -j$(nproc)
          make install

      - name: Add Verilator to PATH
        run: echo "$HOME/verilator-install/bin" >> $GITHUB_PATH

      - uses: actions/setup-python@v5
        with:
          python-version: '3.12'

      - name: Install Python deps
        run: pip install -r sim/requirements.txt

      - name: Cache RISC-V GCC
        uses: actions/cache@v4
        with:
          path: .tools/riscv-gcc
          key: riscv-gcc-xpack-15.2.0-1-linux-x64

      - name: Install RISC-V GCC
        run: bash .tools/riscv-gcc.sh

      - name: Add RISC-V GCC to PATH
        run: echo "$GITHUB_WORKSPACE/.tools/riscv-gcc/bin" >> $GITHUB_PATH

      - name: Build riscv-tests and programs
        run: |
          export PATH="$PWD/.tools/riscv-gcc/bin:$PATH"
          make -C sw all

      # Golden ISS: unit tests, official rv32ui-p-* compliance, example programs, GNU cross-check.
      - name: Golden ISS tests
        run: python -m pytest sim/golden -q
        env:
          REQUIRE_RISCV_TESTS: '1'   # a missing build is a failure, not a skip

      - name: Lint RTL
        run: bash scripts/lint.sh

      # Unit suites per module, then the single-cycle core in lockstep with the golden ISS over
      # every riscv-tests image and example program. Each suite has its own SIM_BUILD (see run.sh).
      - name: cocotb - unit suites
        run: bash sim/run.sh unit

      - name: cocotb - single-cycle core lockstep vs ISS
        run: bash sim/run.sh lockstep
        env:
          REQUIRE_RISCV_TESTS: '1'

      - name: cocotb - 5-stage core lockstep vs ISS (hazard-free programs)
        run: bash sim/run.sh pipe

      # The iCE40 top level runs fib on the pipeline and prints 6765 over its UART (decoded in simulation).
      - name: cocotb - FPGA top prints fib over UART
        run: bash sim/run.sh fpga