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Unify execution scopes and add NVIDIA thread backend - #37

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plancherb1 merged 11 commits into
mainfrom
feature/nvidia-thread-backend
Aug 31, 2026
Merged

Unify execution scopes and add NVIDIA thread backend#37
plancherb1 merged 11 commits into
mainfrom
feature/nvidia-thread-backend

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@plancherb1 plancherb1 commented Aug 30, 2026

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Summary

  • add cuSOLVERDx thread-scope LAPACK implementations under glass::nvidia::thread::
  • make NVIDIA execution scope explicit (block, warp, or thread) and remove the ambiguous bare NVIDIA re-export
  • replace the flat advisor family with one glass::recommend<op, T, dims...>() query returning implementation family, execution scope, and legal launch packing
  • generate paired MathDx-enabled and native-only placement tables from the same captures, independent of include order
  • validate every NVIDIA-thread ladder winner with independent valid inputs and fail closed when timing intervals cannot resolve the dispatch margin
  • centralize target-SM selection, normalize advisor operation names and GEMM dimension order, and remove obsolete API machinery
  • migrate examples, tests, tuning tools, README, Sphinx docs, and agent guidance to the unified model

Breaking API changes

  • glass::nvidia::op becomes glass::nvidia::{block,warp,thread}::op
  • backend and suggested_* become family, scope, execution_plan, and recommend()
  • advisor names use op::potrf and op::ldlt_solve
  • rectangular GEMM advice uses conventional (M, N, K) order

The native bare glass::op face retains its block-scope calling contract and measured in-kernel body dispatch.

Timing methodology

The five-contender main ladder remains the broad throughput sweep. Because its in-place solver operands are restored once per trial, a separate confirmation harness gives every timed launch an independent valid system. That confirmation is a veto only: it can reject a provisional NVIDIA-thread winner but cannot promote one, and it fails closed when the observed three-trial intervals do not resolve the 5% dependency margin.

The raw ladder selects NVIDIA thread in 17/132 RTX 5090 cells and 19/132 Orin cells. The valid-input gate retains 14/132 and 15/132, respectively. Both confirmation captures were taken in quiet windows and are provenance-pinned by SHA-256 in the tuning documentation and paper evidence manifest.

Validation

  • signed, all-fresh eight-shard GPU receipt: 4,735/4,735 passed, no carried shards
  • strict receipt verification: signature, source fingerprint, commit ancestry, expected skips, and release no-carry policy all pass
  • documented-overload API coverage: 665/665 (100%), including 38 call sites requiring overload-level matching
  • declared behavioral correctness obligations: 21/21 (100%)
  • shard-scope closure: all called overload definitions are fingerprinted by their assigned shard
  • focused NVIDIA-thread CUDA coverage: 67/67 on RTX 5090 and 66/66 on Orin
  • examples: 19/19 compile and run
  • Sphinx documentation builds with warnings as errors
  • CMake configure/build check passes
  • sm_120 resource canary exactly matches the pinned 18-kernel baseline with zero spill/stack growth

An isolated post-change quick ladder dry-run completed successfully but showed excessive within-run timing spread (76 rows above the 5% margin), so it was rejected as retuning evidence and made no table changes. The shipped placements use the pinned repeated ladder captures plus the independent-valid-input veto described above.

@plancherb1
plancherb1 merged commit 43e42ab into main Aug 31, 2026
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