[Feat][Ascend] Add fused RotateQuant backend

[Big2Wheel]

What this PR does / why we need it

Adds an optional Huawei Ascend implementation of quantize_and_rotate_rowwise using torch_npu.npu_rotate_quant and integrates it into the Ascend ConvRot INT8 linear path.

The backend:

• registers the capability only when npu_rotate_quant is available;
• validates dtype, shape, group size, device, and deterministic-rounding requirements;
• supports FP16/BF16, batched inputs, and non-contiguous inputs;
• falls back to the existing _rotate_activation + npu_dynamic_quant path for unsupported runtimes or shapes;
• avoids an extra scale-clamp kernel in the internal INT8 linear hot path while preserving the public API's positive-scale contract.

Relationship to the other Ascend PRs

• Depends on [Feat][Ascend] Add Ascend INT8 quantization backend #151, which introduces the base Ascend backend and quantization capabilities.
• Depends on [Feat][Ascend] Add Ascend INT8 linear backend #153, which introduces the Ascend INT8 linear and ConvRot integration point. This branch is stacked directly on the latest [Feat][Ascend] Add Ascend INT8 linear backend #153 branch.
• Does not depend on [Feat][Ascend] Add Ascend RoPE and RMS-RoPE backend #154. The RoPE/RMS-RoPE backend is orthogonal and can be reviewed or merged independently.

Once #151 and #153 are merged, this PR can be rebased onto main, leaving only the RotateQuant-specific commits.

Performance and memory

Measured on one Ascend 910B3 with real Z-Image activation shapes:

Shape	Eager API	Ascend RotateQuant	Reduction
[32, 3840]	0.487 ms	0.174 ms	64.3%
[8192, 3840]	1.337 ms	0.207 ms	84.6%
[32, 10240]	0.466 ms	0.169 ms	63.7%
[8192, 10240]	2.945 ms	0.457 ms	84.5%

NPU profiling at [8192, 3840] confirms that aclnnMatmul + aclnnDynamicQuantV2 is replaced by aclnnRotateQuant, reducing the combined device time by 18.05% across ten iterations.

An alternating AB/BA Z-Image INT8 workflow test found no statistically meaningful end-to-end latency change; generated PNGs were pixel-identical. The fused operator uses additional temporary workspace: approximately 60 MiB at [8192, 3840] and 160 MiB at [8192, 10240] relative to the separate path.

Does this PR introduce any user-facing change?

Yes. Eligible quantize_and_rotate_rowwise calls and ConvRot Ascend INT8 linear calls automatically use the fused NPU operator. Unsupported configurations retain the existing fallback behavior.

How was this patch tested?

• Ascend 910B3 operator correctness against the eager reference for FP16 and BF16.
• Group sizes 16, 64, and 256.
• Batched, all-zero-row, non-contiguous, and asymmetric-rotation inputs.
• Capability selection, unsupported-shape decline, missing-operator fallback, and INT8 linear integration tests.
• Caller-provided zero tensor-wise scales for FP16 and BF16, matching eager quantization semantics.
• Fixed-seed Z-Image INT8 workflow: baseline and fused outputs were pixel-identical.
• Wan2.2 14B BF16 smoke test completed successfully and made zero npu_rotate_quant calls.
• Focused tests: 55 passed.
• Full post-rebase suite: 660 passed, 1603 skipped, 1 warning.
• ruff check, ruff format --check, and git diff --check passed.

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📝 Walkthrough

Walkthrough

The pull request adds an optional Huawei Ascend backend. It registers when torch-npu and an Ascend device are available, implements INT8 quantization, dequantization, ConvRot, and linear operations, updates backend selection, and adds NPU-focused tests and documentation.

Changes

Ascend backend

Layer / File(s)	Summary
Availability and registry integration comfy_kitchen/__init__.py, comfy_kitchen/backends/ascend/__init__.py, comfy_kitchen/registry.py, tests/conftest.py, tests/test_backends.py, tests/test_ascend_backend.py	The package detects torch-npu and Ascend device support, registers available capabilities, prioritizes ascend, and validates backend selection and device reporting.
INT8 quantization and dequantization comfy_kitchen/backends/ascend/__init__.py, README.md, tests/test_ascend_backend.py	The backend adds tensorwise, rowwise, rotated rowwise, and dequantization operations. Validation restricts dtypes, scales, shapes, group sizes, and stochastic rounding. Tests compare NPU results with the eager backend.
Dynamic INT8 linear execution comfy_kitchen/backends/ascend/__init__.py, tests/test_ascend_backend.py	int8_linear applies activations, optional ConvRot processing, NPU quantization, npu_quant_matmul, scaling, bias, and output reshaping. Tests cover batched inputs, activations, fallback paths, and invalid parameters.

Sequence Diagram(s)

sequenceDiagram
  participant BackendRegistry
  participant ascend
  participant torch_npu
  participant NPUResult
  BackendRegistry->>ascend: validate INT8 call
  ascend->>torch_npu: execute supported operation
  torch_npu-->>ascend: return NPU tensor and scale
  ascend-->>NPUResult: return backend result

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Suggested reviewers: 0xdeluxa, contentis

Merge Risk: ⚪ Minimal · up to d8dd6

This change enables optional Ascend fused INT8 quantization and rotation while retaining fallbacks for unsupported environments. No concrete current-head merge-blocking risk remains.

🚥 Pre-merge checks | ✅ 2

✅ Passed checks (2 passed)

Check name	Status	Explanation
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.

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Actionable comments posted: 2

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Inline comments:
In `@comfy_kitchen/backends/ascend/__init__.py`:
- Line 241: Update the Ascend quantization path around output_scale and
torch_npu.npu_quantize to replace caller-provided zero scales with the same
finite minimum used by the eager path before division. Preserve nonzero scales
unchanged, and add a regression test covering scale=0 to verify Ascend behavior
matches the eager path.

In `@README.md`:
- Line 34: Update the README capability matrix and support list entries for
quantize_and_rotate_rowwise and int8_linear to match runtime registration: mark
quantize_and_rotate_rowwise as conditional on torch_npu.npu_rotate_quant, add
int8_linear’s Ascend support as conditional on torch_npu.npu_quant_matmul, and
document both prerequisites wherever the capability checks are listed.

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