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Directed fadd rounding is off by one ulp at a max-finite midpoint

Status: Open.

#330 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 24, 2026

RV32 AMOCAS.D is rejected although Zacas defines register-pair semantics

Status: Open.

#329 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 24, 2026

mip MTIP and MEIP writes incorrectly replace platform-pending state

Status: Open.

#328 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 24, 2026

RISC-V privileged fences and MRET ignore the current privilege level

Status: Open.

#327 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 24, 2026

The c.lui rd=x0 HINT code point is rejected as a reserved encoding

Status: Open.

#321 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 22, 2026

The legal vfmv.v.f encoding is rejected as an illegal instruction

Status: Open.

#320 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 22, 2026

vcompress.vm accepts a misaligned destination register group

Status: Open.

#319 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 22, 2026

cbo.zero faults report the aligned block base in mtval instead of rs1

Status: Open.

#318 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 22, 2026

FP instructions and FP CSRs are not gated on mstatus.FS

Status: Open.

#317 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 22, 2026