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[should rebase & merge] 2 fixes about A/D update #279

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Merged
poemonsense merged 2 commits into from
Sep 22, 2026
+17 −12
Merged

[should rebase & merge] 2 fixes about A/D update #279

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c4448af
TLB: apply in-order A/D page-fault checks to the OoO path
good-circle Sep 17, 2026
de8d2fd
TLB: gate hardware A/D updates behind EnableUpdateAD (#280)
good-circle Sep 20, 2026
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9 changes: 5 additions & 4 deletions src/main/scala/nutcore/mem/EmbeddedTLB.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -223,13 +223,14 @@ class EmbeddedTLBExec(implicit val tlbConfig: TLBConfig) extends TlbModule{
val hitMask = hitMeta.mask
// hit write back pte.flag
val hitinstrPF = WireInit(false.B)
val hitWB = hit && (!hitFlag.a || !hitFlag.d && req.isWrite()) && !hitinstrPF && !(loadPF || storePF || io.pf.isPF())
val enableUpdateAD = Settings.get("EnableUpdateAD")
val hitWB = if (enableUpdateAD) hit && (!hitFlag.a || !hitFlag.d && req.isWrite()) && !hitinstrPF && !(loadPF || storePF || io.pf.isPF()) else false.B
val hitRefillFlag = Cat(req.isWrite().asUInt, 1.U(1.W), 0.U(6.W)) | hitFlag.asUInt
val hitWBStore = RegEnable(Cat(0.U(10.W), hitData.ppn, 0.U(2.W), hitRefillFlag), hitWB)

// hit permission check
val hitCheck = hit /*&& hitFlag.v */&& !(pf.privilegeMode === ModeU && !hitFlag.u) && !(pf.privilegeMode === ModeS && hitFlag.u && (!pf.status_sum || ifecth))
val hitADCheck = if (Settings.get("FPGAPlatform")) false.B else !hitFlag.a || !hitFlag.d && req.isWrite()
val hitADCheck = if (enableUpdateAD) false.B else !hitFlag.a || !hitFlag.d && req.isWrite()
val hitExec = hitCheck && !hitADCheck && hitFlag.x
val hitLoad = hitCheck && !hitADCheck && (hitFlag.r || pf.status_mxr && hitFlag.x)
val hitStore = hitCheck && !hitADCheck && hitFlag.w
Expand Down Expand Up @@ -318,11 +319,11 @@ class EmbeddedTLBExec(implicit val tlbConfig: TLBConfig) extends TlbModule{
}
}.elsewhen (level =/= 0.U) { //TODO: fix needFlush
val permCheck = missflag.v && !(pf.privilegeMode === ModeU && !missflag.u) && !(pf.privilegeMode === ModeS && missflag.u && (!pf.status_sum || ifecth))
val permAD = if (Settings.get("FPGAPlatform")) false.B else !missflag.a || (!missflag.d && req.isWrite())
val permAD = if (enableUpdateAD) false.B else !missflag.a || (!missflag.d && req.isWrite())
val permExec = permCheck && !permAD && missflag.x
val permLoad = permCheck && !permAD && (missflag.r || pf.status_mxr && missflag.x)
val permStore = permCheck && !permAD && missflag.w
val updateAD = if (Settings.get("FPGAPlatform")) !missflag.a || (!missflag.d && req.isWrite()) else false.B
val updateAD = if (enableUpdateAD) !missflag.a || (!missflag.d && req.isWrite()) else false.B
val updateData = Cat( 0.U(56.W), req.isWrite(), 1.U(1.W), 0.U(6.W) )
missRefillFlag := Cat(req.isWrite(), 1.U(1.W), 0.U(6.W)) | missflag.asUInt
memRespStore := io.mem.resp.bits.rdata | updateData
Expand Down
19 changes: 11 additions & 8 deletions src/main/scala/nutcore/mem/TLB.scala
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Expand Up @@ -411,15 +411,17 @@ sealed class TLBExec(implicit val tlbConfig: TLBConfig) extends TlbModule{
val hitMask = hitMeta.mask
// hit write back pte.flag
val hitinstrPF = WireInit(false.B)
val hitWB = hit && (!hitFlag.a || !hitFlag.d && req.isWrite()) && !hitinstrPF && !(loadPF || storePF || io.pf.isPF())
val enableUpdateAD = Settings.get("EnableUpdateAD")
val hitWB = if (enableUpdateAD) hit && (!hitFlag.a || !hitFlag.d && req.isWrite()) && !hitinstrPF && !(loadPF || storePF || io.pf.isPF()) else false.B
val hitRefillFlag = Cat(req.isWrite().asUInt, 1.U(1.W), 0.U(6.W)) | hitFlag.asUInt
val hitWBStore = RegEnable(Cat(0.U(10.W), hitData.ppn, 0.U(2.W), hitRefillFlag), hitWB)

// hit permission check
val hitCheck = hit /*&& hitFlag.v */&& !(pf.privilegeMode === ModeU && !hitFlag.u) && !(pf.privilegeMode === ModeS && hitFlag.u && (!pf.status_sum || ifecth))
val hitExec = hitCheck && hitFlag.x
val hitLoad = hitCheck && (hitFlag.r || pf.status_mxr && hitFlag.x)
val hitStore = hitCheck && hitFlag.w
val hitADCheck = if (enableUpdateAD) false.B else !hitFlag.a || !hitFlag.d && req.isWrite()
val hitExec = hitCheck && !hitADCheck && hitFlag.x
val hitLoad = hitCheck && !hitADCheck && (hitFlag.r || pf.status_mxr && hitFlag.x)
val hitStore = hitCheck && !hitADCheck && hitFlag.w

io.pf.loadPF := loadPF //RegNext(loadPF, init =false.B)
io.pf.storePF := storePF //RegNext(storePF, init = false.B)
Expand Down Expand Up @@ -506,10 +508,11 @@ sealed class TLBExec(implicit val tlbConfig: TLBConfig) extends TlbModule{
}
}.elsewhen (level =/= 0.U) { //TODO: fix needFlush
val permCheck = missflag.v && !(pf.privilegeMode === ModeU && !missflag.u) && !(pf.privilegeMode === ModeS && missflag.u && (!pf.status_sum || ifecth))
val permExec = permCheck && missflag.x
val permLoad = permCheck && (missflag.r || pf.status_mxr && missflag.x)
val permStore = permCheck && missflag.w
val updateAD = if (Settings.get("FPGAPlatform")) !missflag.a || (!missflag.d && req.isWrite()) else false.B
val permAD = if (enableUpdateAD) false.B else !missflag.a || (!missflag.d && req.isWrite())
val permExec = permCheck && !permAD && missflag.x
val permLoad = permCheck && !permAD && (missflag.r || pf.status_mxr && missflag.x)
val permStore = permCheck && !permAD && missflag.w
val updateAD = if (enableUpdateAD) !missflag.a || (!missflag.d && req.isWrite()) else false.B
val updateData = Cat( 0.U(56.W), req.isWrite(), 1.U(1.W), 0.U(6.W) )
missRefillFlag := Cat(req.isWrite(), 1.U(1.W), 0.U(6.W)) | missflag.asUInt
memRespStore := io.mem.resp.bits.rdata | updateData
Expand Down
1 change: 1 addition & 0 deletions src/main/scala/top/Settings.scala
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Expand Up @@ -37,6 +37,7 @@ object DefaultSettings {
"IsRV32" -> false,

"FPGAPlatform" -> false,
"EnableUpdateAD" -> false,
"EnableILA" -> true,
"EnableDebug" -> false,
"EnableRVC" -> true
Expand Down
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