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feat(1mhz): F_CPU-derived timing + divide-elimination + HSV→RGB LUT + 1MHz-safe ISP clock + CPU_SPEED=1MHz - #158
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… 1MHz-safe ISP clock + CPU_SPEED=1MHz Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
…ion operations and adjusting ISP clock settings
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F_CPU-derived micros; divide-free HSV->RGB LUT; recurring Timer alarm with no AVR divide/modulo in the per-tick hot path -- a small slip re-anchors to now so beats stay evenly spaced (smooth on hardware), while a large gap (timer suspended in a long menu) realigns to the period grid so menu cadence is preserved; play the pattern across the one-tick toggle state so the blink timer keeps its beat; Makefile 1MHz (-B10 + CPU_SPEED=1000000L). All 506 CLI tests pass; the 6 toggle/lock tests were re-recorded to the corrected (no dropped-tick) cadence.
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Co-Authored-By: Claude Opus 4.8 noreply@anthropic.com