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[LLVM] Fix true16 lowering for packed FP8 conversions - #1110
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Patch the pinned LLVM AMDGPU backend to select the real true16 packed FP8/BF8 conversion opcode and the low VGPR half on true16 targets. Apply the patch in local and CI LLVM builds and include all LLVM patch inputs in cache keys. Co-authored-by: vllmellm <190700713+vllmellm@users.noreply.github.com> Co-authored-by: Tan Pin Siang <1716735+tanpinsiang@users.noreply.github.com> Signed-off-by: big_yellow_duck <83417790+big-yellow-duck@users.noreply.github.com>
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Summary
Motivation
llvm.amdgcn.cvt.pk.f32.{fp8,bf8}is selected through a fake16 pseudo because the intrinsic carries two selectable 16-bit words. On targets using real true16 instructions, the MC lowering must explicitly select the true16 opcode and spell a VGPR source as its low half. Without this, packed conversion lowering can produce an invalid or incorrectly encoded instruction.This PR is independent of the FlyDSL scalar
cvt_f32_fp8API addition and is based directly onmainfor focused review.Validation
git apply --checkagainst the pinned LLVM revisione2a39f504fee836e4def9581bed817ecc327b9dcllvm-lit -v llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.llpassesgit clang-format --diffreports no LLVM source formatting changes