[llvm][Skill] Add an LLVM kernel-tuning and verification skill

[Phil-amd]

What

A skill for tuning a FlyDSL kernel through LLVM — picking the compile hint,
function attribute or backend flag — and, crucially, proving the knob reached
codegen before believing any result.

Why a skill, not a doc section

The tree is knob-rich and instrument-poor. A grep of all 17 SKILL.md files
finds no -mllvm, llc, opt or mlir-opt recipe anywhere: nothing could
answer "did this knob apply?". That gap is exactly what let the four inert
knobs removed in #1153 sit unnoticed — a knob that silently does nothing looks
identical to one that works, because an unknown hint still forces a recompile.

So the skill leads with verification, not with a knob list. Every recipe
pairs an artifact grep with a mandatory negative control:

CompilationContext.compile_hints({"waves_per_eU": 4})   # deliberate typo

The assertion must now fail. If it still passes, the instrument is dead — stop
before recording any result. Claims are artifact greps, never timings: gfx950
carries ±14% clock noise, and a knob that changed nothing in the IR cannot have
changed the runtime.

Key points

Per-arch references, because occupancy knobs are not interchangeable.
amdgpu-num-vgpr=64 yields 128 registers on gfx942/gfx950 (silently doubled via
hasGFX90AInsts) but exactly 64 on gfx1250; max occupancy is 8 waves/SIMD on
CDNA versus 16 on gfx1250. Each file leads with that arch's silent failure — for
gfx1250, -mattr=+wavefrontsize64 emits a zero-instruction object with exit
code 0 and no diagnostic.

Two scripts, each proven against a positive and a negative control:
llvm_knob_check.py separates cl::opt from function attribute from missing, so
a flag is checked against the LLVM that will actually compile; llvm_ir_attrs.py
tabulates or diffs per-kernel attributes from an IR dump.

Documented as correct, not as a limitation: FlyDSL raising on gfx1250's
legacy s_waitcnt is right — that intrinsic aborts llc there (rc=134) while
compiling fine on gfx950.

Cross-references added to the four sibling skills that lead here; nothing
discovers a skill automatically. flydsl-kernel-authoring also carried two
mis-attributions about the dead opts= lane, corrected in passing.

Testing

Every [source] claim re-verified line by line against the pinned LLVM
(e2a39f504), and every [measured] one by running llc — each with a
positive control established before any negative was recorded. Both scripts
re-run against their controls after every edit. check_repo.py (including the
API-drift gate) and the style gate pass on this branch.