Verilog implementation of an integer square root FSM and dual M9K RAM system on the Intel MAX10 FPGA, verified in ModelSim and demonstrated on the DE10-Lite board.
🧮 Integer Square Root & Dual RAM — Intel MAX10 FPGA (DE10-Lite)
A Verilog implementation of an integer square root circuit and dual M9K RAM system on the Intel MAX10 FPGA. The square root unit uses a six-state FSM-controlled datapath that computes floor(√N) by iteratively subtracting successive odd integers. Both designs were verified in ModelSim and demonstrated on the DE10-Lite board.
🛠️ Technologies
- Verilog HDL – RTL and behavioral design
- Intel Quartus Prime 19.1 – Synthesis, M9K inference, resource analysis
- ModelSim 19.1 – Functional simulation and waveform verification
- DE10-Lite (Intel MAX10 FPGA) – Target hardware platform
- M9K Block RAM – Dedicated embedded memory blocks on MAX10
✨ Features
- Integer Square Root: Computes floor(√N) for 8-bit inputs using iterative odd-integer subtraction controlled by a six-state FSM
- Dual RAM: Two independent 16x4 M9K RAM modules with shared address and data inputs, independently writable via a select switch
- ModelSim Verification: All 16 test vectors verified against expected floor square root values with pass/fail transcript output
- 7-Segment Display: Input value and square root result displayed live on HEX0–HEX3 of the DE10-Lite board
- Hardware Debouncing: Debouncer module added to eliminate switch bounce at 50 MHz for reliable Start signal detection
- M9K Inference: Both designs confirmed to correctly infer M9K blocks via Quartus Fitter Resource Usage Summary
🏗️ Architecture
Part I – Dual 16x4 RAM:
Two independent 16x4 RAM modules are instantiated using the M9K ramstyle pragma. Both RAMs share the same address and data inputs but are written independently using a select switch (SW[8]). Both outputs are read simultaneously and displayed on HEX0–HEX3 via a hex decoder submodule.
| Signal | Mapping | Description |
|---|---|---|
| SW[9] | Write Enable | Enables write to selected RAM |
| SW[8] | RAM Select | Selects RAM0 or RAM1 for write |
| SW[7:4] | Address | 4-bit RAM address |
| SW[3:0] | Data Input | 4-bit data to write |
| KEY[0] | Clock | Manual clock input |
Part II – Integer Square Root FSM:
The squareroot module uses three always blocks: a sequential state register block, a combinational next-state logic block, and a clocked datapath block. A 16x8 RAM pre-loaded with 16 test vectors feeds the input values.
| State | Name | Description |
|---|---|---|
| S0 | Idle | Wait for Start signal |
| S1 | Load | Latch N, reset odd integer to 1, reset counter to 0 |
| S2 | Subtract | Compute N − odd, set borrow if N < odd |
| S3 | Check | Branch on borrow flag |
| S4 | Increment | Increment counter by 1, odd integer by 2 |
| S5 | Done | Assert Done, output square root result |
✅ Verification
- ModelSim testbench reads 16 binary test vectors using $readmemb
- For each input: asserts Start, waits for Done, prints result, deasserts Start, waits for Done to go low
- All 16 results matched expected floor square root values
- Waveform confirms correct FSM state sequencing, Done assertion timing, and correct OutputSqrt values across all test cases
- M9K usage confirmed: 2 blocks for Part I, 1 block for Part II
💡 What I Learned
- M9K Block RAM Inference: Using the ramstyle pragma to direct Quartus to infer dedicated M9K blocks instead of flip-flops
- FSM Datapath Control: Structuring a three-always-block FSM with separate sequential, combinational, and datapath always blocks
- Switch Bounce Debugging: Diagnosing and fixing switch bounce at 50 MHz by adding a debouncer module with a 20 ms stability window
- Synchronous RAM Read Latency: Understanding the one-cycle delay between address presentation and valid data output on M9K RAMs
- ModelSim Testbench Setup: Using $readmemb to load test vectors from a file and automating pass/fail checking across all test cases
🔧 Tools Required
- Intel Quartus Prime 19.1
- ModelSim 19.1
- DE10-Lite FPGA board
👥 Contributors
Shayan Khosh Keifi — FSM design, all Verilog implementation, ModelSim simulation setup and verification, hardware debouncer debugging, board testing, report writing
George Rizk — Hardware testing and verification on DE10-Lite, state diagram review, board behavior debugging, report writing