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Update examples/README.md and add www/examples/README.md. Build and publish release #133: Commit 594009c pushed by fdxmw
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Update Python dependencies: Build and publish release #132: Commit 55144f9 pushed by fdxmw
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Update CHANGELOG.md for 1.0.3 release. Build and publish release #131: Commit de8e3f8 pushed by fdxmw
3m 55s 1.0.3
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Update CHANGELOG.md for 1.0.3 release. Build and publish release #130: Commit de8e3f8 pushed by fdxmw
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Improve render_trace's ASCII output. Build and publish release #129: Commit 98460e2 pushed by fdxmw
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Add a Makefile to automate screenshot post-processing and update in… Build and publish release #128: Commit df956a7 pushed by fdxmw
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Run all presubmit checks on all tested platforms. Build and publish release #127: Commit 0b9db08 pushed by fdxmw
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Polish GitHub Pages hero: full-span banner, tagline, and section spac… Build and publish release #126: Commit 27b1413 pushed by fdxmw
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Update related projects link in README.md and minor website edits. Build and publish release #125: Commit 5a9d67e pushed by fdxmw
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Deploy GitHub pages from GitHub actions with Sphinx (#489) Build and publish release #124: Commit d4c22cb pushed by fdxmw
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Update concat to immediately concatenate Consts, returning a new … Build and publish release #123: Commit 1a7c606 pushed by fdxmw
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name_scope is a context manager that prepends prefixes to `WireVect… Build and publish release #122: Commit d05a872 pushed by fdxmw
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Remove unnecessary slice (s) LogicNets from sign_extended and `… Build and publish release #121: Commit 96fbc6f pushed by fdxmw
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Fix an output_to_verilog bug where inlined arithmetic expressions m… Build and publish release #120: Commit 9454d07 pushed by fdxmw
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Enable Python test GitHub actions workflow on the windows-latest ru… Build and publish release #119: Commit 82d8858 pushed by fdxmw
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Update CHANGELOG.md for 1.0.2 release. Build and publish release #118: Commit 954dcc1 pushed by fdxmw
3m 46s 1.0.2
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Update CHANGELOG.md for 1.0.2 release. Build and publish release #117: Commit 954dcc1 pushed by fdxmw
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Fix a bug in CompiledSimulation's arm64 multiplication macro. Ena… Build and publish release #116: Commit 6134908 pushed by fdxmw
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Update CHANGELOG.md for 1.0.1 release. Build and publish release #115: Commit c5b83f2 pushed by fdxmw
4m 11s 1.0.1
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Update CHANGELOG.md for 1.0.1 release. Build and publish release #114: Commit c5b83f2 pushed by fdxmw
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Upgrade GitHub actions. Build and publish release #113: Commit 42f9e0a pushed by fdxmw
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Add a warning about signed logic to output_to_verilog's documentati… Build and publish release #112: Commit c8b4971 pushed by fdxmw
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Fix a CompiledSimulation concat bug. (#498) Build and publish release #111: Commit baaf61f pushed by fdxmw
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Apply ConsecutiveSlice optimizations to CompiledSimulation for ~4… Build and publish release #110: Commit 34a4538 pushed by fdxmw
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Clean up FastSimulation's handling of slice (s) LogicNets for ~… Build and publish release #109: Commit 1c9ce1f pushed by fdxmw
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