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WIP: Weak memory support - #487

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hiroki-chen wants to merge 75 commits into
asterinas:mainfrom
hiroki-chen:weak-memory
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WIP: Weak memory support#487
hiroki-chen wants to merge 75 commits into
asterinas:mainfrom
hiroki-chen:weak-memory

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@hiroki-chen

@hiroki-chen hiroki-chen commented Jun 1, 2026

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Ok so the weak memory has been started, and this serves as the triage PR for this feature. The core idea behind this implementation to encode message histories (parameterized by the timerstamp token) for each memory location as ghost states in the concurrent separation logic which allows the caller to open the invariant and obtain the handle to the underlying data.

Basically, the roadmap includes:

  • [x] Modelling the "weak" part (i.e., memory ordering) of the atomic operations. This includes adding new atomic wrapper types from the Rust std library and stopping using the vstd's atomic types at all (since they assume SC). The Verus team is also designing this part.
  • [x] Introduce idomatic macros, types, and interfaces for proving around our customized atomic types.
  • Use the atomic types to prove the RCU reclamation as well as the traversal security properties.
  • Design the OS scheduler/task struct (for sound thread/preemption reasoning).
  • Add several examples.

@hiroki-chen hiroki-chen self-assigned this Jun 1, 2026
@hiroki-chen hiroki-chen added enhancement New general lemmas in vstd_extra, or new tooling features model design Model or specification of system design exec code Proofs about execution code labels Jun 1, 2026
@hiroki-chen

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Reference https://dl.acm.org/doi/pdf/10.1145/3729246 and https://dl.acm.org/doi/pdf/10.1145/3591297

There is no need to model the full C11 semantics (they are even flawed) so we just do an in-order spec.

@hiroki-chen

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Just done the low-level primitives so that we can model the atomic operations for the weak memory model.

@rikosellic

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This will be a huge win if it is correct. I've not read the paper in detail yet, so I'm afraid I will not have enough knowledge to review this PR until next week.

@hiroki-chen

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This will be a huge win if it is correct. I've not read the paper in detail yet, so I'm afraid I will not have enough knowledge to review this PR until next week.

No worries; the core idea is rather simple. I'll keep you updated.

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@hiroki-chen

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Note: somehow blocked by the CPU local/core design. This should be left as is until that part has been merged upstream.

hiroki-chen and others added 2 commits July 31, 2026 00:14
* preliminary CPU core and local models

* formatting

* update names
@rikosellic

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I notice there is also some work about the weak memory model on a Verus branch. verus-lang/verus#2716

@hiroki-chen

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I notice there is also some work about the weak memory model on a Verus branch. verus-lang/verus#2716

Seems that we all follow the same logic.

@hiroki-chen

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This PR is large so in the future I'll split it into small pieces.

@hiroki-chen
hiroki-chen marked this pull request as ready for review August 11, 2026 07:38
@hiroki-chen

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Ready now!

@hiroki-chen

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This one is done @rikosellic @Marsman1996

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