Bluespec, Inc.

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1. Flute Flute Public

   RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

   Bluespec 383 65

2. Piccolo Piccolo Public

   RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

   Verilog 343 54

3. Toooba Toooba Public

   RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

   Verilog 191 53

4. RISCV_gdbstub RISCV_gdbstub Public

   A gdbstub for connecting GDB to a RISC-V Debug Module

   C 30 8

5. AWSteria_Infra AWSteria_Infra Public

   "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)

   VHDL 20 7

6. Accel_AES Accel_AES Public

   Verilog 15 7