FPGA-CNN-Accelerator

Personal Project: A INT8 CNN convolution accelerator implemented on DE10-Nano with RTL verification, HPS control, hardware benchmarks, documentation Initially started off with deciding what size and types to use. Activation: signed INT8, Weight: signed INT8, Product: signed INT16, Accumulator: kernel_sizeinput_channels = 33*3 = 27, Bias = signed IN32, Output: shifted accumulator clamped into INT8

OOP for accelerator:

1. multiply
2. accumulate
3. add bias
4. right shift/quantize
5. clamp into INT8
6. ReLU

accumulate = sum(activation * wieght) biased = accumulate + bias shifted = biased >>> quant_shift; clipped = clamp(shifted, -128, 127) ReLU_out = max(clipped, 0)

Created a software golden model in C and tested to use later to verify results.