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Verilog: support for let expressions with ports#1925

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Verilog: support for let expressions with ports#1925
kroening wants to merge 1 commit into
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kroening/let-ports

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@kroening kroening commented Jun 21, 2026

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Implements macro-like substitution for let constructs with formal arguments (IEEE 1800-2017 A.2.12).

Changes

  • Parser: added action to let_port_item to capture port identifiers
  • Elaboration: stores port names in the let symbol, defers body conversion to call site
  • Expression typechecking: detects let calls and substitutes arguments for port names

Testing

  • Updated let_ports1 test (single port) to expect success
  • Added let_ports2 test with multiple ports and nested let calls

@kroening kroening marked this pull request as draft June 21, 2026 17:13
@kroening kroening force-pushed the kroening/let-ports branch from d0bac03 to a0aff23 Compare June 21, 2026 18:45
@kroening
Verilog: support for let expressions with ports
73d98af 
Implements macro-like substitution for let constructs with formal
arguments (IEEE 1800-2017 A.2.12). At the call site, actual arguments
are substituted for the formal port names in the let body expression.
@kroening kroening force-pushed the kroening/let-ports branch from a0aff23 to 73d98af Compare June 24, 2026 23:11
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