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epic: our own model -- IGLA CODER, HSLM in t27 and the harness, one 27-part map #10024
Description
Goal
One map of what exists, and what does not, before the project has its own model: IGLA CODER (the code model in gHashTag/igla-coder-gpu), HSLM in t27 (the ternary language model that was trained in Zig), and the harness that has to compile, run and show them. Replaces the scattered state in #1032 (closed for lack of close criteria), #1037-#1040, #7778, igla-coder-gpu#28/#38.
The map is a t27 spec, specs/igla/own_model.t27: 27 cells through the T27F topic workflow (specs/t27f/topic_engine.t27 earned_status, checked by specs/t27f/topic_reel.t27). A cell's status is earned from measurements (source, test pass, review, live), never chosen. A cell's percent is a separate estimate with its basis named in the spec's SOURCES.
State on master, 2026-10-18
The values come from specs/igla/own_model.t27 at 82bd5f4 (#10428).
4 published, 22 verified, 1 draft, 0 gaps. Percent, equal weight per cell (a convention, not a measurement): overall 62.
The IGLA board shows the map. GET https://board-production-2dec.up.railway.app/state has a live job own_model with the message "3 published, 22 verified, 1 drafts, 1 gaps; 61%" and 27 cells. It is the event t27c gen-json specs/igla/own_model_board.t27 printed on the Railway lab, posted 2026-10-18 09:10:27 UTC.
Review: #10164, #10179, #10186, #10185 and #10270 were all merged by auto-merge before the reviewer bee approved them. #10273 took back #10270's unbacked claim. #10275 put the seven DELIVER cells to review again, labelled no-auto-merge. REVIEW_ID names review 5561941493, the bee's APPROVE of 014a34d. On the final head 24e9f71 the bee's model approved again, but the bee posted NEEDS_PERSON because the head changes two .trinity/seals/ files (t27c seal output from the lab). It merged over that hold, under the owner's standing instruction; the reason is on the PR.
Parts
| # | Part | Status | % | Next |
|---|---|---|---|---|
| 1 | Corpus, 11.7B tokens of code | verified | 60 | |
| 2 | BPE 32K tokenizer with FIM | verified | 70 | |
| 3 | Size ladder 13M to 100M | verified | 80 | |
| 4 | t27 bench, 466 items | verified | 80 | |
| 5 | MultiPL-E pass@1 harness | verified | 60 | |
| 6 | IGLA CODER specs in t27 | verified | 100 | |
| 7 | tern-tc-9m on Hugging Face | published | 50 | |
| 8 | A public 100M model | published | 90 | |
| 9 | Scale-up to 0.5-1.5B | published | 30 | tern-tc-500m on Hugging Face, reviewed in #10428. Card (HF 945bf79, igla-coder-gpu#45): HumanEval pass@1 0.95%, 2/164 solved, below the 100m; t27 bench partial (279/466), mixed |
| 10 | HSLM experiment ledger | verified | 100 | |
| 11 | HSLM Zig trainer | verified | 100 | reference only |
| 12 | The one checkpoint left | verified | 20 | best runs wiped by EXP-002 |
| 13 | Loss: cross entropy | verified | 80 | |
| 14 | Optimizers: sgd, adam, lamb | verified | 65 | |
| 15 | Forward pass | verified | 95 | |
| 16 | Backward pass | verified | 75 | |
| 17 | Ternary straight-through | verified | 55 | |
| 18 | Data loader and checkpoint I/O | verified | 40 | |
| 19 | tc engine, C and PyTorch parity | verified | 70 | |
| 20 | FPGA: 8 tokens on the AX7203 | verified | 15 | |
| 21 | Live IGLA board | published | 60 | |
| 22 | Ternary matvec in t27 | verified | 40 | |
| 23 | ML specs that compile | verified | 100 | |
| 24 | Heap and file I/O in t27c | verified | 60 | |
| 25 | t27c --backend ml |
verified | 30 | |
| 26 | Full model on FPGA, DDR3 | draft | 10 | head read 2769 MB/s (#10248). Next: weights in DDR3, a forward pass from them, a review |
| 27 | This map | verified | 50 |
Closing the epic needs cell 26 (the model computing from DDR3, reviewed).
Boundary
- In:
specs/igla/own_model.t27and the sub-issues below. Each sub-issue changes.t27only, and updates the map's measurements and tests in the same PR. - Out: no new hand-written non-t27 code; no model-quality claim beyond the numbers in the spec's
SOURCES; nothing posted externally. - A cell's status changes only when its measurement changes; its percent only with a named source.
Close criteria
Every cell in specs/igla/own_model.t27 is VERIFIED or PUBLISHED, measured on the lab, and the IGLA board shows the map from the spec.
Sub-issues
- the map spec itself
- Implement part 1 of 1 of the empty bodies in specs/nn/hslm.t27 (4 functions) #7778 forward pass bodies in
specs/nn/hslm.t27 - make the nine
specs/igla/coder/*.t27compile - revive the board loop: igla: repost the own_model board event from master on a Railway cron (Closes #10321) #10324 runs the Railway cron
own-model-board(17 */6 * * *), which repostsgen/json/igla/own_model_board.jsonfrom master; the 2026-10-18 12:21 UTC fire returned ok and the board shows "3 published, 22 verified, 1 drafts, 1 gaps; 61%" (igla-coder-gpu#38, the wider Queen executor, stays open) - spec(igla): own_model -- take back the REVIEWED claim #10270 merged without a review #10272 take back the unreviewed REVIEWED claim (PR spec(igla): own_model -- take back the REVIEWED claim #10270 merged without a review (Closes #10272) #10273, merged)
- spec(igla): own_model -- the seven DELIVER cells reviewed, 3 published / 22 verified #10269 the seven DELIVER drafts reviewed (7, 8, 16, 17, 18, 25, 27), PR spec(igla): own_model -- put the seven DELIVER cells to review, auto-merge off (Closes #10269) #10275, merged
- cell 9: tern-tc-500m trained, carded, published (Hugging Face playra/tern-tc-500m @ 7f203b66, card igla-coder-gpu @ 510a22c7; igla cell 9: tern-tc-500m grounded, then reviewed (Closes #10420) #10428 grounds LIVE[8] and REVIEWED[8], review 5563369440 on the final head; merged 82bd5f4. The card now carries HumanEval and a partial t27 bench, HF commit 945bf79, igla-coder-gpu#45)
- cell 26: the model computing from DDR3 on the AX7203, reviewed
Activity
spec(igla): own_model.t27 -- the 27-part map of our own model (Closes #…
spec(hslm): nn/hslm and hslm/forward_pass compile and pass; own_model…
spec(nn): ternary STE, training step and data/checkpoint layout in t27 (
spec(ml): train_slice_model -- main() trains 20 steps and writes a ch…
fpga(ax7203): DDR3 head read measured at 2769 MB/s, cell 26 grounded …
fpga(ax7203): DDR3 head read measured at 2769 MB/s -- own_model cell …
igla cell 9: tern-tc-500m grounded, then reviewed (Closes #10420) (#1…