fpga(ax7203): take back the reds rc_filter brought to master (TOK_REAL, hex_digit, elab ratchet) #10294

Goal

Take back the master reds that #10278 (the cpphdl RC low-pass on the AX7203) brought in when issue-gate auto-merged it at its first commit: duplicate-bodies (hex_digit), fpga-lint (function real / input real rejected by yosys as TOK_REAL) and the elaboration ratchet (rc_filter_ax7203 NEW, not in the baseline).

Boundary

• specs/fpga/rc_filter_ax7203.t27: the f64 reference helpers (fabs, volts, be_charge) move into the tests, and PLLE2_ADV's real-valued params become comptime_float. The clocked machine is unchanged.
• .trinity/seals/fpga_FpgaRcFilter.json: resealed for the new spec.
• tools/duplicate_bodies_baseline.txt: hex_digit 2 blessed (the copy in ddr3_head_bandwidth.t27 is deliberate: t27b bitstream specs are self-contained).
• tools/elab_baseline.txt: a row for rc_filter_ax7203 with a KNOWN GAP note, and 0 rows for three modules that reached master without one.
• Not in scope: ddr3_head_bandwidth.t27 (another owner); the other duplicate-body groups on master; teaching t27c gen-verilog primitive instances (compiler code).

Scenarios

• Given the new spec, When t27c runs its tests on the Railway lab, Then 10/10 pass with 0 vacuous and the seal saves.
• Given the new spec, When t27b verilog emits it, Then the logic is the same as the board-verified build of fpga(ax7203): cpphdl RC low-pass as a t27 spec, measured on the board (Closes #10276) #10278 and the new bitstream prints PASS on the board.
• Given the branch, When tools/dupe_scan.py runs, Then hex_digit is no longer reported.
• Given the branch, When tools/check_elab_ratchet.py runs, Then rc_filter_ax7203 is no longer NEW.

Requirements

• FR-001: The spec MUST NOT declare a module-level f64 fn or f64 param (t27c emits them as Verilog real, which yosys rejects).
• FR-002: The tests MUST keep the same bounds as before (3 LSB against f64, cpphdl's 0.992396 V at 5 us, step-halving convergence).
• FR-003: The bitstream from the new spec MUST be re-verified on the AX7203 before merge.

Success Criteria

• Lab: 10/10 tests, 0 vacuous; seal spec_hash equals the committed spec.
• Board: consecutive receipt lines all PASS with A=FE0DA3 B=1EE92 S=77EDFF0295C3FE9E C=4B0.
• duplicate-bodies no longer names hex_digit; the elaboration ratchet no longer names rc_filter_ax7203.

Close criteria

• The PR merges and the three named reds no longer come from this spec.