t27b ratchet: rc_filter_ax7203 blocked on comptime_float PLL params since #10296 #10313

Goal

t27b-native-ratchet is red on master (run 39110248563, 30b4363) with specs/fpga/rc_filter_ax7203.t27: ledger pass, now blocked: type comptime_float. #10278 recorded the spec in the ledger as a t27b pass. #10296 then changed PLLE2_ADV's CLKIN1_PERIOD and REF_JITTER1 from f64 to comptime_float, so that t27c gen-verilog would not emit input real, and t27b rejects a comptime_float parameter. Since #10302, gen-verilog skips t27b bitstream specs (any const *_LOC : str), so the reason for that change no longer applies.

Boundary

• specs/fpga/rc_filter_ax7203.t27: the two PLLE2_ADV parameter types go back to f64. Its seal .trinity/seals/fpga_FpgaRcFilter.json is regenerated if the spec hash moves.
• Not in scope:
  • specs/fpga/ddr3_head_bandwidth.t27, the other UNEXPECTED FAILURE (ExprIdentifier(undeclared));
  • the 12 UNLISTED rows;
  • t27b itself.

Scenarios

• Given the branch, When the t27b corpus runs on specs/fpga/rc_filter_ax7203.t27, Then it reports pass.
• Given the branch, When the reference runs the spec's tests, Then 10 of 10 pass.
• Given the branch, When t27b verilog lowers the spec, Then the PLL instance carries the same parameter values as the build verified on the board.

Requirements

• FR-001: The clocked machine and the tests MUST be unchanged; only the two parameter types change.
• FR-002: The seal MUST be regenerated by the tool, not hand-edited.

Success Criteria

• The ratchet no longer lists rc_filter_ax7203 as UNEXPECTED FAILURE.

Close criteria

• The PR merges, and master's t27b-native-ratchet no longer names rc_filter_ax7203.