fpga(ax7203): ddr3_head_bandwidth lowers under t27b again -- its state-reading pins become registers #10327

Goal

t27b-native-ratchet is red on master (run 39105096338) with specs/fpga/ddr3_head_bandwidth.t27: ledger pass, now blocked: ExprIdentifier(undeclared). The row is "t27b": "pass" in docs/reports/t27b_expectations.json, so every PR that merges master inherits the red check.

Measured on the Railway lab at master 7912660 (t27b built there; the x86 lab has no t27b JIT, so CI's arm64 runs the tests): t27b test --blockers reports unknown name st, verdict and hb. They come from the three module-level pub const nets uart_tx, led_2 and led_3, which read var registers. t27b's test path cannot read a var from a net. This is the same shape that #10278 hit and fixed in rc_filter, where the outputs became pub var registers set in on_clock. The error is blamed on the line of the first fn, not on the nets.

Boundary

• specs/fpga/ddr3_head_bandwidth.t27: uart_tx, led_2 and led_3 become pub var registers set at the top of on_clock, which gets one more parameter, core_uart_tx, the core's UART output (t27b binds a parameter named <instance>_<output> to that instance's output). Its 32 calls in the spec's tests get the extra argument. One new spec test covers the three registered pins. Its seal .trinity/seals/fpga_FpgaDdr3HeadBandwidth.json is regenerated.
• Not in scope:
  • the 12 UNLISTED rows;
  • t27b itself;
  • the LiteDRAM core, the pinout, and the traffic and receipt logic.

Scenarios

• Given the branch, When t27b test --blockers runs on the spec, Then it reports no unsupported construct (on x86 it stops at the JIT message, after lowering).
• Given the branch, When the reference runs the spec's tests, Then all 12 pass with 0 vacuous.
• Given the branch, When t27b verilog lowers the spec, Then the module differs from master's only in the three pins: output reg instead of output wire, assigned in the clocked process.

Requirements

• FR-001: The pinout, the LiteDRAM instance, the write and read traffic, the checksum, the divider and the receipt MUST be unchanged.
• FR-002: The seal MUST be regenerated by the tool on the lab, not hand-edited.
• FR-003: The ledger row MUST stay pass; max_not_pass MUST NOT move.

Success Criteria

• The ratchet no longer lists ddr3_head_bandwidth as UNEXPECTED FAILURE.

Close criteria

• The PR merges, and master's t27b-native-ratchet no longer names ddr3_head_bandwidth.