master red: trinity_fpga_adapter emits a 2^32-1 bit width; 20 blessed duplicate helper bodies to merge #10382

Two required CI checks went red on master at b2fbb75 (#10370) and stayed red through 5152eee and 9969315, so every open PR inherited them. #10373 turned both green by adding ledger lines by hand and with dupe_scan.py --bless. This issue repairs the causes behind those lines instead of leaving them as debt.

Goal

1. "Verilog widths (absurd-width ledger)": specs/port/tools/trinity_fpga_adapter.t27 emitted reg [4294967295:0] c; in self_check. The cause is a local var c: Consts: Consts is a struct of four str fields, a str has no bit representation, so the packed width is 0 and range_decl prints [0 - 1 : 0] as 2^32-1. The spec reached the gate only when seals: verdict-blocked specs compile and seal; 11 refused specs fixed, 30 blocked ones listed (Refs #8314) #10370 made it compile (it could not before), which is why the ledger never held it. Fix the spec so no such local exists and drop the ledger line that claw: suggest_feed -- a spec that t27c fmt would reformat becomes a suggestion review on the PR (Closes #10365) #10373 added.
2. "duplicate-bodies": seals: verdict-blocked specs compile and seal; 11 refused specs fixed, 30 blocked ones listed (Refs #8314) #10370 (verdict-blocked specs made to compile) and the specs that landed around it wrote small byte helpers again in each file. claw: suggest_feed -- a spec that t27c fmt would reformat becomes a suggestion review on the PR (Closes #10365) #10373 blessed 20 new names. De-duplicate the groups that have a natural home through use of one spec and shrink the ledger by exactly what is removed; bless nothing blindly.

Boundary

• specs/port/tools/trinity_fpga_adapter.t27
• tools/verilog_width_baseline.txt
• tools/duplicate_bodies_baseline.txt
• the specs whose duplicate bodies are merged (listed in the pull request)
• .trinity/seals/*.json and gen/ files of the specs above, written by t27c only

User Scenarios

• Given master after this change, when python3 tools/check_verilog_widths.py --require runs with a release t27c, then specs/port/tools/trinity_fpga_adapter.t27 is not reported and the ledger no longer names it.
• Given master after this change, when python3 tools/dupe_scan.py runs, then it exits 0 and each group merged in this change is gone from, or smaller in, tools/duplicate_bodies_baseline.txt.
• Given a merged spec, when t27c test-report runs on it and on each spec that imports it, then every test still passes and no seal is stale.

Requirements

• FR-001: trinity_fpga_adapter.t27 MUST NOT declare a local or parameter whose type has zero packed width.
• FR-002: The self_check result and every existing test of the spec MUST be unchanged.
• FR-003: The width ledger MUST lose the trinity_fpga_adapter line, and MUST NOT gain any line.
• FR-004: A duplicate group MUST be merged only when the importing spec still lowers alone through use_resolve and its tests pass; otherwise it stays in the ledger with the reason in the pull request.
• FR-005: The duplicate ledger MUST be edited only to remove or shrink groups that were really merged.
• FR-006: Only .t27 files, seals and generated files change; no hand-written foreign code.

Success Criteria

• tools/check_verilog_widths.py --require prints OK and names no new or stale spec.
• tools/dupe_scan.py prints "ok" and tools/duplicate_bodies_baseline.txt is smaller than at master.
• t27c test-report is green for every touched spec and check_seal_currency.py reports 0 stale.
• Both checks are green on the pull request.