analog M1b: board receipts for the linear cell -- series RLC and 5-node RC ladder on the AX7203 #10496

Goal

M1b of #10486: run the linear cell of #10487 (specs/analog/linear.t27) on the ALINX AX7203 for two circuits, the series RLC and the 5-node RC ladder, and record a board receipt for each, as M0 (#10276) did for the RC low-pass.

Boundary

• New board tops under specs/fpga/ (one per circuit), lowered by t27b verilog; their seals and ledger handling as M0 (fpga(ax7203): cpphdl RC low-pass as a t27 spec, measured on the board #10276, fpga(build): skip t27b-only bitstream specs in fpga-build, not teach gen-verilog a second lowering (rc_filter_ax7203, ddr3_head_bandwidth) #10300).
• No hand-written Verilog or XDC; pins are pin attributes in the spec.
• Board work on the AX7203 bench (skills board-eye, bench-agent); flashing with openFPGALoader as fpga/HARDWARE_SSOT.md says.

Scenarios

• Given the RLC board top, When it runs on the AX7203, Then every UART line reads PASS with the A/B/S values the spec's tests derive.
• Given the 5-node ladder board top, When it runs, Then every UART line reads PASS.
• Given each circuit's negative-control bitstream, When it runs, Then the lines read the predicted FAIL values.

Requirements

• FR-001: Each receipt MUST report LUT, FF, DSP, BRAM and Fmax.
• FR-002: Each board top MUST compute the same samples as the spec's tests.

Success Criteria

• Two UART captures with at least 100 consecutive PASS lines each, attached to the PR.
• Each board top closes timing at 100 MHz (Fmax >= 100 MHz in the nextpnr report).
• Each negative-control bitstream prints FAIL with the predicted values.

Part of #10486