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analog M3b: IHP SG13G2 PSP103 tables per corner from ngspice, plugged into the M3a solver -- inverter against ngspice #10516

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#10778
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analog M3b: IHP SG13G2 PSP103 tables per corner from ngspice, plugged into the M3a solver -- inverter against ngspice#10516
#10778

Description

@gHashTag
gHashTag
opened on Oct 18, 2026

Goal

M3 of #10486, second half: replace M3a's square-law table (#10515) with current (and charge) tables generated from the foundry model, IHP SG13G2 sg13_lv_nmos / sg13_lv_pmos (PSP103 via OSDI), one table set per corner (mos_tt, mos_ff, mos_ss, mos_fs, mos_sf), and check the inverter against ngspice with the same model. Tables are loaded into BRAM at run time (one bitstream per topology, not per corner; W4 in docs/analog/competitors.md).

Reference environment (the one Symbiotic EDA used for its golden SAR deck)

uberWAVE's wp2-parser/golden/Dockerfile: ngspice with OSDI, OpenVAF-Reloaded, IHP-Open-PDK libs.tech/ngspice/install.py (compiles libs.tech/verilog-a/*.va into libs.tech/ngspice/osdi/*.osdi with openvaf-r), spinit loading psp103.osdi, psp103_nqs.osdi, r3_cmc.osdi, mosvar.osdi, ngbehavior=hsa. On this Mac: ngspice-47 (Homebrew) is installed; OpenVAF-Reloaded v24.0.2mob ships a macos-aarch64 build.

Boundary

  • Table generation runs ngspice (an external tool, like yosys) with DC sweeps of Id(Vgs, Vds) and terminal charges per corner, W/L as in the SAR deck's inverter; the conversion of ngspice output into t27 table constants is a t27 program (no hand scripts committed).
  • specs/analog/ table spec(s) per corner (or one spec with a corner index), the inverter run against ngspice transient.
  • Every table records the PDK commit and the corner.

Scenarios

  • Given the tt tables, When interpolated at 10,000 random bias points, Then relative error vs ngspice+PSP103 <= the bound stated (proposal 1 %, floor 1e-9 A).
  • Given the inverter with tt tables, When run, Then propagation delay is within the stated bound of ngspice tt.
  • Given the ss tables loaded into the tt run, When compared with ngspice tt, Then the check fails (negative control).

Requirements

  • FR-001: Tables MUST name the PDK commit, the corner, W, L and the grid.
  • FR-002: Value and derivative MUST come from the same table (consistent gm, gds).

Success Criteria

  • Five corners tabulated; the tt inverter within bounds; one negative control failing; t27c test-report 0 vacuous.

Part of #10486

Activity

  1. gHashTag commented on Oct 18, 2026

    @gHashTag
    gHashTag
    on Oct 18, 2026
    OwnerAuthor

    Notes from M3a (PR #10518) that this issue inherits:

    • The first table cell above Vth. A bilinear chord over a square law reads exactly twice the law in the first cell above threshold, on any uniform grid (relative error 1.0 there, 0.2000 from the second cell on). With PSP103 the subthreshold region is not zero, so the grid near Vth needs a finer or nonuniform spacing, or a transformed table (for example sqrt(Id) or log(Id)) with the bound stated per region.
    • Lowering. t27b verilog lowers the scalar step and the Newton division (exit 0), but refuses board_step on two constructs: a slice parameter and array indexing (ExprIndex, exit 2). The table read (node_at) has to become a ROM / BRAM read for the board -- which is also the run-time loadable table of the design (W4).
    • Error budget. The largest of the three errors in M3a is discretization (dt vs dt/2: 27.2 mV at dt = 10 ns), not arithmetic (29 nV) or table (0.43 mV). M3b should state dt per circuit from the fastest pole, not reuse 10 ns.

  2. gHashTag commented on Oct 18, 2026

    @gHashTag
    gHashTag
    on Oct 18, 2026
    OwnerAuthor

    Environment facts for the reference setup (IHP SG13G2 with ngspice), to avoid a silent wrong model:

    • Pin the PDK commit and record it in every table: the reference golden runs used IHP-Open-PDK v0.3.0-1046-g21133f21 (commit 21133f21, 8 Sep 2026).
    • ngspice must load psp103.osdi (not only psp103_nqs.osdi, r3_cmc.osdi and mosvar.osdi), and for the MIM capacitors also cap_cmomi.osdi and cap_cmomf.osdi; without psp103.osdi every IHP MOS instance fails with "Unknown model type psp103va". Put the six osdi lines in the .spiceinit the table generator uses and assert in the run log that they loaded.
    • Compile the Verilog-A models with openvaf-r (OpenVAF-Reloaded): it reproduces the shipped models exactly; OpenVAF 23.5 gives the MOS varactor about 3.5 % less capacitance.
    • ngspice 47 is what the reference used and what is installed on the bench Mac.
    • First corner checks worth having before the full tables: the SAR inverter delay and the dynamic comparator decision time across the five corners and -40 / 27 / 125 C, against ngspice.
  3. gHashTag
    added a commit that references this issue on Oct 19, 2026

    analog: mos_psp103.t27 -- IHP SG13G2 PSP103 tables for five corners f…

    6f21327
  4. gHashTag
    closed this as completedin #10778on Oct 19, 2026
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