analog M4: the SAR ADC of the golden deck -- capacitive DAC, dynamic comparator, sampling switch, SAR logic, then the whole converter against ngspice #10524

Goal

M4 of #10486, re-targeted on 2026-10-18 by the partner (Symbiotic EDA): the ring oscillator is a digital block and not relevant to them; the ADC is. The acceptance circuit is the SAR ADC of uberWAVE's golden deck (wp2-parser/golden/top.spice, xschem, IHP SG13G2, GPL-2.0, used at run time, never vendored) and the reference waveform is the ngspice result of that deck (SAR_top_tb_tran.raw, ASCII RAW; a 1 GB variant is in uberWAVE's release). The deck runs tran 0.1n 16u with a 62.5 kHz differential sine on Vinp/Vinn and a 2 MHz sample clock.

Decomposition (each a sub-issue when it starts)

• M4a -- capacitive DAC (Diff_cap_DAC): binary-weighted IHP cap_cmim MIM capacitors (9 x 9 um units, 1, 2, 4, 8, ... per bit) switched by Bit_1..Bit_10. Linear between switch events: the M1 cell (analog M1: linear state-space cell -- any linear R/C/L circuit, fixed step, folded to x' = Mx + Nu #10487) plus charge conservation at each switch. Check: the top-plate voltage for every code against ngspice.
• M4b -- dynamic comparator (dynamic_comparator): a StrongARM-style latch (sg13_lv_nmos / pmos, m = 6 to 36). Regenerative, so the hard part: the M3 solver (analog M3a: nonlinear table-device cell -- CMOS inverter with a tabulated square-law MOS, backward Euler and a fixed Newton count, against cpphdl #10515) with IHP tables (analog M3b: IHP SG13G2 PSP103 tables per corner from ngspice, plugged into the M3a solver -- inverter against ngspice #10516), and the decision time vs input difference against ngspice; metastability near 0 V input is reported, not hidden.
• M4c -- sampling switch (tracking_switch): a bootstrapped NMOS switch, 7 transistors. Check: tracking error and charge injection against ngspice.
• M4d -- SAR logic and clocks (SAR_logic, clock_gen, dff, nand, nor3, delay_cell, tgate): transistor-level digital. First at switch/gate level extracted from the netlist, with the extraction checked against ngspice edges; the analog blocks above stay at device level (mixed-level emulation).
• M4e -- the whole converter: the output code of every conversion in the 16 us run equals the code ngspice produces from the same deck (read from the golden RAW), and the analog nodes VDP/VDN stay within the stated bound.

Boundary

• Specs under specs/analog/ per block and one top for the converter; board tops under specs/fpga/; the netlist is read by the t27o SPICE front end (analog M2a: SPICE front end for t27o -- parse, flatten and inventory an ngspice netlist, or refuse with the line #10509), not re-typed.
• No claim about ENOB, INL/DNL or speed until measured; no claim that the digital part is emulated at transistor level when it is gate level.

Scenarios

• Given the golden deck and the RAW, When M4e runs, Then every conversion's code equals ngspice's.
• Given the DAC alone, When each code is applied, Then the top-plate voltage matches ngspice within the stated bound.
• Given a comparator input of 1 mV, When it is clocked, Then the decision matches ngspice and the decision time is reported.

Requirements

• FR-001: Each block MUST be checked against ngspice with the same IHP models and corner before it is composed.
• FR-002: The level of each block (device, switch, gate) MUST be named in every report.

Success Criteria

• M4e: 100 % of the conversion codes in the golden 16 us run match ngspice (count stated).
• Each of M4a..M4d has a test-report with 0 vacuous and an ngspice comparison with a named bound.

Part of #10486