verilog widths: why_card and deps_card stdin edge buffers are exact 2^21-bit widths, not an accident #10774

Boundary

tools/verilog_width_baseline.txt only. No spec, compiler or checker change.

Master's Verilog widths (absurd-width ledger) check (tools/check_verilog_widths.py --require) has been red since #10719 and #10725 merged. It flags two specs as NEW:

• specs/t27f/why_card.t27: 2097151
• specs/t27f/deps_card.t27: 2097151

(seen on PR #10387, job 117853026643). Every open PR inherits this red.

Scenarios

• Cause, measured on the Railway lab with t27c gen-verilog: in each spec the only absurd signal is reg [2097151:0] edges;. It comes from main's stdin buffer var edges : [262144]u8. 262144 * 8 = 2,097,152 bits, so [2097151:0] is exact. It is not an underflow, and no mask is leaking into a width.
• That buffer holds the whole t27c use-edges --specs-dir specs output. On master today that output is 2,490 lines and 138,986 bytes, already more than 131,072 bytes (2^20 bits, the checker's threshold). Shrinking the buffer under the threshold would make both cards refuse the real corpus, so resizing cannot fix the spec.
• Both mains are host-side text plumbing: they read fd 0 with std.c.read, call std.c.getenv, and print an ffmpeg filter graph to stderr. They have no hardware form. specs/claw/suggest_feed.t27 (claw: pr-suggestions -- t27c fmt keeps comments, and a changed spec becomes a suggestion review from TRI CLAW #10365, ledgered in claw: suggest_feed -- a spec that t27c fmt would reformat becomes a suggestion review on the PR (Closes #10365) #10373) is already in the ledger for the same [262144]u8 -> [2097151:0] arithmetic, and specs/t27f/token_floor.t27 (ledgered in master red: three inherited checks fixed at their cause (Closes #10439, Closes #10440, Closes #10441) #10443) is the t27f precedent.

Requirements

• Add one ledger row per spec, with its exact arithmetic and the measured edge-list size, in the same form as the suggest_feed.t27 and token_floor.t27 rows.

Criteria

• The width checker run with --require against a master-built t27c on the lab prints OK: ... known, 0 new.
• t27c test on both specs still passes.

Requirements

FR-001: Add a ledger row for specs/t27f/why_card.t27 to tools/verilog_width_baseline.txt with its exact arithmetic (262144 * 8 = 2097152 bits, width 2097151:0) and the measured edge-list size (138,986 bytes), following the same form as the existing suggest_feed.t27 and token_floor.t27 rows. MUST

FR-002: Add a ledger row for specs/t27f/deps_card.t27 to tools/verilog_width_baseline.txt with its exact arithmetic (262144 * 8 = 2097152 bits, width 2097151:0) and the measured edge-list size (138,986 bytes), following the same form as the existing suggest_feed.t27 and token_floor.t27 rows. MUST

Success Criteria

• tools/check_verilog_widths.py --require prints OK: ... known, 0 new. and exits 0
• t27c test specs/t27f/why_card.t27 exits 0
• t27c test specs/t27f/deps_card.t27 exits 0
• Only tools/verilog_width_baseline.txt is modified