analog M4d-b: the delay cell is history dependent -- repeated clkc falls 83-127 % late in the gate-level model #10848

Goal

Follow-up of M4d (#10754, PR #10845). The gate-level SAR logic matches ngspice + PSP103 on the CK edge order, on the delay cell's eight trim settings and on the first clkc edges, but in the repeated self-timed cycles the delay cell's falling edge comes 83-127 % late (model 13.2 ns, ngspice 7.0 ns): its input has not settled when Valid rises again (1.05 V), so a table of settled delays cannot follow it. The CK edges also come about 17 % early overall. Model the delay cell's state (a one-node RC-like internal state on the M1/M3 path, or a delay as a function of the input's distance from its rail) so the repeated edges fall within the bound of the first ones.

Requirements

• FR-001: The repeated clkc falling edges within 15 % of ngspice (the bound the first edges already meet), from the same PSP103 decks.
• FR-002: The CK edge error explained or reduced below 10 %.

Scenarios

• Given 11 Valid pulses at the golden deck's pace, When the model runs, Then every clkc fall is within the bound.

Boundary

• specs/analog/sar_logic.t27 and its decks.

Success Criteria

• Repeated clkc falls within 15 %; t27c test-report 0 vacuous; the SL_REPEAT_F_BOUND_PM = 1300 bound removed.

Part of #10754

Success Criteria

• t27c test specs/analog/sar_logic.t27 --repeat 11 exits 0 with all repeated clkc falls within 15 % of ngspice reference
• t27c test-report specs/analog/sar_logic.t27 shows 0 vacuous tests and CK edge error below 10 %
• The constant SL_REPEAT_F_BOUND_PM = 1300 removed from specs/analog/sar_logic.t27