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HSLM backward elementwise PTX: RMSNorm, ReLU, softmax-CE backward and the f32-to-int8 quantise step, with CPU references #10932
The HSLM backward GEMMs (dX, dW) already have int8 tensor-core PTX written by t27 (specs/igla/coder/hslm_bwd_ptx.t27, merged in #10855, issue #10847). The rest of the backward pass of specs/ml/train_hslm.t27 is elementwise and still CPU-only. This issue adds the PTX emitters and CPU references for those elementwise steps in a new spec, on the same skeleton and text-pin style as hslm_bwd_ptx.t27. The GPU run is a separate step on a 4090 pod; the bees need only t27c.
Refs #10847. Out of bounds (do not edit): specs/ml/train_hslm.t27, specs/igla/coder/hslm_bwd_ptx.t27, any Rust source under bootstrap/src.
Given the new spec, when t27c test-report runs it, then every test passes: each kernel's PTX text is pinned (length and key lines), and each CPU reference matches hand-computed cases in the layout train_hslm.t27 uses.
Given a quantised activation row, when the f32-to-int8 per-row quantise reference runs, then the int8 values and the scale reproduce the f64 input within the stated bound.
Requirements
FR-001: The spec MUST give a PTX emitter plus an f64 CPU reference for each of: RMSNorm backward, ReLU backward, softmax-cross-entropy backward, and the f32 to int8 per-row and per-column quantise step that feeds hslm_dx_s8 and hslm_dw_s8.
FR-002: Each reference MUST follow the index layout and the formulas of the matching function in specs/ml/train_hslm.t27 (read it; do not edit it).
FR-003: The spec MUST state the error bound of the quantise step and test it against an f64 reference.
FR-004: The spec MUST hold at least one test or invariant per kernel (law L4), be ASCII-only (L3), and have no vacuous test.
FR-005: Shared helpers MUST be reused from specs/igla/coder/hslm_bwd_ptx.t27 by use, not copied (the duplicate-body ratchet fails on a copy).
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