[spec] elab baseline: add systolic 0 -- master fpga-conformance red since #11094 made systolic elaborate #11099

Goal

Add systolic 0 to tools/elab_baseline.txt so the fpga-conformance gate ("Elaboration errors may fall, never rise") is green on master again.

Why this matters

#11094 fixed the Verilog emitter (Closes #10780), so specs/.../systolic.t27 now generates Verilog that iverilog elaborates with 0 errors. Before the fix it did not elaborate and the gate never listed the module. The gate reads a module that is generated but absent from the baseline as NEW and fails, even at 0 errors. Master's fpga-conformance has been red on fcb3bc5 for this reason alone: elaboration errors: 214 (baseline 214), NEW systolic: 0 errors, not in baseline. Every open PR inherits the red.

Source of truth

tools/check_elab_ratchet.py --update-baseline, run on a t27c built from master (compiler.rs digest e34e1b174c96..., identical to master's FROZEN_HASH). The verify run reproduces CI's numbers exactly (214 vs 214, same NEW row). The update changed two lines: systolic 0 (kept) and the iverilog calibration comment 12.0 -> 13.0 (dropped: CI runs iverilog 12.0, and every other count is identical under 13.0, so the calibration stays what CI measures).

Deliverable

One added line in tools/elab_baseline.txt: systolic 0.

Done when

fpga-conformance is green on master and on PRs that merge master.

How to verify

python3 tools/check_elab_ratchet.py     # needs iverilog and target/release/t27c

Expected: elaboration errors: 214 (baseline 214), no NEW row.

Risks

None: the ratchet value is 0, the floor. If systolic regresses later, the gate fails as designed.

Links

#11094, #10780, #11097 (the separate Linux seal re-save that keeps spec-guards and coverage red).