analog M5e: the SAR inverter delays into 20 fF from the PSP103 tables with charge, the last NOT MODELLED row of the inverter block #11350

Part of the analog epic (see #10486). After #11325 the external team's per-block checks give 7 PASS, 0 FAIL, 6 NOT MODELLED of 13 blocks. The inverter block is NOT MODELLED only for one row: its fall and rise delays into 20 fF (the report: 81 ps and 100 ps; the limit 1 to 500 ps); its switching threshold already passes (0.6892 V against 0.69 V).

The tt PSP103 tables with their drain and gate charge (M3c, mos_psp103.t27, mos_table.t27) already give the 500 fF inverter's 50 % delays within 0.02 % of ngspice backward Euler on a 100 ps grid. 20 fF needs a much finer step and the SAR inverter's own device sizes from the converter netlist (W, L and m as the existing comparator decks state them).

Only .t27 (skill only-t27); decks under specs/analog/decks/.

Requirements

• FR-001: The inverter of the SAR netlist (its W, L and m; bulks as the netlist has them) into 20 fF MUST be stepped on the tt tables with the devices' charge (and the Vsb axis of analog M3e: a source-to-bulk axis on the PSP103 log tables, so the tgate Ron with its bulks on the rails is within 0.09 percent of ngspice #11288 where a source is not at its bulk), on a step fine enough that halving it moves each delay by less than 1 %.
• FR-002: The fall and rise 50 % delays MUST be compared with our own ngspice-47 run of the same cell into 20 fF (container jobs on the reference host, at most 6 of its 12 cores, removed afterwards), the gap printed in percent; the row is PASS only inside the report's limit AND within 10 % of ngspice.
• FR-003: accept_sar.t27 and docs/analog/accept-sar-2026-10-20.md recompute the inverter block and the totals.
• FR-004: a negative control: the charge removed, the delay is refused by the 10 % bar.

Boundary

• specs/analog/ (a new spec for the 20 fF run if needed; mos_table.t27, mos_psp103.t27 only by extension)
• specs/analog/accept_sar.t27
• specs/analog/decks/
• docs/analog/

Success Criteria

• t27c test-report on every changed spec prints FAIL 0 and vacuous passes 0
• the inverter delay rows are PASS, or the measured gap is written and the rows stay NOT MODELLED with the reason

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