analog M3f: the 13-transistor comparator with charge on the AX7203 as a parallel machine -- resources per transistor and step time, measured

Part of the analog epic (see #10486). The owner's word 2026-10-20: the comparator on the board comes next. It answers the external team's question of how many transistors an FPGA can emulate (asked about a Kintex-7 420T): today the only measured design is the 2-transistor PSP103 inverter on the AX7203 (1426 + 170 LUT, 1219 FF, 4 RAMB36 + 1 RAMB18, 0 DSP, a bit-serial machine, 1700 to 1960 clocks per 100 ps step). A 13-transistor circuit as a parallel machine gives resources per transistor and a step time that are measured, not guessed.

The circuit: the 27 C dynamic comparator with its output inverter, the devices' own charge and the body effect (specs/analog/sar_comparator_q.t27, PR #11325: decision time within 1.75 % of ngspice).

Only .t27 (skill only-t27): the machine is a .t27 board top generated to RTL; no hand-written HDL.

Requirements

Phase 1 (spec, a T27 OS pane lane):

FR-001: an integer (fixed-point) step of the comparator in the arithmetic the board will run (the exact-integer table reads of mos_table.t27 and the charge step), as functions a board top can call; a test shows its decision time at +2 mV and -2 mV within 0.5 % of the f64 model of sar_comparator_q.t27 and the sign right.
FR-002: the per-step work is written as independent device evaluations (13 current-and-charge reads that do not depend on each other within an iteration) and one node update, so a board top can run the evaluations in parallel.

Phase 2 (board, after a slot on the AX7203):

FR-003: a board top (specs/fpga/) that runs the step with the device evaluations in parallel (DSP multipliers allowed), its receipt lines equal to the spec's integer run at every step (as psp103_inv_ax7203.t27 does), and a negative control.
FR-004: the report: LUT, FF, RAMB, DSP after routing, Fmax, and clocks per step, so resources per transistor and the step time are measured numbers; no speed claim.

Boundary

specs/analog/ (a new integer comparator spec)
specs/fpga/ (phase 2)
docs/analog/

Success Criteria

Phase 1: t27c test-report FAIL 0 and vacuous passes 0; t27b test --check exit 0; the integer decision times within 0.5 % of the f64 model
Phase 2: every receipt line PASS on the board; the resource table in the doc

🤖 Generated with Claude Code

Closed by the issue-shape gate (specs/policy/issue_shape.t27, #7498): an issue must have the template's sections. Edit the body; an edit that passes reopens it.

missing: ## User Scenarios -- at least one Given/When/Then scenario

analog M3f phase 1: the comparator step in board arithmetic, bit for …

Phase 2 status, 2026-10-20 21:30 (UTC+7). Partial. Nothing has been synthesized, placed or loaded yet, so there are no resource, Fmax or receipt numbers for the comparator.

Pushed on branch lane/cmp-int-11380-p2 (18f037d):

specs/fpga/sar_cmp_qi_unit.t27 models one device evaluation (qi_eval of sar_comparator_qi.t27) as a clocked unit.
Products go through a two-product multiply-add, the tables are read from a ROM one clock after the address register, and the unit serves 20 stamp words per device.
It lowers with t27b at rung 1 (t27b verilog rung 1: T27 OS decision specs lower to RTL (Closes #11375) #11376). Its one test passes under t27b and t27c test-report: 4 runtime asserts, 0 vacuous.
It is NOT yet checked bit for bit against sq_i, sq_qt, sq_slope and qi_eval.

Measured along the way:

Rung 1 lets a board spec index imported table consts. With a tied reset the ROMs map to block RAM. A ROM read twice in one module is mapped twice, so each table needs one read port per clock.
Three of the log and charge tables took 30 RAMB18 + 1 RAMB36.
A 32x32 multiply placed on 4 DSP48E1, and fasm2frames ran clean on a 100 MHz probe. That design was not loaded.
Word widths needed by the 8x8 solve over the +2 mV run:

Quantity	Bits
Elimination factor	20
Matrix entries	30
Elimination product	49
Back-substitution product, sums, numerator	50
Divisor	29
Quotient	24
Stamp registers	33

So a 32x32 multiplier and a divider with a 50-bit dividend cover it.

Not measured, extrapolated from the three tables: about 54 RAMB36 per device kind's table set. Four units with private tables would take about 216 RAMB36, roughly 60 % of the 200T's 365. Sharing the tables between units is the design question this raises.

Next, a smaller step (phase 2a): test the unit bit for bit against the spec, then synthesize ONE unit for its resources after place and route. That gives the per-device cost on the AX7203. The 8x8 solve, the top, the receipt and the board run follow as phase 2b. Both wait until this Mac's free disk is back above 8 GB (it was under 4 GB at 21:22).

merge master into the M3f phase 2a lane for #11380 (Closes #11380)

analog M3f phase 2a: the comparator unit is bit for bit the spec -- a…

analog M3f phase 2a: the comparator unit with its table ROMs placed a…

analog M3f phase 2a: the unit calls sq_qw of sar_comparator_q instead…

analog M3f phase 2a: the comparator device evaluation as a clocked un…

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analog M3f: the 13-transistor comparator with charge on the AX7203 as a parallel machine -- resources per transistor and step time, measured #11380

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analog M3f: the 13-transistor comparator with charge on the AX7203 as a parallel machine -- resources per transistor and step time, measured #11380

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